Symbol: INTC_WRITE
sys/arch/arm/gemini/gemini_icu.c
126
INTC_WRITE(sc, GEMINI_ICU_IRQ_ENABLE, sc->sc_enabled_mask);
sys/arch/arm/gemini/gemini_icu.c
132
INTC_WRITE(sc, GEMINI_ICU_IRQ_CLEAR,
sys/arch/arm/gemini/gemini_icu.c
143
INTC_WRITE(sc, GEMINI_ICU_IRQ_ENABLE, sc->sc_enabled_mask);
sys/arch/arm/gemini/gemini_icu.c
149
INTC_WRITE(sc, GEMINI_ICU_IRQ_CLEAR,
sys/arch/arm/gemini/gemini_icu.c
201
INTC_WRITE(sc, GEMINI_ICU_IRQ_ENABLE, sc->sc_enabled_mask);
sys/arch/arm/gemini/gemini_icu.c
202
INTC_WRITE(sc, GEMINI_ICU_IRQ_CLEAR, irq_mask);
sys/arch/arm/gemini/gemini_icu.c
222
INTC_WRITE(sc, GEMINI_ICU_IRQ_TRIGMODE, sc->sc_edge_mask);
sys/arch/arm/gemini/gemini_icu.c
223
INTC_WRITE(sc, GEMINI_ICU_IRQ_TRIGLEVEL,
sys/arch/arm/gemini/gemini_icu.c
259
INTC_WRITE(sc, GEMINI_ICU_IRQ_ENABLE, 0);
sys/arch/arm/gemini/gemini_icu.c
260
INTC_WRITE(sc, GEMINI_ICU_IRQ_CLEAR, 0xffffffff);
sys/arch/arm/gemini/gemini_icu.c
261
INTC_WRITE(sc, GEMINI_ICU_IRQ_TRIGMODE, 0);
sys/arch/arm/gemini/gemini_icu.c
262
INTC_WRITE(sc, GEMINI_ICU_IRQ_TRIGLEVEL, 0xffffffff);
sys/arch/arm/imx/imx31_icu.c
109
INTC_WRITE(avic, IMX31_INTDISABLEL, irq_mask);
sys/arch/arm/imx/imx31_icu.c
111
INTC_WRITE(avic, IMX31_INTDISABLEH, irq_mask);
sys/arch/arm/imx/imx31_icu.c
118
INTC_WRITE(avic, IMX31_INTDISNUM, irq_base);
sys/arch/arm/imx/imx31_icu.c
139
INTC_WRITE(avic, priority_reg, v);
sys/arch/arm/imx/imx31_icu.c
187
INTC_WRITE(avic, IMX31_NIMASK, ipl);
sys/arch/arm/imx/imx31_icu.c
199
INTC_WRITE(avic, IMX31_NIMASK, saved_nimask);
sys/arch/arm/imx/imx31_icu.c
89
INTC_WRITE(avic, IMX31_INTENABLEL, irq_mask);
sys/arch/arm/imx/imx31_icu.c
91
INTC_WRITE(avic, IMX31_INTENABLEH, irq_mask);
sys/arch/arm/imx/imx31_icu.c
98
INTC_WRITE(avic, IMX31_INTENNUM, irq_base);
sys/arch/arm/imx/imx51_tzic.c
176
INTC_WRITE(tzic, TZIC_ENSET(group), irq_mask);
sys/arch/arm/imx/imx51_tzic.c
187
INTC_WRITE(tzic, TZIC_ENCLEAR(group), irq_mask);
sys/arch/arm/imx/imx51_tzic.c
227
INTC_WRITE(tzic, TZIC_PRIORITY(priority_offset), reg);
sys/arch/arm/imx/imx51_tzic.c
267
INTC_WRITE(tzic, TZIC_INTCNTL, INTCNTL_NSEN_MASK|INTCNTL_NSEN|INTCNTL_EN);
sys/arch/arm/imx/imx51_tzic.c
269
INTC_WRITE(tzic, TZIC_PRIOMASK, SW_TO_HW_IPL(IPL_NONE));
sys/arch/arm/imx/imx51_tzic.c
272
INTC_WRITE(tzic, TZIC_SYNCCTRL, 0x00);
sys/arch/arm/imx/imx51_tzic.c
277
INTC_WRITE(tzic, TZIC_INTSEC(i), 0xffffffff);
sys/arch/arm/imx/imx51_tzic.c
281
INTC_WRITE(tzic, TZIC_ENCLEAR(i), 0xffffffff);
sys/arch/arm/sunxi/sunxi_intc.c
100
INTC_WRITE(sc, INTC_MASK_REG(group), ~sc->sc_enabled_irqs[group]);
sys/arch/arm/sunxi/sunxi_intc.c
110
INTC_WRITE(sc, INTC_EN_REG(group), sc->sc_enabled_irqs[group]);
sys/arch/arm/sunxi/sunxi_intc.c
111
INTC_WRITE(sc, INTC_MASK_REG(group), ~sc->sc_enabled_irqs[group]);
sys/arch/arm/sunxi/sunxi_intc.c
190
INTC_WRITE(sc, INTC_IRQ_PEND_REG(group), pend);
sys/arch/arm/sunxi/sunxi_intc.c
253
INTC_WRITE(sc, INTC_EN_REG(i), 0);
sys/arch/arm/sunxi/sunxi_intc.c
254
INTC_WRITE(sc, INTC_MASK_REG(i), ~0U);
sys/arch/arm/sunxi/sunxi_intc.c
255
INTC_WRITE(sc, INTC_IRQ_PEND_REG(i),
sys/arch/arm/sunxi/sunxi_intc.c
259
INTC_WRITE(sc, INTC_PROTECT_REG, INTC_PROTECT_EN);
sys/arch/arm/sunxi/sunxi_intc.c
99
INTC_WRITE(sc, INTC_EN_REG(group), sc->sc_enabled_irqs[group]);
sys/arch/arm/ti/am18xx_intc.c
152
INTC_WRITE(sc, esr_reg, mask);
sys/arch/arm/ti/am18xx_intc.c
162
INTC_WRITE(sc, ecr_reg, mask);
sys/arch/arm/ti/am18xx_intc.c
178
INTC_WRITE(sc, cmr_reg, cmr);
sys/arch/arm/ti/am18xx_intc.c
194
INTC_WRITE(sc, reg, pending);
sys/arch/arm/ti/am18xx_intc.c
227
INTC_WRITE(sc, AM18XX_AINTC_GER, 0);
sys/arch/arm/ti/am18xx_intc.c
228
INTC_WRITE(sc, AM18XX_AINTC_HIER, 0);
sys/arch/arm/ti/am18xx_intc.c
231
INTC_WRITE(sc, AM18XX_AINTC_CR, 0);
sys/arch/arm/ti/am18xx_intc.c
235
INTC_WRITE(sc, AM18XX_AINTC_ECR1 + 4 * i, 0xFFFFFFFF);
sys/arch/arm/ti/am18xx_intc.c
236
INTC_WRITE(sc, AM18XX_AINTC_SECR1 + 4 * i, 0xFFFFFFFF);
sys/arch/arm/ti/am18xx_intc.c
240
INTC_WRITE(sc, AM18XX_AINTC_HIER, AM18XX_AINTC_HIER_IRQ);
sys/arch/arm/ti/am18xx_intc.c
243
INTC_WRITE(sc, AM18XX_AINTC_GER, AM18XX_AINTC_GER_ENABLE);
sys/arch/arm/ti/ti_omapintc.c
114
INTC_WRITE(sc, group, INTC_MIR_CLEAR, irq_mask);
sys/arch/arm/ti/ti_omapintc.c
117
INTC_WRITE(sc, 0, INTC_CONTROL, INTC_CONTROL_NEWIRQAGR);
sys/arch/arm/ti/ti_omapintc.c
126
INTC_WRITE(sc, group, INTC_MIR_SET, irq_mask);
sys/arch/arm/ti/ti_omapintc.c
163
INTC_WRITE(sc, 0, INTC_CONTROL, INTC_CONTROL_NEWIRQAGR);
sys/arch/arm/ti/ti_omapintc.c
260
INTC_WRITE(sc, n, INTC_MIR_SET, 0xffffffff);