IA64_RR_BASE
*bshp = addr + IA64_RR_BASE(7);
*bshp = addr + IA64_RR_BASE(6);
ia64_set_rr(IA64_RR_BASE(6), (6 << 8) | (LOG2_ID_PAGE_SIZE << 2));
ia64_set_rr(IA64_RR_BASE(7), (7 << 8) | (LOG2_ID_PAGE_SIZE << 2));
if (va >= IA64_RR_BASE(6)) {
ia64_set_rr(IA64_RR_BASE(i),
ia64_set_rr(IA64_RR_BASE(i),
ia64_set_rr(IA64_RR_BASE(5), (5 << 8) | (PAGE_SHIFT << 2) | 1);
(IA64_RR_BASE(IA64_PBVM_RR) + IA64_REGION_GAP_EXTEND)
(IA64_RR_BASE(IA64_PBVM_RR + 1) - IA64_PBVM_PGTBL_MAXSZ)
#define IA64_BACKINGSTORE IA64_RR_BASE(4)
#define VM_MAX_ADDRESS ((vaddr_t) IA64_RR_BASE(5))
#define VM_INIT_KERNEL_ADDRESS IA64_RR_BASE(IA64_VM_MINKERN_REGION + 1)
#define VM_MAX_KERNEL_ADDRESS ((vaddr_t) (IA64_RR_BASE(6) - 1))
#define IA64_PHYS_TO_RR6(x) ((x) | IA64_RR_BASE(6))
#define IA64_PHYS_TO_RR7(x) ((x) | IA64_RR_BASE(7))
ia64_set_rr(IA64_RR_BASE(6), (6 << 8) | (28 << 2));
ia64_set_rr(IA64_RR_BASE(7), (7 << 8) | (28 << 2));
__asm __volatile("mov cr.ifa=%0" :: "r"(IA64_RR_BASE(7)));
__asm __volatile("ptr.d %0,%1" :: "r"(IA64_RR_BASE(7)), "r"(28<<2));
__asm __volatile("ptr.i %0,%1;;" :: "r"(IA64_RR_BASE(7)), "r"(28<<2));
ia64_set_rr(IA64_RR_BASE(6), (6 << 8) | (28 << 2));
ia64_set_rr(IA64_RR_BASE(7), (7 << 8) | (28 << 2));
__asm __volatile("mov cr.ifa=%0" :: "r"(IA64_RR_BASE(7)));