HWRITE4
HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_PGS_GEN1);
HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_PGS_GEN2);
HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF,
HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_LINK_TRAIN_EN);
HWRITE4(sc, PCIE_RC_CONFIG_LCSR, HREAD4(sc, PCIE_RC_CONFIG_LCSR) | PCIE_LCSR_RETRAIN);
HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG,
HWRITE4(sc, PCIE_LM_VENDOR_ID, PCI_VENDOR_ROCKCHIP);
HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG,
HWRITE4(sc, PCIE_LM_RCBAR, PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS);
HWRITE4(sc, PCIE_RC_CONFIG_THP_CAP, status);
HWRITE4(sc, PCIE_RC_PCIE_LCAP, status);
HWRITE4(sc, PCIE_ATR_OB_ADDR0(0), 20 - 1);
HWRITE4(sc, PCIE_ATR_OB_ADDR1(0), 0);
HWRITE4(sc, PCIE_ATR_OB_DESC0(0), PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID);
HWRITE4(sc, PCIE_ATR_OB_DESC1(0), 0);
HWRITE4(sc, PCIE_ATR_OB_ADDR0(region), 32 - 1);
HWRITE4(sc, PCIE_ATR_OB_ADDR1(region), 0);
HWRITE4(sc, PCIE_ATR_OB_DESC0(region), type | PCIE_ATR_HDR_RID);
HWRITE4(sc, PCIE_ATR_OB_DESC1(region), 0);
HWRITE4(sc, PCIE_ATR_IB_ADDR0(2), 32 - 1);
HWRITE4(sc, PCIE_ATR_IB_ADDR1(2), 0);
HWRITE4(sc, PCIE_ATR_OB_ADDR0(0),
HWRITE4(sc, PCIE_ATR_OB_DESC0(0),
HWRITE4(sc, PCIE_RC_NORMAL_BASE + reg, data);
HWRITE4(sc, PCIE_ATR_OB_ADDR0(0),
HWRITE4(sc, PCIE_ATR_OB_DESC0(0),
HWRITE4(sc, PCIE_CLIENT_INT_MASK,
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
HWRITE4(sc, PMA_CMN_CTRL1, 0x830);
HWRITE4(sc, XCVR_DIAG_LANE_FCM_EN_MGN(i), 0x90);
HWRITE4(sc, TX_RCVDET_EN_TMR(i), 0x960);
HWRITE4(sc, TX_RCVDET_ST_TMR(i), 0x30);
HWRITE4(sc, CMN_DIAG_HSCLK_SEL, reg);
HWRITE4(sc, CMN_PLL0_VCOCAL_INIT, 0xf0);
HWRITE4(sc, CMN_PLL0_VCOCAL_ITER, 0x18);
HWRITE4(sc, CMN_PLL0_INTDIV, 0xd0);
HWRITE4(sc, CMN_PLL0_FRACDIV, 0x4a4a);
HWRITE4(sc, CMN_PLL0_HIGH_THR, 0x34);
HWRITE4(sc, CMN_PLL0_SS_CTRL1, 0x1ee);
HWRITE4(sc, CMN_PLL0_SS_CTRL2, 0x7f03);
HWRITE4(sc, CMN_PLL0_DSM_DIAG, 0x20);
HWRITE4(sc, CMN_DIAG_PLL0_OVRD, 0);
HWRITE4(sc, CMN_DIAG_PLL0_FBH_OVRD, 0);
HWRITE4(sc, CMN_DIAG_PLL0_FBL_OVRD, 0);
HWRITE4(sc, CMN_DIAG_PLL0_V2I_TUNE, 0x7);
HWRITE4(sc, CMN_DIAG_PLL0_CP_TUNE, 0x45);
HWRITE4(sc, CMN_DIAG_PLL0_LF_PROG, 0x8);
HWRITE4(sc, TX_PSC_A0(0), 0x7799);
HWRITE4(sc, TX_PSC_A1(0), 0x7798);
HWRITE4(sc, TX_PSC_A2(0), 0x5098);
HWRITE4(sc, TX_PSC_A3(0), 0x5098);
HWRITE4(sc, TX_TXCC_MGNFS_MULT_000(0), 0x0);
HWRITE4(sc, XCVR_DIAG_BIDI_CTRL(0), 0xbf);
HWRITE4(sc, RX_PSC_A0(1), 0xa6fd);
HWRITE4(sc, RX_PSC_A1(1), 0xa6fd);
HWRITE4(sc, RX_PSC_A2(1), 0xa410);
HWRITE4(sc, RX_PSC_A3(1), 0x2410);
HWRITE4(sc, RX_PSC_CAL(1), 0x23ff);
HWRITE4(sc, RX_SIGDET_HL_FILT_TMR(1), 0x13);
HWRITE4(sc, RX_REE_CTRL_DATA_MASK(1), 0x03e7);
HWRITE4(sc, RX_DIAG_SIGDET_TUNE(1), 0x1004);
HWRITE4(sc, RX_PSC_RDY(1), 0x2010);
HWRITE4(sc, XCVR_DIAG_BIDI_CTRL(1), 0xfb);
HWRITE4(sc, PMA_LANE_CFG, PIN_ASSIGN_D_F);
HWRITE4(sc, DP_MODE_CTL, DP_MODE_ENTER_A2);
HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) | USBHC_HR_FHR);
HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_FHR));
HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) | USBHC_HR_FSBIR);
HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_SSE));
HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) &
HWRITE4(sc, USBHC_HIE, USBHC_HIE_RWIE | USBHC_HIE_UPRIE);
HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) | USBHC_HR_FHR);
HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_FHR));
HWRITE4(sc, GENI_TX_FIFO, word);
HWRITE4(sc, GENI_M_IRQ_CLEAR, stat);
HWRITE4(sc, GENI_I2C_TX_TRANS_LEN, cmdlen);
HWRITE4(sc, GENI_M_CMD0, m_cmd);
HWRITE4(sc, GENI_M_IRQ_CLEAR, stat);
HWRITE4(sc, GENI_I2C_RX_TRANS_LEN, buflen);
HWRITE4(sc, GENI_M_CMD0, m_cmd);
HWRITE4(sc, GENI_M_IRQ_CLEAR, stat);
HWRITE4(sc, GENI_I2C_TX_TRANS_LEN, buflen);
HWRITE4(sc, GENI_M_CMD0, m_cmd);
HWRITE4(sc, IPCC_RECV_SIGNAL_CLEAR, reg);
HWRITE4(sc, IPCC_RECV_SIGNAL_ENABLE,
HWRITE4(sc, IPCC_RECV_SIGNAL_DISABLE,
HWRITE4(sc, IPCC_SEND_ID,
HWRITE4(sc, QCSPMI_REG_OBSRVR,
HWRITE4(sc, QCSPMI_REG_CHNLS, SPMI_CHAN_OFF(sc, apid) +
HWRITE4(sc, QCSPMI_REG_CHNLS, SPMI_CHAN_OFF(sc, apid) +
HWRITE4(sc, QCSPMI_REG_CHNLS, SPMI_CHAN_OFF(sc, apid) + SPMI_COMMAND,
HWRITE4(hp, SDHC_CLOCK_CTL,
HWRITE4(hp, SDHC_CLOCK_CTL,
do if ((bits) != 0) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0)
do if ((bits) != 0) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0)
HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR, desc_addr & 0xffffffff);
HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR + 4,
HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr);
HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16));
HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg);
HWRITE4(hp, SDHC_MIX_CTRL, mode |
HWRITE4(hp, SDHC_TRANSFER_MODE, command << 16);
HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16));
HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg);
HWRITE4(hp, SDHC_DMA_ADDR, posaddr);
HWRITE4(hp, SDHC_DMA_ADDR, dm_segs[++seg].ds_addr);
HWRITE4(hp, SDHC_DATA, htole32(*(uint32_t *)data));
HWRITE4(hp, SDHC_DATA, v);
HWRITE4(hp, SDHC_DATA, v);
HWRITE4(hp, SDHC_NINTR_STATUS, xstatus);
HWRITE4(hp, reg, val);
HWRITE4(hp, SDHC_MMC_BOOT, 0);
HWRITE4(hp, SDHC_HOST_CTL, SDHC_USDHC_BURST_LEN_EN |
HWRITE4(hp, SDHC_WATERMARK_LEVEL,
HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16);
HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0);
HWRITE4(hp, i,
HWRITE4(hp, i,
HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0);
HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16);
HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask);
HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask);