HREAD4
status = HREAD4(sc, PCIE_CLIENT_BASIC_STATUS1);
HWRITE4(sc, PCIE_RC_CONFIG_LCSR, HREAD4(sc, PCIE_RC_CONFIG_LCSR) | PCIE_LCSR_RETRAIN);
status = HREAD4(sc, PCIE_LM_CORE_CTRL);
status = HREAD4(sc, PCIE_RC_CONFIG_THP_CAP);
status = HREAD4(sc, PCIE_RC_PCIE_LCAP);
val = HREAD4(sc, PCIE_RC_NORMAL_BASE + reg);
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
reg = HREAD4(sc, CMN_DIAG_HSCLK_SEL);
reg = HREAD4(sc, PMA_CMN_CTRL1);
hr = HREAD4(sc, USBHC_HR);
hr = HREAD4(sc, USBHC_HR);
hr = HREAD4(sc, USBHC_HR);
while (HREAD4(sc, USBHC_HR) & USBHC_HR_FSBIR)
hr = HREAD4(sc, USBHC_HR);
hr = HREAD4(sc, USBHC_HR);
hr = HREAD4(sc, USBHC_UHCRHDA);
hr = HREAD4(sc, USBHC_HR);
hr = HREAD4(sc, USBHC_HR);
stat = HREAD4(sc, GENI_M_IRQ_STATUS);
stat = HREAD4(sc, GENI_RX_FIFO_STATUS);
word = HREAD4(sc, GENI_RX_FIFO);
stat = HREAD4(sc, GENI_TX_FIFO_STATUS);
stat = HREAD4(sc, GENI_M_IRQ_STATUS);
stat = HREAD4(sc, GENI_M_IRQ_STATUS);
stat = HREAD4(sc, GENI_M_IRQ_STATUS);
while ((reg = HREAD4(sc, IPCC_RECV_ID)) != ~0) {
val = HREAD4(sc, QCSPMI_REG_CORE, SPMI_VERSION);
val = HREAD4(sc, QCSPMI_REG_CORE, SPMI_ARB_APID_MAP(sc, i));
val = HREAD4(sc, QCSPMI_REG_CNFG, SPMI_OWNERSHIP_TABLE(sc, i));
reg = HREAD4(sc, QCSPMI_REG_OBSRVR,
reg = HREAD4(sc, QCSPMI_REG_OBSRVR,
reg = HREAD4(sc, QCSPMI_REG_OBSRVR,
reg = HREAD4(sc, QCSPMI_REG_CHNLS, SPMI_CHAN_OFF(sc, apid) +
present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK);
if (ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_SDSTB))
state = HREAD4(hp, SDHC_PRESENT_STATE);
cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE + 0);
cmd->c_resp[1] = HREAD4(hp, SDHC_RESPONSE + 4);
cmd->c_resp[2] = HREAD4(hp, SDHC_RESPONSE + 8);
cmd->c_resp[3] = HREAD4(hp, SDHC_RESPONSE + 12);
cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS)));
do if ((bits) != 0) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0)
do if ((bits) != 0) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0)
(HREAD4(hp, SDHC_MIX_CTRL) & ~SDHC_TRANSFER_MODE_MASK));
posaddr = HREAD4(hp, SDHC_DMA_ADDR);
if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), pmask)) {
*(uint32_t *)data = le32toh(HREAD4(hp, SDHC_DATA));
const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_READ_SHIFT) & SDHC_WATERMARK_READ_MASK;
v = HREAD4(hp, SDHC_DATA);
v = HREAD4(hp, SDHC_DATA);
const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_WRITE_SHIFT) & SDHC_WATERMARK_WRITE_MASK;
uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS);
status = xstatus = HREAD4(hp,
return HREAD4(hp, reg);
HREAD4(hp, SDHC_PRESENT_STATE));
HREAD4(hp, SDHC_CAPABILITIES));
HREAD4(hp, SDHC_MAX_CAPABILITIES));
sdhcver = HREAD4(hp, SDHC_ESDHC_HOST_CTL_VERSION);
caps = HREAD4(hp, SDHC_CAPABILITIES);
caps = sc->sc_caps = HREAD4(hp, SDHC_CAPABILITIES);
caps2 = sc->sc_caps2 = HREAD4(hp, SDHC_CAPABILITIES2);
uint32_t v = HREAD4(hp, i);
r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED);
r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH);