FP_X_UFL
float_flag_underflow = FP_X_UFL,
float_flag_underflow = FP_X_UFL,
float_flag_underflow = FP_X_UFL,
float_flag_underflow = FP_X_UFL,
float_flag_underflow = FP_X_UFL,
float_flag_underflow = FP_X_UFL,
float_flag_underflow = FP_X_UFL,
float_flag_underflow = FP_X_UFL,
float_flag_underflow = FP_X_UFL,
& (FP_X_IMP | FP_X_UFL | FP_X_OFL | FP_X_DZ | FP_X_INV);
fpcr |= (disables & (FP_X_IMP | FP_X_UFL)) << (61 - 3);
__CTASSERT(ALPHA_AESR_UNF == (FP_X_UFL << 1));
__CTASSERT(IEEE_TRAP_ENABLE_UNF == (FP_X_UFL << 1));
__CTASSERT((uint64_t)FP_X_UFL << (61 - 3) == FPCR_UNFD);
#define FP_AA_FLAGS (FP_X_INV | FP_X_DZ | FP_X_OFL | FP_X_UFL | FP_X_IMP)
__fp |= FP_X_UFL;
if (__fp & FP_X_UFL)
float_flag_underflow = FP_X_UFL,
{ f_ufl, FP_X_UFL, FPE_FLTUND },
{ d_ufl, FP_X_UFL, FPE_FLTUND },
{ ld_ufl, FP_X_UFL, FPE_FLTUND },
fp_except_t msk, lst[] = { FP_X_INV, FP_X_DZ, FP_X_OFL, FP_X_UFL };
fpsetmask(FP_X_INV|FP_X_DZ|FP_X_OFL|FP_X_UFL|FP_X_IMP);
fpsetmask(FP_X_INV|FP_X_DZ|FP_X_OFL|FP_X_UFL|FP_X_IMP);
fpsetmask(FP_X_INV|FP_X_DZ|FP_X_OFL|FP_X_UFL|FP_X_IMP);
fpsetmask(FP_X_UFL);
ATF_CHECK_EQ_MSG(fpgetmask(), FP_X_UFL,
(int)fpgetmask(), (int)FP_X_UFL);