FP_X_INV
float_flag_invalid = FP_X_INV
float_flag_invalid = FP_X_INV
float_flag_invalid = FP_X_INV
float_flag_invalid = FP_X_INV
if ((mask & FP_X_INV) == 0)
float_flag_invalid = FP_X_INV
if ((mask & FP_X_INV) == 0)
float_flag_invalid = FP_X_INV
if ((mask & FP_X_INV) == 0)
float_flag_invalid = FP_X_INV
float_flag_invalid = FP_X_INV
float_flag_invalid = FP_X_INV
& (FP_X_IMP | FP_X_UFL | FP_X_OFL | FP_X_DZ | FP_X_INV);
fpcr |= (disables & (FP_X_OFL | FP_X_DZ | FP_X_INV)) << (49 - 0);
float_raise(FP_X_INV);
__CTASSERT(ALPHA_AESR_INV == (FP_X_INV << 1));
__CTASSERT(IEEE_TRAP_ENABLE_INV == (FP_X_INV << 1));
__CTASSERT((uint64_t)FP_X_INV << (49 - 0) == FPCR_INVD);
#define FP_AA_FLAGS (FP_X_INV | FP_X_DZ | FP_X_OFL | FP_X_UFL | FP_X_IMP)
#define float_set_invalid() float_raise(FP_X_INV)
__fp |= FP_X_INV;
if (__fp & FP_X_INV)
float_flag_invalid = FP_X_INV
if (0 == fpsetmask(fpsetmask(FP_X_INV))) {
{ f_inv, FP_X_INV, FPE_FLTINV },
{ d_inv, FP_X_INV, FPE_FLTINV },
{ ld_inv, FP_X_INV, FPE_FLTINV },
fp_except_t msk, lst[] = { FP_X_INV, FP_X_DZ, FP_X_OFL, FP_X_UFL };
if (0 == fpsetmask(fpsetmask(FP_X_INV))) \
if (0 == fpsetmask(fpsetmask(FP_X_INV)))
fpsetmask(FP_X_INV|FP_X_DZ|FP_X_OFL|FP_X_UFL|FP_X_IMP);
fpsetmask(FP_X_INV|FP_X_DZ|FP_X_OFL|FP_X_UFL|FP_X_IMP);
if (0 == fpsetmask(fpsetmask(FP_X_INV)))
fpsetmask(FP_X_INV|FP_X_DZ|FP_X_OFL|FP_X_UFL|FP_X_IMP);
fpsetmask(FP_X_INV);
ATF_CHECK_EQ_MSG(fpgetmask(), FP_X_INV,
(int)fpgetmask(), (int)FP_X_INV);
if (0 == fpsetmask(fpsetmask(FP_X_INV))) \