FIFO_ENABLE
sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1;
sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8;
sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4;
FIFO_XMT_RST | FIFO_RCV_RST | FIFO_ENABLE);
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1);
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1);
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1;
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1;
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1);
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1);
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_1);
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1);
FIFO_XMT_RST | FIFO_RCV_RST | FIFO_ENABLE);
sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8;
sc->sc_fifo = FIFO_ENABLE |
sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8;
sc->sc_fifo = FIFO_ENABLE |
sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8;
sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1;
sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1;
sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8;
sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4;
fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST);
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1);
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1);
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1);
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14);
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14);
uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14;