ENABLE
error = cbq_set_enable((struct cbq_interface *)addr, ENABLE);
case ENABLE:
case ENABLE:
error = wfq_setenable((struct wfq_interface *)addr, ENABLE);
CLK_GATE("pll1_sys", "pll1_bypass", CCM_ANALOG, PLL_ARM, ENABLE),
CLK_GATE("pll2_bus", "pll2_bypass", CCM_ANALOG, PLL_SYS, ENABLE),
CLK_GATE("pll3_usb_otg", "pll3_bypass", CCM_ANALOG, PLL_USB1, ENABLE),
CLK_GATE("pll4_audio", "pll4_bypass", CCM_ANALOG, PLL_AUDIO, ENABLE),
CLK_GATE("pll5_video", "pll5_bypass", CCM_ANALOG, PLL_VIDEO, ENABLE),
CLK_GATE("pll6_enet", "pll6_bypass", CCM_ANALOG, PLL_ENET, ENABLE),
CLK_GATE("pll7_usb_host", "pll7_bypass", CCM_ANALOG, PLL_USB2, ENABLE),
CLK_GATE("pll1_sys", "pll1_bypass", CCM_ANALOG, PLL_ARM, ENABLE),
CLK_GATE("pll2_bus", "pll2_bypass", CCM_ANALOG, PLL_SYS, ENABLE),
CLK_GATE("pll3_usb_otg", "pll3_bypass", CCM_ANALOG, PLL_USB1, ENABLE),
CLK_GATE("pll4_audio", "pll4_bypass", CCM_ANALOG, PLL_AUDIO, ENABLE),
CLK_GATE("pll5_video", "pll5_bypass", CCM_ANALOG, PLL_VIDEO, ENABLE),
CLK_GATE("pll6_enet", "pll6_bypass", CCM_ANALOG, PLL_ENET, ENABLE),
CLK_GATE("pll7_usb_host", "pll7_bypass", CCM_ANALOG, PLL_USB2, ENABLE),
ENABLE(reg & MQ200_GCC_ENABLE),
ENABLE(reg & MQ200_GCC_WINEN),
ENABLE(reg & MQ200_GCC_ALTEN),
ENABLE(reg&MQ200_GC1CRTC_DACEN));
ENABLE(reg & MQ200_FPC_ENABLE),
p1->portC = POWER | READ_BUSY | ENABLE;
msb = p1->portA & ENABLE;
p1->portC = POWER | WRITE_DATA | ENABLE;
p1->portC = POWER | WRITE_CMD | ENABLE;
ahc_outb(ahc, BCTL, ENABLE);