sys/dev/i2c/bmx280thpi2c.c

141

.write_reg = bmx280thpi2c_write_register,

sys/dev/i2c/sc16is7xxi2c.c

139

.write_reg = sc16is7xxi2c_write_register,

sys/dev/ic/bmx280.c

443

error = sc->sc_funcs->write_reg(sc, buf, 2);

sys/dev/ic/bmx280.c

700

error = sc->sc_funcs->write_reg(sc, cr, s);

sys/dev/ic/bmx280var.h

56

int (*write_reg)(struct bmx280_sc *, uint8_t *, size_t);

sys/dev/ic/sc16is7xx.c

223

error = sc->sc_funcs->write_reg(sc, SC16IS7XX_REGISTER_IOSTATE, 1, &r, 1);

sys/dev/ic/sc16is7xx.c

237

error = sc->sc_funcs->write_reg(sc, SC16IS7XX_REGISTER_IOCONTROL, 1, &iocontrol, 1);

sys/dev/ic/sc16is7xx.c

255

error = sc->sc_funcs->write_reg(sc, SC16IS7XX_REGISTER_IOCONTROL, 1, &iocontrol, 1);

sys/dev/ic/sc16is7xx.c

262

error = sc->sc_funcs->write_reg(sc, SC16IS7XX_REGISTER_IODIR, 1, &iodir, 1);

sys/dev/ic/sc16is7xx.c

449

sc->sc_funcs->write_reg(sc, SC16IS7XX_REGISTER_IOCONTROL, 0, &iocontrol_reg, 1);

sys/dev/ic/sc16is7xx.c

536

error = sc->sc_funcs->write_reg(sc, SC16IS7XX_REGISTER_IOCONTROL, 1, &iocontrol_reg, 1);

sys/dev/ic/sc16is7xxvar.h

49

int (*write_reg)(struct sc16is7xx_sc *, uint8_t, int, uint8_t *,

sys/dev/pci/igc/igc_hw.h

240

int (*write_reg)(struct igc_hw *, uint32_t, uint16_t);

sys/dev/pci/igc/igc_i225.c

158

phy->ops.write_reg = igc_write_phy_reg_gpy;

sys/dev/pci/igc/igc_phy.c

41

phy->ops.write_reg = igc_null_write_reg;

sys/dev/pci/igc/igc_phy.c

440

ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);

sys/dev/pci/igc/igc_phy.c

447

ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,

sys/dev/pci/igc/igc_phy.c

451

ret_val = phy->ops.write_reg(hw,

sys/dev/pci/igc/igc_phy.c

503

ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);

sys/dev/pci/igc/igc_phy.c

763

hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);

sys/dev/pci/igc/igc_phy.c

783

hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);

sys/dev/pci/igc/igc_phy.c

874

ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);

sys/dev/pci/igc/igc_phy.c

878

ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);

sys/dev/pci/igc/igc_phy.c

882

ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |

sys/dev/pci/igc/igc_phy.c

890

ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);

sys/dev/pci/igc/igc_phy.c

895

ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);

sys/dev/pci/igma.c

539

co->write_reg(cd, ii->ii_reg, reg);

sys/dev/pci/igma/igmafb.c

422

co->write_reg(cd, sc->sc_chip.vga_cntrl, r | VGA_CNTRL_DISABLE);

sys/dev/pci/igma/igmafb.c

428

co->write_reg(cd, PF_WINPOS(pipe),

sys/dev/pci/igma/igmafb.c

430

co->write_reg(cd, PF_WINSZ(pipe),

sys/dev/pci/igma/igmafb.c

434

co->write_reg(cd, PIPE_SRCSZ(pipe),

sys/dev/pci/igma/igmafb.c

438

co->write_reg(cd, PIPE_CONF(pipe),

sys/dev/pci/igma/igmafb.c

445

co->write_reg(cd, PRI_CTRL(pipe), r | cd->pri_cntrl);

sys/dev/pci/igma/igmafb.c

446

co->write_reg(cd, PRI_LINOFF(pipe), 0);

sys/dev/pci/igma/igmafb.c

447

co->write_reg(cd, PRI_STRIDE(pipe), sc->sc_stride);

sys/dev/pci/igma/igmafb.c

448

co->write_reg(cd, PRI_SURF(pipe), 0);

sys/dev/pci/igma/igmafb.c

449

co->write_reg(cd, PRI_TILEOFF(pipe), 0);

sys/dev/pci/igma/igmafb.c

458

co->write_reg(cd, PRI_CTRL(pipe), 0 | cd->pri_cntrl);

sys/dev/pci/igma/igmafb.c

459

co->write_reg(cd, PRI_LINOFF(pipe), 0);

sys/dev/pci/igma/igmafb.c

460

co->write_reg(cd, PRI_STRIDE(pipe), 2560);

sys/dev/pci/igma/igmafb.c

461

co->write_reg(cd, PRI_SURF(pipe), 0);

sys/dev/pci/igma/igmafb.c

462

co->write_reg(cd, PRI_TILEOFF(pipe), 0);

sys/dev/pci/igma/igmafb.c

465

co->write_reg(cd, PIPE_SRCSZ(pipe),

sys/dev/pci/igma/igmafb.c

469

co->write_reg(cd, PIPE_CONF(pipe), 0);

sys/dev/pci/igma/igmafb.c

478

co->write_reg(cd, 0x42000, (r & 0x1fffffff) | 0xa0000000);

sys/dev/pci/igma/igmafb.c

480

co->write_reg(cd, 0x42004, (r & 0xfbffffff) | 0x00000000);

sys/dev/pci/igma/igmafb.c

483

co->write_reg(cd, PF_WINPOS(pipe),

sys/dev/pci/igma/igmafb.c

485

co->write_reg(cd, PF_WINSZ(pipe),

sys/dev/pci/igma/igmafb.c

490

co->write_reg(cd, sc->sc_chip.vga_cntrl, r & ~VGA_CNTRL_DISABLE);

sys/dev/pci/igma/igmafb.c

500

co->write_reg(cd, PIPE_CONF(pipe),

sys/dev/pci/igma/igmafb.c

515

co->write_reg(cd, FW_BLC_SELF, fwbcl & ~FW_BLC_SELF_EN);

sys/dev/pci/igma/igmafb.c

518

co->write_reg(cd, CUR_CNTR(pipe), 1<<5 | 0x07);

sys/dev/pci/igma/igmafb.c

523

co->write_reg(cd, CUR_CNTR(pipe), cntrl);

sys/dev/pci/igma/igmafb.c

524

co->write_reg(cd, CUR_BASE(pipe),

sys/dev/pci/igma/igmafb.c

527

co->write_reg(cd, FW_BLC_SELF, fwbcl);

sys/dev/pci/igma/igmafb.c

539

co->write_reg(cd, PF_CTRL_I965, r & ~PF_ENABLE);

sys/dev/pci/igma/igmafb.c

584

co->write_reg(cd, cd->backlight_cntrl,

sys/dev/pci/igmavar.h

29

void (*write_reg)(const struct igma_chip *, int, u_int32_t);

sys/dev/pci/ixgbe/ixgbe_api.c

559

return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,

sys/dev/pci/ixgbe/ixgbe_common.c

378

hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,

sys/dev/pci/ixgbe/ixgbe_phy.c

1083

hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,

sys/dev/pci/ixgbe/ixgbe_phy.c

1098

hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,

sys/dev/pci/ixgbe/ixgbe_phy.c

1113

hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,

sys/dev/pci/ixgbe/ixgbe_phy.c

1128

hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,

sys/dev/pci/ixgbe/ixgbe_phy.c

1195

hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,

sys/dev/pci/ixgbe/ixgbe_phy.c

1250

hw->phy.ops.write_reg(hw, phy_offset,

sys/dev/pci/ixgbe/ixgbe_phy.c

265

phy->ops.write_reg = ixgbe_write_phy_reg_generic;

sys/dev/pci/ixgbe/ixgbe_phy.c

2767

status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,

sys/dev/pci/ixgbe/ixgbe_phy.c

529

hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,

sys/dev/pci/ixgbe/ixgbe_phy.c

813

hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,

sys/dev/pci/ixgbe/ixgbe_phy.c

842

hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,

sys/dev/pci/ixgbe/ixgbe_phy.c

857

hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,

sys/dev/pci/ixgbe/ixgbe_phy.c

869

hw->phy.ops.write_reg(hw, MDIO_PMAPMD_CTRL1,MDIO_MMD_PMAPMD,

sys/dev/pci/ixgbe/ixgbe_phy.c

878

hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,

sys/dev/pci/ixgbe/ixgbe_phy.c

891

hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,

sys/dev/pci/ixgbe/ixgbe_type.h

4135

s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);

sys/dev/pci/ixgbe/ixgbe_x550.c

2253

status = hw->phy.ops.write_reg(hw,

sys/dev/pci/ixgbe/ixgbe_x550.c

2272

status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,

sys/dev/pci/ixgbe/ixgbe_x550.c

2290

status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,

sys/dev/pci/ixgbe/ixgbe_x550.c

2307

status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,

sys/dev/pci/ixgbe/ixgbe_x550.c

2473

hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;

sys/dev/pci/ixgbe/ixgbe_x550.c

2484

hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;

sys/dev/pci/ixgbe/ixgbe_x550.c

2518

phy->ops.write_reg = ixgbe_write_phy_reg_x550em;

sys/dev/pci/ixgbe/ixgbe_x550.c

2523

phy->ops.write_reg = ixgbe_write_phy_reg_x550em;

sys/dev/pci/ixgbe/ixgbe_x550.c

2534

phy->ops.write_reg = ixgbe_write_phy_reg_x550em;

sys/dev/pci/ixgbe/ixgbe_x550.c

2769

status = hw->phy.ops.write_reg(hw,

sys/dev/pci/ixgbe/ixgbe_x550.c

2989

ret_val = hw->phy.ops.write_reg(hw, reg_slice,

sys/dev/pci/ixgbe/ixgbe_x550.c

611

hw->phy.ops.write_reg = NULL;

sys/dev/podulebus/esp_podule.c

100

void (*write_reg)(struct ncr53c9x_softc *, int, uint8_t);

sys/dev/podulebus/esp_podule.c

141

esc->sc_esp_glue.gl_write_reg = devices[i].write_reg;

sys/dev/spi/bmx280thpspi.c

143

.write_reg = bmx280thpspi_write_reg,

sys/dev/spi/sc16is7xxspi.c

136

.write_reg = sc16is7xxspi_write_register,

sys/dev/usb/uchcom.c

509

return write_reg(sc, UCHCOM_REG_STAT1, val, UCHCOM_REG_STAT1, val);

sys/dev/usb/uchcom.c

608

err = write_reg(sc, UCHCOM_REG_BREAK, brk, UCHCOM_REG_LCR, lcr);

sys/dev/usb/uchcom.c

684

if ((err = write_reg(sc,

sys/dev/usb/uchcom.c

736

err = write_reg(sc, UCHCOM_REG_LCR, lcr, UCHCOM_REG_LCR2, lcr2);