vu_char
vu_char *esc;
sc->sc_iobase = (vu_char *)sc->sc_podule->fast_base;
rp->chipreset = (vu_char *)&dummy[0];
rp->inten = (vu_char *)&dummy[1];
rp->status = (vu_char *)&dummy[2];
rp->led = (vu_char *)&dummy[4];
vu_char *chipreset;
vu_char *inten;
vu_char *status;
vu_char *term;
vu_char *led;
vu_char *sc_iobase;
vu_char *fas;
(vu_char *)sc->sc_specific.sc_podule->mod_base;
vu_char *status0;
vu_char *alatch;
vu_char *sc_iobase;
vu_char *esc_status;
vu_char *esc_command;
vu_char *esc_interrupt;
vu_char *esc_fifo;
vu_char *esc_tc_low; /* rw: Transfer count low */
vu_char *esc_tc_mid; /* rw: Transfer count mid */
vu_char *esc_fifo; /* rw: Data FIFO */
vu_char *esc_command; /* rw: Chip command reg */
vu_char *esc_dest_id; /* w: (Re)select bus ID */
vu_char *esc_timeout; /* w: (Re)select timeout */
vu_char *esc_syncper; /* w: Synch. transfer period */
vu_char *esc_syncoff; /* w: Synch. transfer offset */
vu_char *esc_config1; /* rw: Config register #1 */
vu_char *esc_clkconv; /* w: Clock conv. factor */
vu_char *esc_test; /* w: Test register */
vu_char *esc_config2; /* rw: Config register #2 */
vu_char *esc_config3; /* rw: Config register #3 */
vu_char *esc_config4; /* rw: Config register #4 */
vu_char *esc_tc_high; /* rw: Transfer count high */
vu_char *esc_fifo_bot; /* w: FIFO bottom register */
vu_char *fas;
(vu_char *)sc->sc_specific.sc_podule->fast_base;
vu_char *chipreset;
vu_char *inten;
vu_char *status;
vu_char *term;
vu_char *led;
vu_char *sc_iobase;
vu_char *sfas_tc_low; /* rw: Transfer count low */
vu_char *sfas_tc_mid; /* rw: Transfer count mid */
vu_char *sfas_fifo; /* rw: Data FIFO */
vu_char *sfas_command; /* rw: Chip command reg */
vu_char *sfas_dest_id; /* w: (Re)select bus ID */
vu_char *sfas_timeout; /* w: (Re)select timeout */
vu_char *sfas_syncper; /* w: Synch. transfer period */
vu_char *sfas_syncoff; /* w: Synch. transfer offset */
vu_char *sfas_config1; /* rw: Config register #1 */
vu_char *sfas_clkconv; /* w: Clock conv. factor */
vu_char *sfas_test; /* w: Test register */
vu_char *sfas_config2; /* rw: Config register #2 */
vu_char *sfas_config3; /* rw: Config register #3 */
vu_char *sfas_tc_high; /* rw: Transfer count high */
vu_char *sfas_fifo_bot; /* w: FIFO bottom register */
sc->sc_sbic.sbic_asr_p = ((vu_char *)rp + 0x43);
sc->sc_sbic.sbic_value_p = ((vu_char *)rp + 0x47);
sc->sc_sbic.sbic_asr_p = ((vu_char *)rp + 0x41);
sc->sc_sbic.sbic_value_p = ((vu_char *)rp + 0x43);
vu_char SASR; /* sbic asr */
vu_char SCMD; /* sbic data */
vu_char SASR; /* sbic asr */
vu_char SCMD; /* sbic data */
vu_char SASR;
vu_char SCMD;
vu_char dcm_data;
vu_char dcm_stcon; /* Self test condition 8e47 */
vu_char dcm_modemchng; /* 638 Modem change mask 8e5b */
vu_char dcm_modemintr; /* 638 Modem interrupt mask 8e5d */
vu_char data_char;
vu_char r_head; /* +01 */
vu_char r_tail; /* +09 */
vu_char t_head; /* +11 */
vu_char t_tail; /* +19 */
vu_char dcm_rsid; /* Reset / ID 0001 */
vu_char dcm_ic; /* Interrupt control register 0003 */
vu_char dcm_sem; /* Semaphore register 0005 */
vu_char dcm_iir; /* Interrupt ident register 8001 */
vu_char dcm_cr; /* Command register 8003 */
vu_char data_char;
vu_char data_stat;
vu_char data_data;
vu_char ptr;
vu_char ptr;
vu_char ptr;
vu_char ptr;
vu_char dcm_conf;
vu_char dcm_baud;
vu_char mdmin; /* Modem in 8e31 */
vu_char mdmout; /* Modem out 8e33 */
vu_char mdmmsk; /* Modem mask 8e35 */
vu_char dcm_data;
vu_char dma_cr;
vu_char hpib_cid;
vu_char hpib_ids;
vu_char hpib_ctrl2;
vu_char hpib_latch;
vu_char hpib_intr;
vu_char hpib_imask;
vu_char hpib_data;
vu_char hpib_stat;
vu_char hpib_cmd;
vu_char hpib_ar;
vu_char hpib_pmask;
vu_char hpib_psense;
vu_char hpib_cid;
vu_char hpib_ids;
vu_char hpib_csa;
vu_char hpib_mis;
vu_char hpib_lis;
vu_char hpib_is;
vu_char hpib_cls;
vu_char hpib_ar;
vu_char hpib_sprb;
vu_char hpib_cpt;
vu_char hpib_data;
vu_char ap_data;
vu_char ap_ier;
vu_char ap_iir;
vu_char ap_cfcr;
vu_char ap_mcr;
vu_char ap_lsr;
vu_char ap_msr;
vu_char ap_scratch;
vu_char dca_reset;
vu_char dca_pad[0x800-1];
vu_char dca_data; /* receive buf or xmit hold */
vu_char dca_ier; /* interrupt enable */
vu_char dca_iir; /* (RO) interrupt identify */
vu_char dca_cfcr; /* line control */
vu_char dca_mcr; /* modem control */
vu_char dca_lsr; /* line status */
vu_char dca_msr; /* modem status */
vu_char dca_scr; /* scratch pad */
vu_char dca_id; /* 0x01 (read) */
vu_char dca_ic; /* 0x03 */
vu_char dca_ocbrc; /* 0x05 */
vu_char dca_lcsm; /* 0x07 */
vu_char dca_data; /* 0x11 */
vu_char dca_ier; /* 0x13 */
vu_char dca_iir; /* 0x15 (read) */
vu_char dca_cfcr; /* 0x17 */
vu_char dca_mcr; /* 0x19 */
vu_char dca_lsr; /* 0x1B */
vu_char dca_msr; /* 0x1D */
vu_char drive; /* Select FB vs. Overlay. 0x40BF */
vu_char zconfig; /* Z buffer configuration 0x40CB */
vu_char alt_rr; /* Alternate replacement rule 0x40CF */
vu_char zrr; /* Z replacement rule 0x40D3 */
vu_char en_scan; /* Enable scan DTACK. 0x40D7 */
vu_char rep_rule; /* Replacement rule 0x40EF */
vu_char cmapbank; /* Bank select (0 or 1) 0x6003 */
vu_char dispen; /* Display enable 0x6007 */
vu_char fbvenp; /* Frame buffer video enable 0x600B */
vu_char fbvens; /* fbvenp blink counterpart 0x6017 */
vu_char vdrive; /* Video display mode 0x6023 */
vu_char panxh; /* Pan display in X (high) 0x6083 */
vu_char panxl; /* Pan display in X (low) 0x6087 */
vu_char panyh; /* Pan display in Y (high) 0x608B */
vu_char panyl; /* Pan display in Y (low) 0x608F */
vu_char zoom; /* Zoom factor 0x6093 */
vu_char pz_trig; /* Pan & zoom trigger 0x6097 */
vu_char ovly0p; /* Overlay 0 primary map 0x609B */
vu_char ovly1p; /* Overlay 1 primary map 0x609F */
vu_char ovly0s; /* Overlay 0 secondary map 0x60A3 */
vu_char ovly1s; /* Overlay 1 secondary map 0x60A7 */
vu_char opvenp; /* Overlay video enable 0x60AB */
vu_char opvens; /* Overlay blink enable 0x60AF */
vu_char fv_trig; /* Trigger control registers 0x60B3 */
vu_char cdwidth; /* Iris cdwidth timing reg. 0x60B7 */
vu_char chstart; /* Iris chstart timing reg. 0x60BB */
vu_char cvwidth; /* Iris cvwidth timing reg. 0x60BF */
vu_char red0;
vu_char green0;
vu_char blue0;
vu_char red1;
vu_char green1;
vu_char blue1;
vu_char red;
vu_char green;
vu_char blue;
vu_char reset; /* reset register 0x01 */
vu_char interrupt; /* interrupt register 0x03 */
vu_char fbwmsb; /* frame buffer width MSB 0x05 */
vu_char fbwlsb; /* frame buffer width MSB 0x07 */
vu_char fbhmsb; /* frame buffer height MSB 0x09 */
vu_char fbhlsb; /* frame buffer height MSB 0x0b */
vu_char dwmsb; /* display width MSB 0x0d */
vu_char dwlsb; /* display width MSB 0x0f */
vu_char dhmsb; /* display height MSB 0x11 */
vu_char dhlsb; /* display height MSB 0x13 */
vu_char fbid; /* frame buffer id 0x15 */
vu_char fbomsb; /* frame buffer offset MSB 0x5d */
vu_char fbolsb; /* frame buffer offset LSB 0x5f */
vu_char wbusy; /* Window move in progress 0x4047 */
vu_char as_busy; /* Scan accessing frame buf. 0x405B */
vu_char wmove; /* Initiate window move. 0x409F */
vu_char fold; /* Byte/longword per pixel 0x40B3 */
vu_char opwen; /* Overlay plane write enable 0x40B7 */
vu_char height; /* height in tiles 0x5003 */
vu_char rep_rule; /* replacement rule 0x5007 */
vu_char blink1; /* blink 1 0x6001 */
vu_char blink2; /* blink 2 0x6005 */
vu_char write_protect; /* write protect 0x6009 */
vu_char cmap_busy; /* color map busy 0x6803 */
vu_char creg_select; /* color map register select 0x68b8 */
vu_char cmap_write; /* color map write trigger 0x68f1 */
vu_char cmap_red; /* red value register 0x69b3 */
vu_char cmap_grn; /* green value register 0x69b5 */
vu_char cmap_blu; /* blue value register 0x69b6 */
vu_char reset; /* reset register 0x01 */
vu_char sec_interrupt; /* Secondary interrupt register 0x03 */
vu_char interrupt; /* interrupt register 0x03 */
vu_char fbwmsb; /* frame buffer width MSB 0x05 */
vu_char fbwlsb; /* frame buffer width MSB 0x07 */
vu_char fbhmsb; /* frame buffer height MSB 0x09 */
vu_char fbhlsb; /* frame buffer height MSB 0x0b */
vu_char dwmsb; /* display width MSB 0x0d */
vu_char dwlsb; /* display width MSB 0x0f */
vu_char dhmsb; /* display height MSB 0x11 */
vu_char dhlsb; /* display height MSB 0x13 */
vu_char fbid; /* Scondary frame buffer id 0x15 */
vu_char fbomsb; /* frame buffer offset MSB 0x5d */
vu_char fbolsb; /* frame buffer offset LSB 0x5f */
vu_char crtc_address; /* CTR controller address reg 0x4000 */
vu_char status; /* Status register 0x4001 */
vu_char crtc_data; /* CTR controller data reg 0x4002 */
vu_char line_mover_rep_rule; /* Line move rep rule */
vu_char line_mover_width; /* Line move width */
vu_char width; /* width in tiles 0x5001 */
vu_char reset; /* reset register 0x01 */
vu_char fb_address; /* frame buffer address 0x02 */
vu_char interrupt; /* interrupt register 0x03 */
vu_char fbwmsb; /* frame buffer width MSB 0x05 */
vu_char fbwlsb; /* frame buffer width MSB 0x07 */
vu_char fbhmsb; /* frame buffer height MSB 0x09 */
vu_char fbhlsb; /* frame buffer height MSB 0x0b */
vu_char dwmsb; /* display width MSB 0x0d */
vu_char dwlsb; /* display width MSB 0x0f */
vu_char dhmsb; /* display height MSB 0x11 */
vu_char dhlsb; /* display height MSB 0x13 */
vu_char fbid; /* Scondary frame buffer id 0x15 */
vu_char bits; /* square(0)/double-high(1) 0x17 */
vu_char num_planes; /* number of color planes 0x5b */
vu_char fbomsb; /* frame buffer offset MSB 0x5d */
vu_char fbolsb; /* frame buffer offset LSB 0x5f */
vu_char nblank; /* display enable planes 0x4000 */
vu_char wmove; /* start window mover 0x409f */
vu_char blink; /* blink register 0x40a3 */
vu_char fold; /* fold register 0x40b3 */
vu_char tmode; /* Tile mode size 0x40bb */
vu_char drive; /* drive register 0x40bf */
vu_char vdrive; /* vdrive register 0x40c3 */
vu_char zconfig; /* Z-buffer mode 0x40cb */
vu_char dmode; /* dither mode 0x40d3 */
vu_char en_scan; /* enable scan board to DTACK 0x40d7 */
vu_char rep_rule; /* replacement rule 0x40ef */
vu_char value;
vu_char reset; /* reset register 0x01 */
vu_char fb_address; /* frame buffer address 0x02 */
vu_char interrupt; /* interrupt register 0x03 */
vu_char fbwmsb; /* frame buffer width MSB 0x05 */
vu_char fbwlsb; /* frame buffer width MSB 0x07 */
vu_char fbhmsb; /* frame buffer height MSB 0x09 */
vu_char fbhlsb; /* frame buffer height MSB 0x0b */
vu_char dwmsb; /* display width MSB 0x0d */
vu_char dwlsb; /* display width MSB 0x0f */
vu_char dhmsb; /* display height MSB 0x11 */
vu_char dhlsb; /* display height MSB 0x13 */
vu_char fbid; /* frame buffer id 0x15 */
vu_char fbomsb; /* frame buffer offset MSB 0x5d */
vu_char fbolsb; /* frame buffer offset LSB 0x5f */
vu_char wbusy; /* window mover is active 0x4047 */
vu_char scanbusy; /* scan converteris active 0x405B */
vu_char video_enable; /* drive vid. refresh bus 0x4083 */
vu_char display_enable; /* enable the display 0x4087 */
vu_char altframe; /* enable alternate frame 0x40a8 */
vu_char curon; /* cursor control register 0x40ac */
vu_char prr; /* pixel replacement rule 0x40ea */
vu_char wmrr; /* move replacement rule 0x40ef */
vu_char reset; /* reset register 0x01 */
vu_char fb_address; /* frame buffer address 0x02 */
vu_char interrupt; /* interrupt register 0x03 */
vu_char fbwmsb; /* frame buffer width MSB 0x05 */
vu_char fbwlsb; /* frame buffer width MSB 0x07 */
vu_char fbhmsb; /* frame buffer height MSB 0x09 */
vu_char fbhlsb; /* frame buffer height MSB 0x0b */
vu_char dwmsb; /* display width MSB 0x0d */
vu_char dwlsb; /* display width MSB 0x0f */
vu_char dhmsb; /* display height MSB 0x11 */
vu_char dhlsb; /* display height MSB 0x13 */
vu_char fbid; /* Scondary frame buffer id 0x15 */
vu_char bits; /* square(0)/double-high(1) 0x17 */
vu_char num_planes; /* number of color planes 0x5b */
vu_char fbomsb; /* frame buffer offset MSB 0x5d */
vu_char fbolsb; /* frame buffer offset LSB 0x5f */
vu_char vblank; /* vertical blanking 0x4040 */
vu_char busy; /* window move active 0x4044 */
vu_char vtrace_request; /* vert retrace intr request 0x4048 */
vu_char move_request; /* window move intr request 0x404C */
vu_char nblank; /* display enable planes 0x4080 */
vu_char wen; /* write enable plane 0x4088 */
vu_char ren; /* read enable plane 0x408c */
vu_char fben; /* frame buffer write enable 0x4090 */
vu_char wmove; /* start window move 0x409c */
vu_char blink; /* enable blink planes 0x40a0 */
vu_char hil_data;
vu_char hil_cmd;
vu_char hil_rsthold; /* (WO) reset hold (and Serial #3) */
vu_char hil_resv1[2047];
vu_char hil_data; /* send/receive data to/from 8042 */
vu_char hil_cmd; /* status/control to/from 8042 */
vu_char hil_resv2[1022];
vu_char hil_rstrel; /* (WO) reset release (and Serial #3) */
vu_char ler0_id; /* ID */
vu_char ler0_status; /* interrupt enable/status */