vDirB
via_reg(VIA1, vDirB) |= 0x30; /* register B bits 4 and 5:
via_reg(VIA1, vDirB) &= 0xf7; /* register B bit 3: input */
via_reg(VIA1, vDirB) |= 0x30; /* register B bits 4 and 5:
via_reg(VIA1, vDirB) &= 0xf7; /* register B bit 3: input */
via_reg(VIA1, vDirB) |= 0x30; /* register B bits 4 and 5:
via_reg(VIA1, vDirB) &= 0xf7; /* register B bit 3: input */
via_reg(VIA1, vDirB) |= DB1O_AuxIntEnb;
via_reg(VIA1, vDirB) |= (0x40);
via2_reg(vDirB) |= 0x02;
via2_reg(vDirB) |= 0x04; /* Set write for bit 2 */
via_reg_or(VIA1, vDirB, 0x30); /* register B bits 4 and 5:
via_reg_and(VIA1, vDirB, 0xf7); /* register B bit 3: input */
reg = cuda_read_reg(sc, vDirB);
cuda_write_reg(sc, vDirB, reg);
reg = cuda_read_reg(sc, vDirB);
cuda_write_reg(sc, vDirB, reg);