vACR
#define ADB_SET_SR_INPUT() via_reg(VIA1, vACR) &= ~vSR_OUT
#define ADB_SET_SR_OUTPUT() via_reg(VIA1, vACR) |= vSR_OUT
via_reg(VIA1, vACR) &= ~vSR_OUT; /* make sure SR is set
via_reg(VIA1, vACR) &= ~vSR_OUT; /* make sure SR is set
via_reg(VIA1, vACR) &= ~vSR_OUT; /* make sure SR is set
via_reg(VIA1, vACR) = (via_reg(VIA1, vACR) | 0x0c) & ~0x10;
via_reg(VIA1, vACR) |= 0x0c;
via_reg(VIA1, vACR) &= ~0x10;
via_reg(VIA1, vACR) |= 0x1c;
via_reg(VIA1, vACR) |= 0x1c;
via_reg(VIA1, vACR) |= 0x1c;
via_reg(VIA1, vACR) |= ACR_T1LATCH;
via_reg(VIA2, vACR) |= ACR_T1LATCH;
via_reg(VIA1, vACR) &= ~ACR_T1LATCH;
via_reg(VIA1, vACR) &= 0x3f;
via2_reg(vACR) &= 0x3f;
#define ADB_SET_SR_INPUT() via_reg_and(VIA1, vACR, ~vSR_OUT)
#define ADB_SET_SR_OUTPUT() via_reg_or(VIA1, vACR, vSR_OUT)
via_reg_and(VIA1, vACR, ~vSR_OUT); /* make sure SR is set
write_via_reg(VIA1, vACR, (read_via_reg(VIA1, vACR) | 0x0c) & ~0x10);
reg = cuda_read_reg(sc, vACR);
cuda_write_reg(sc, vACR, reg);
cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10);
reg = cuda_read_reg(sc, vACR);
cuda_write_reg(sc, vACR, reg);
reg = cuda_read_reg(sc, vACR);
cuda_write_reg(sc, vACR, reg);
via_reg_or(VIA1, vACR, 0x0c);
via_reg_and(VIA1, vACR, ~0x10);
via_reg_or(VIA1, vACR, 0x1c);
via_reg_or(VIA1, vACR, 0x1c);
via_reg_or(VIA1, vACR, 0x1c);
via_reg_or(VIA1, vACR, 0x1c);
reg = pmu_read_reg(sc, vACR);
pmu_write_reg(sc, vACR, reg);
reg = pmu_read_reg(sc, vACR);
pmu_write_reg(sc, vACR, reg);