tx_conf_read
reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG);
reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG);
reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG);
reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG);
reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG);
reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG);
reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG);
reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG);
reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG);
reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG);
reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG);
rev = tx_conf_read(tc, TX3922_REVISION_REG);
val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG);
reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG);
reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG);
reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG);
reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG);
reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG);
reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG);
reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG);
reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG);
oreglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG);
reglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG);
oreghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG);
reghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG);
reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG);
return tx_conf_read(tc, TX39_TIMERRTCLO_REG);
reg = tx_conf_read(tc, TX39_TIMERPERIODIC_REG);
reg = tx_conf_read(tc, TX39_INTRENABLE6_REG);
reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG);
regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG);
regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG);
regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG);
regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG);
regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG);
regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG);
regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG);
regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG);
reg = tx_conf_read(tc, TX39_INTRENABLE6_REG);
tx_conf_read(tc, TX39_INTRSTATUS1_REG));
tx_conf_read(tc, TX39_INTRSTATUS2_REG));
tx_conf_read(tc, TX39_INTRSTATUS3_REG));
tx_conf_read(tc, TX39_INTRSTATUS4_REG));
tx_conf_read(tc, TX39_INTRSTATUS5_REG));
tx_conf_read(tc, TX39_INTRSTATUS7_REG));
tx_conf_read(tc, TX39_INTRSTATUS8_REG));
reg = tx_conf_read(tc, TX39_INTRENABLE6_REG);
regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG);
regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG);
regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG);
regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG);
regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG);
regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG);
regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG);
regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG);
regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG);
regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG);
regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG);
regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG);
regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG);
regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG);
regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG);
regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG);
reg = tx_conf_read(tc, TX39_INTRENABLE6_REG);
reg = tx_conf_read(tc, TX39_INTRENABLE6_REG);
reg = tx_conf_read(tc, TX39_INTRENABLE6_REG);
reg = tx_conf_read(tc, ofs);
reg = tx_conf_read(tc, ofs);
reg = tx_conf_read(tc, ofs);
reg = tx_conf_read(tc, TX39_INTRENABLE6_REG);
reg = tx_conf_read(tc, TX39_IOMFIODATAOUT_REG);
return (tx_conf_read(sc->sc_tc, TX39_IOMFIODATAIN_REG) & (1 << port));
stat_mfio->dir = tx_conf_read(tc, TX39_IOMFIODATADIR_REG);
stat_mfio->in = tx_conf_read(tc, TX39_IOMFIODATAIN_REG);
stat_mfio->out = tx_conf_read(tc, TX39_IOMFIODATAOUT_REG);
stat_mfio->power = tx_conf_read(tc, TX39_IOMFIOPOWERDWN_REG);
stat_mfio->u.select = tx_conf_read(tc, TX39_IOMFIODATASEL_REG);
txreg_t reg = tx_conf_read(sc->sc_tc, TX39_IOCTRL_REG);
reg = tx_conf_read(tc, TX39_IOCTRL_REG);
reg = tx_conf_read(tc, TX39_IOCTRL_REG);
reg = tx_conf_read(tc, TX39_IOIOPOWERDWN_REG);
txreg_t reg = tx_conf_read(sc->sc_tc, TX392X_IODATAINOUT_REG);
reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG);
reg = tx_conf_read(tc, TX39_IOCTRL_REG);
reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG);
reg = tx_conf_read(tc, TX39_IOIOPOWERDWN_REG);
reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG);
reg = tx_conf_read(tc, TX39_IRCTRL1_REG);
reg = tx_conf_read(tc, TX39_IRCTRL1_REG);
reg = tx_conf_read(tc, TX39_POWERCTRL_REG);
reg = tx_conf_read(tc, TX39_POWERCTRL_REG);
reg = tx_conf_read(tc, TX39_POWERCTRL_REG);
iregs[0] = tx_conf_read(tc, TX39_INTRENABLE6_REG);
iregs[1] = tx_conf_read(tc, TX39_INTRENABLE1_REG);
iregs[2] = tx_conf_read(tc, TX39_INTRENABLE2_REG);
iregs[3] = tx_conf_read(tc, TX39_INTRENABLE3_REG);
iregs[4] = tx_conf_read(tc, TX39_INTRENABLE4_REG);
iregs[5] = tx_conf_read(tc, TX39_INTRENABLE5_REG);
iregs[7] = tx_conf_read(tc, TX39_INTRENABLE7_REG);
iregs[8] = tx_conf_read(tc, TX39_INTRENABLE8_REG);
reg = tx_conf_read(tc, TX39_POWERCTRL_REG);
reg = tx_conf_read(tc, TX39_POWERCTRL_REG);
reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG);
reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
for (i = 0; (!(tx_conf_read(tc, TX39_INTRSTATUS1_REG) &
reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG);
reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG);
return tx_conf_read(sc->sc_tc, TX39_SPICTRL_REG) & (TX39_SPICTRL_EMPTY);
while(!(tx_conf_read(tc, TX39_INTRSTATUS5_REG) & TX39_INTRSTATUS5_SPIBUFAVAILINT))
while(!(tx_conf_read(tc, TX39_INTRSTATUS5_REG) & TX39_INTRSTATUS5_SPIRCVINT))
return tx_conf_read(tc, TX39_SPIRXHOLD_REG) & 0xffff;
txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);
txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);
txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);
txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);
txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);
txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);
txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);
reg = tx_conf_read(tc, TX39_SPICTRL_REG);
reg = tx_conf_read(tc, TX39_UARTCTRL1_REG(slot));
reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG);
reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG);
reg = tx_conf_read(tc, ofs);
reg = tx_conf_read(tc, ofs);
while(!(tx_conf_read(tc, ofs) & TX39_UARTCTRL1_UARTON) &&
reg = tx_conf_read(tc, TX39_UARTCTRL1_REG(slot));
reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG);
if (tx_conf_read(tc, ofs) & TX39_UARTCTRL1_EMPTY)
reg = tx_conf_read(tc, ofs);
while(!(TX39_UARTCTRL1_RXHOLDFULL & tx_conf_read(tc, ofs)))
tx_conf_read(tc, TX39_UARTRXHOLD_REG(txcom_chip.sc_slot)));
reg = tx_conf_read(chip->sc_tc, ofs);
reg1 = tx_conf_read(chip->sc_tc, ofs);
reg = tx_conf_read(tc, TX39_UARTCTRL1_REG(slot));
tx_conf_read(chip->sc_tc,
reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG);
reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG);
reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG);
reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG);
reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG);
reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG);