sys/arch/arm/xscale/ixp425_pci_space.c

272

data = CSR_READ_4(PCI_NP_RDATA);

sys/arch/arm/xscale/ixp425_pci_space.c

273

if (CSR_READ_4(PCI_ISR) & ISR_PFE)

sys/arch/arm/xscale/ixp425_pci_space.c

292

data = CSR_READ_4(PCI_NP_RDATA);

sys/arch/arm/xscale/ixp425_pci_space.c

293

if (CSR_READ_4(PCI_ISR) & ISR_PFE)

sys/arch/arm/xscale/ixp425_pci_space.c

309

data = CSR_READ_4(PCI_NP_RDATA);

sys/arch/arm/xscale/ixp425_pci_space.c

310

if (CSR_READ_4(PCI_ISR) & ISR_PFE)

sys/arch/arm/xscale/ixp425_pci_space.c

332

if (CSR_READ_4(PCI_ISR) & ISR_PFE)

sys/arch/arm/xscale/ixp425_pci_space.c

352

if (CSR_READ_4(PCI_ISR) & ISR_PFE)

sys/arch/arm/xscale/ixp425_pci_space.c

367

if (CSR_READ_4(PCI_ISR) & ISR_PFE)

sys/arch/arm/xscale/pxa2x0_i2c.c

423

while (CSR_READ_4(sc, I2C_ICR) & ~ICR_UR)

sys/arch/arm/xscale/pxa2x0_i2c.c

436

isr = CSR_READ_4(sc, I2C_ISR);

sys/arch/arm/xscale/pxa2x0_i2c.c

512

*bytep = CSR_READ_4(sc, I2C_IDBR);

sys/arch/arm/xscale/pxa2x0_mci.c

1007

device_xname(sc->sc_dev), CSR_READ_4(sc, MMC_STAT)));

sys/arch/arm/xscale/pxa2x0_mci.c

154

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (val))

sys/arch/arm/xscale/pxa2x0_mci.c

156

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(val))

sys/arch/arm/xscale/pxa2x0_mci.c

732

if (ISSET(CSR_READ_4(sc, MMC_STAT), STAT_CLK_EN)) {

sys/arch/arm/xscale/pxa2x0_mci.c

735

while (ISSET(CSR_READ_4(sc, MMC_STAT), STAT_CLK_EN)

sys/arch/arm/xscale/pxa2x0_mci.c

757

status = CSR_READ_4(sc, MMC_I_REG) & ~CSR_READ_4(sc, MMC_I_MASK);

sys/arch/arm/xscale/pxa2x0_mci.c

884

uint32_t h = CSR_READ_4(sc, MMC_RES) & 0xffff;

sys/arch/arm/xscale/pxa2x0_mci.c

885

uint32_t l = CSR_READ_4(sc, MMC_RES) & 0xffff;

sys/arch/arm/xscale/pxa2x0_mci.c

907

uint32_t h = CSR_READ_4(sc, MMC_RES) & 0xffff;

sys/arch/arm/xscale/pxa2x0_mci.c

908

uint32_t m = CSR_READ_4(sc, MMC_RES) & 0xffff;

sys/arch/arm/xscale/pxa2x0_mci.c

909

uint32_t l = CSR_READ_4(sc, MMC_RES) & 0xffff;

sys/arch/arm/xscale/pxa2x0_mci.c

916

status = CSR_READ_4(sc, MMC_STAT);

sys/arch/sandpoint/stand/altboot/fxp.c

520

while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) &

sys/arch/sandpoint/stand/altboot/pcn.c

157

(void)CSR_READ_4(l, PCN_32RESET);

sys/arch/sandpoint/stand/altboot/pcn.c

314

return CSR_READ_4(l, PCN_RDP);

sys/arch/sandpoint/stand/altboot/pcn.c

328

return CSR_READ_4(l, PCN_BDP);

sys/arch/sandpoint/stand/altboot/rge.c

323

v = CSR_READ_4(l, RGE_PHYAR);

sys/arch/sandpoint/stand/altboot/rge.c

338

v = CSR_READ_4(l, RGE_PHYAR);

sys/arch/sandpoint/stand/altboot/siisata.c

184

val = CSR_READ_4(ss); /* has completed */

sys/arch/sandpoint/stand/altboot/skg.c

463

val = CSR_READ_4(l, SK_GPIO);

sys/arch/sandpoint/stand/altboot/stg.c

363

reg = CSR_READ_4(l, STGE_AsicCtrl);

sys/arch/sandpoint/stand/altboot/stg.c

370

if ((CSR_READ_4(l, STGE_AsicCtrl) & AC_ResetBusy) == 0)

sys/dev/ic/bwi.c

10022

tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS_0);

sys/dev/ic/bwi.c

10025

(void)CSR_READ_4(sc, BWI_TXSTATUS_1);

sys/dev/ic/bwi.c

10084

val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);

sys/dev/ic/bwi.c

10136

busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);

sys/dev/ic/bwi.c

10154

val = CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/ic/bwi.c

10175

state_lo = CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/ic/bwi.c

10199

state_lo = CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/ic/bwi.c

10212

state_hi = CSR_READ_4(sc, BWI_STATE_HI);

sys/dev/ic/bwi.c

10232

CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/ic/bwi.c

10241

CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/ic/bwi.c

10260

CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/ic/bwi.c

10263

state_hi = CSR_READ_4(sc, BWI_STATE_HI);

sys/dev/ic/bwi.c

10267

imstate = CSR_READ_4(sc, BWI_IMSTATE);

sys/dev/ic/bwi.c

10280

CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/ic/bwi.c

10289

CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/ic/bwi.c

1237

return (CSR_READ_4(sc, BWI_MOBJ_DATA));

sys/dev/ic/bwi.c

1285

CSR_READ_4(mac->mac_sc, BWI_STATE_HI); /* dummy read */

sys/dev/ic/bwi.c

1511

state_lo = CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/ic/bwi.c

1517

CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/ic/bwi.c

1523

CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/ic/bwi.c

1528

status = CSR_READ_4(sc, BWI_MAC_STATUS);

sys/dev/ic/bwi.c

1614

val = CSR_READ_4(sc, BWI_MAC_STATUS);

sys/dev/ic/bwi.c

1621

val = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);

sys/dev/ic/bwi.c

1762

CSR_READ_4(sc, BWI_MAC_STATUS); /* dummy read */

sys/dev/ic/bwi.c

2119

intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);

sys/dev/ic/bwi.c

2131

CSR_READ_4(sc, BWI_MAC_INTR_STATUS); /* dummy read */

sys/dev/ic/bwi.c

2327

mac_status = CSR_READ_4(sc, BWI_MAC_STATUS);

sys/dev/ic/bwi.c

2512

CSR_READ_4(sc, BWI_MAC_STATUS);

sys/dev/ic/bwi.c

2513

CSR_READ_4(sc, BWI_MAC_INTR_STATUS);

sys/dev/ic/bwi.c

2531

CSR_READ_4(sc, BWI_MAC_STATUS);

sys/dev/ic/bwi.c

2535

if (CSR_READ_4(sc, BWI_MAC_INTR_STATUS) & BWI_INTR_READY)

sys/dev/ic/bwi.c

2554

status = CSR_READ_4(sc, BWI_MAC_STATUS);

sys/dev/ic/bwi.c

2561

CSR_READ_4(sc, BWI_MAC_STATUS);

sys/dev/ic/bwi.c

2626

val = CSR_READ_4(sc, BWI_MAC_STATUS);

sys/dev/ic/bwi.c

2631

val = CSR_READ_4(sc, BWI_MAC_STATUS);

sys/dev/ic/bwi.c

2643

val = CSR_READ_4(sc, BWI_STATE_HI);

sys/dev/ic/bwi.c

2653

if (CSR_READ_4(sc, txrx_reg) & BWI_TXRX32_CTRL_ADDRHI_MASK) {

sys/dev/ic/bwi.c

2996

CSR_READ_4(sc, BWI_MAC_STATUS);

sys/dev/ic/bwi.c

3157

CSR_READ_4(mac->mac_sc, BWI_MAC_STATUS);

sys/dev/ic/bwi.c

6617

val = CSR_READ_4(sc, BWI_ID_HI);

sys/dev/ic/bwi.c

6869

info = CSR_READ_4(sc, BWI_INFO);

sys/dev/ic/bwi.c

6874

sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);

sys/dev/ic/bwi.c

7009

val = CSR_READ_4(sc, BWI_FLAGS);

sys/dev/ic/bwi.c

7068

CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */

sys/dev/ic/bwi.c

7070

CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */

sys/dev/ic/bwi.c

7149

val = CSR_READ_4(sc, BWI_CLOCK_CTRL);

sys/dev/ic/bwi.c

7162

val = CSR_READ_4(sc, BWI_CLOCK_INFO);

sys/dev/ic/bwi.c

7210

clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);

sys/dev/ic/bwi.c

7333

if ((CSR_READ_4(sc, BWI_TXSTATUS_0) &

sys/dev/ic/bwi.c

7336

CSR_READ_4(sc, BWI_TXSTATUS_1);

sys/dev/ic/bwi.c

735

intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);

sys/dev/ic/bwi.c

761

CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;

sys/dev/ic/bwi.c

7675

CSR_READ_4(sc, BWI_MAC_INTR_MASK);

sys/dev/ic/bwi.c

7861

ctl = CSR_READ_4(sc, BWI_PIO_TXCTL(idx));

sys/dev/ic/bwi.c

804

if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8)

sys/dev/ic/bwi.c

8513

val = CSR_READ_4(sc, ctrl_base + BWI_RX32_CTRL);

sys/dev/ic/bwi.c

9079

val = CSR_READ_4(sc, BWI_PIO_RXCTL(qid));

sys/dev/ic/bwi.c

9088

val = CSR_READ_4(sc, BWI_PIO_RXCTL(qid));

sys/dev/ic/bwi.c

9149

val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);

sys/dev/ic/bwi.c

9179

status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);

sys/dev/ic/bwi.c

9249

val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);

sys/dev/ic/bwi.c

9264

val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);

sys/dev/ic/bwi.c

9910

val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);

sys/dev/ic/bwivar.h

100

CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))

sys/dev/ic/bwivar.h

105

CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))

sys/dev/ic/bwivar.h

95

CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))

sys/dev/ic/i82557.c

2123

while (((data = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) &

sys/dev/ic/i82557.c

2153

while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&

sys/dev/ic/rtl8169.c

2040

CSR_READ_4(sc, RTK_MISC) & ~RTK_MISC_RXDV_GATED_EN);

sys/dev/ic/rtl8169.c

2064

rxcfg = CSR_READ_4(sc, RTK_RXCFG);

sys/dev/ic/rtl8169.c

2320

CSR_WRITE_4(sc, RTK_RXCFG, CSR_READ_4(sc, RTK_RXCFG) &

sys/dev/ic/rtl8169.c

2326

CSR_READ_4(sc, RTK_MISC) | RTK_MISC_RXDV_GATED_EN);

sys/dev/ic/rtl8169.c

264

data = CSR_READ_4(sc, RTK_PHYAR);

sys/dev/ic/rtl8169.c

291

data = CSR_READ_4(sc, RTK_PHYAR);

sys/dev/ic/rtl8169.c

618

sc->sc_hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV;

sys/dev/ic/rtl81x9.c

1107

txstat = CSR_READ_4(sc, txd->txd_txstat);

sys/dev/ic/rtl81x9.c

1378

rxcfg = CSR_READ_4(sc, RTK_RXCFG);

sys/dev/ic/rtl81x9.c

534

rxfilt = CSR_READ_4(sc, RTK_RXCFG);

sys/dev/pci/if_age.c

1172

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/pci/if_age.c

1612

CSR_READ_4(sc, AGE_MASTER_CFG);

sys/dev/pci/if_age.c

1615

if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)

sys/dev/pci/if_age.c

1626

CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);

sys/dev/pci/if_age.c

1729

reg = CSR_READ_4(sc, AGE_MASTER_CFG);

sys/dev/pci/if_age.c

1771

CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);

sys/dev/pci/if_age.c

1791

reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN);

sys/dev/pci/if_age.c

1798

reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN);

sys/dev/pci/if_age.c

1883

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/pci/if_age.c

1943

CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB));

sys/dev/pci/if_age.c

1947

CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB);

sys/dev/pci/if_age.c

1949

CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB);

sys/dev/pci/if_age.c

1951

if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)

sys/dev/pci/if_age.c

2092

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/pci/if_age.c

2098

reg = CSR_READ_4(sc, AGE_DMA_CFG);

sys/dev/pci/if_age.c

2104

if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &

sys/dev/pci/if_age.c

2119

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/pci/if_age.c

2125

reg = CSR_READ_4(sc, AGE_DMA_CFG);

sys/dev/pci/if_age.c

2131

if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &

sys/dev/pci/if_age.c

214

sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >>

sys/dev/pci/if_age.c

222

CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN),

sys/dev/pci/if_age.c

223

CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN));

sys/dev/pci/if_age.c

2278

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/pci/if_age.c

2296

rxcfg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/pci/if_age.c

362

v = CSR_READ_4(sc, AGE_MDIO);

sys/dev/pci/if_age.c

396

v = CSR_READ_4(sc, AGE_MDIO);

sys/dev/pci/if_age.c

444

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/pci/if_age.c

446

CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) |

sys/dev/pci/if_age.c

496

status = CSR_READ_4(sc, AGE_INTR_STATUS);

sys/dev/pci/if_age.c

567

reg = CSR_READ_4(sc, AGE_SPI_CTRL);

sys/dev/pci/if_age.c

580

CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |

sys/dev/pci/if_age.c

584

reg = CSR_READ_4(sc, AGE_TWSI_CTRL);

sys/dev/pci/if_age.c

597

ea[0] = CSR_READ_4(sc, AGE_PAR0);

sys/dev/pci/if_age.c

598

ea[1] = CSR_READ_4(sc, AGE_PAR1);

sys/dev/pci/if_alc.c

1014

gphy = CSR_READ_4(sc, ALC_GPHY_CFG);

sys/dev/pci/if_alc.c

1066

pmcfg = CSR_READ_4(sc, ALC_PM_CFG);

sys/dev/pci/if_alc.c

1150

pmcfg = CSR_READ_4(sc, ALC_PM_CFG);

sys/dev/pci/if_alc.c

1188

val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);

sys/dev/pci/if_alc.c

1194

CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);

sys/dev/pci/if_alc.c

1196

CSR_READ_4(sc, ALC_PCIE_PHYMISC) |

sys/dev/pci/if_alc.c

1200

val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2);

sys/dev/pci/if_alc.c

1234

val = CSR_READ_4(sc, ALC_PDLL_TRNS1);

sys/dev/pci/if_alc.c

1237

val = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/pci/if_alc.c

1425

sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >>

sys/dev/pci/if_alc.c

1433

CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8,

sys/dev/pci/if_alc.c

1434

CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8);

sys/dev/pci/if_alc.c

2143

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/pci/if_alc.c

2190

CSR_READ_4(sc, ALC_RX_MIB_BASE + i);

sys/dev/pci/if_alc.c

2196

CSR_READ_4(sc, ALC_TX_MIB_BASE + i);

sys/dev/pci/if_alc.c

222

v = CSR_READ_4(sc, ALC_MDIO);

sys/dev/pci/if_alc.c

2224

*reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i);

sys/dev/pci/if_alc.c

2230

*reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i);

sys/dev/pci/if_alc.c

2326

status = CSR_READ_4(sc, ALC_INTR_STATUS);

sys/dev/pci/if_alc.c

2387

prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX);

sys/dev/pci/if_alc.c

254

v = CSR_READ_4(sc, ALC_MDIO);

sys/dev/pci/if_alc.c

2673

reg = CSR_READ_4(sc, ALC_MISC3);

sys/dev/pci/if_alc.c

2678

reg = CSR_READ_4(sc, ALC_MISC);

sys/dev/pci/if_alc.c

2689

reg = CSR_READ_4(sc, ALC_MISC2);

sys/dev/pci/if_alc.c

2719

pmcfg = CSR_READ_4(sc, ALC_PM_CFG);

sys/dev/pci/if_alc.c

2728

reg = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/pci/if_alc.c

2735

if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0)

sys/dev/pci/if_alc.c

2743

if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)

sys/dev/pci/if_alc.c

2750

reg = CSR_READ_4(sc, ALC_IDLE_STATUS);

sys/dev/pci/if_alc.c

2763

reg = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/pci/if_alc.c

2773

reg = CSR_READ_4(sc, ALC_MISC3);

sys/dev/pci/if_alc.c

2777

reg = CSR_READ_4(sc, ALC_MISC);

sys/dev/pci/if_alc.c

2788

CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN |

sys/dev/pci/if_alc.c

2851

CSR_READ_4(sc, ALC_WOL_CFG);

sys/dev/pci/if_alc.c

2933

reg = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/pci/if_alc.c

294

v = CSR_READ_4(sc, ALC_MDIO);

sys/dev/pci/if_alc.c

3058

reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);

sys/dev/pci/if_alc.c

3074

reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);

sys/dev/pci/if_alc.c

3216

reg = CSR_READ_4(sc, ALC_DMA_CFG);

sys/dev/pci/if_alc.c

323

v = CSR_READ_4(sc, ALC_MDIO);

sys/dev/pci/if_alc.c

3267

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/pci/if_alc.c

3273

reg = CSR_READ_4(sc, ALC_IDLE_STATUS);

sys/dev/pci/if_alc.c

3296

cfg = CSR_READ_4(sc, ALC_RXQ_CFG);

sys/dev/pci/if_alc.c

3304

cfg = CSR_READ_4(sc, ALC_TXQ_CFG);

sys/dev/pci/if_alc.c

3316

reg = CSR_READ_4(sc, ALC_RXQ_CFG);

sys/dev/pci/if_alc.c

3329

reg = CSR_READ_4(sc, ALC_TXQ_CFG);

sys/dev/pci/if_alc.c

3336

reg = CSR_READ_4(sc, ALC_IDLE_STATUS);

sys/dev/pci/if_alc.c

3443

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/pci/if_alc.c

3462

rxcfg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/pci/if_alc.c

371

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/pci/if_alc.c

425

v = CSR_READ_4(sc, ALC_MDIO);

sys/dev/pci/if_alc.c

457

v = CSR_READ_4(sc, ALC_MDIO);

sys/dev/pci/if_alc.c

619

opt = CSR_READ_4(sc, ALC_OPT_CFG);

sys/dev/pci/if_alc.c

620

if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 &&

sys/dev/pci/if_alc.c

621

(CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {

sys/dev/pci/if_alc.c

633

CSR_READ_4(sc, ALC_OPT_CFG);

sys/dev/pci/if_alc.c

658

CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);

sys/dev/pci/if_alc.c

660

CSR_READ_4(sc, ALC_WOL_CFG);

sys/dev/pci/if_alc.c

662

CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |

sys/dev/pci/if_alc.c

666

if ((CSR_READ_4(sc, ALC_TWSI_CFG) &

sys/dev/pci/if_alc.c

684

CSR_READ_4(sc, ALC_OPT_CFG);

sys/dev/pci/if_alc.c

721

reg = CSR_READ_4(sc, ALC_SLD);

sys/dev/pci/if_alc.c

730

reg = CSR_READ_4(sc, ALC_SLD);

sys/dev/pci/if_alc.c

743

reg = CSR_READ_4(sc, ALC_EEPROM_LD);

sys/dev/pci/if_alc.c

747

reg = CSR_READ_4(sc, ALC_EEPROM_LD);

sys/dev/pci/if_alc.c

758

reg = CSR_READ_4(sc, ALC_EEPROM_LD);

sys/dev/pci/if_alc.c

776

ea[0] = CSR_READ_4(sc, ALC_PAR0);

sys/dev/pci/if_alc.c

777

ea[1] = CSR_READ_4(sc, ALC_PAR1);

sys/dev/pci/if_alc.c

793

pmcfg = CSR_READ_4(sc, ALC_PM_CFG);

sys/dev/pci/if_alc.c

933

val = CSR_READ_4(sc, ALC_GPHY_CFG);

sys/dev/pci/if_alc.c

965

val = CSR_READ_4(sc, ALC_LPI_CTL);

sys/dev/pci/if_ale.c

1134

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/pci/if_ale.c

1166

CSR_READ_4(sc, ALE_RX_MIB_BASE + i);

sys/dev/pci/if_ale.c

1171

CSR_READ_4(sc, ALE_TX_MIB_BASE + i);

sys/dev/pci/if_ale.c

1190

*reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);

sys/dev/pci/if_ale.c

1195

*reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);

sys/dev/pci/if_ale.c

1290

status = CSR_READ_4(sc, ALE_INTR_STATUS);

sys/dev/pci/if_ale.c

155

v = CSR_READ_4(sc, ALE_MDIO);

sys/dev/pci/if_ale.c

1580

CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);

sys/dev/pci/if_ale.c

1585

if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)

sys/dev/pci/if_ale.c

1592

if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)

sys/dev/pci/if_ale.c

1635

CSR_READ_4(sc, ALE_WOL_CFG);

sys/dev/pci/if_ale.c

1694

reg = CSR_READ_4(sc, ALE_MASTER_CFG);

sys/dev/pci/if_ale.c

1758

reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);

sys/dev/pci/if_ale.c

1870

reg = CSR_READ_4(sc, ALE_TXQ_CFG);

sys/dev/pci/if_ale.c

1873

reg = CSR_READ_4(sc, ALE_RXQ_CFG);

sys/dev/pci/if_ale.c

1876

reg = CSR_READ_4(sc, ALE_DMA_CFG);

sys/dev/pci/if_ale.c

1906

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/pci/if_ale.c

1913

reg = CSR_READ_4(sc, ALE_IDLE_STATUS);

sys/dev/pci/if_ale.c

196

v = CSR_READ_4(sc, ALE_MDIO);

sys/dev/pci/if_ale.c

1973

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/pci/if_ale.c

1991

rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/pci/if_ale.c

246

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/pci/if_ale.c

296

reg = CSR_READ_4(sc, ALE_SPI_CTRL);

sys/dev/pci/if_ale.c

308

CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |

sys/dev/pci/if_ale.c

312

reg = CSR_READ_4(sc, ALE_TWSI_CTRL);

sys/dev/pci/if_ale.c

325

ea[0] = CSR_READ_4(sc, ALE_PAR0);

sys/dev/pci/if_ale.c

326

ea[1] = CSR_READ_4(sc, ALE_PAR1);

sys/dev/pci/if_ale.c

461

if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {

sys/dev/pci/if_ale.c

493

sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >>

sys/dev/pci/if_ale.c

502

txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN);

sys/dev/pci/if_ale.c

503

rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);

sys/dev/pci/if_bge.c

1046

if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)

sys/dev/pci/if_bge.c

1056

byte = CSR_READ_4(sc, BGE_EE_DATA);

sys/dev/pci/if_bge.c

1098

autopoll = CSR_READ_4(sc, BGE_MI_MODE);

sys/dev/pci/if_bge.c

1110

data = CSR_READ_4(sc, BGE_MI_COMM);

sys/dev/pci/if_bge.c

1113

data = CSR_READ_4(sc, BGE_MI_COMM);

sys/dev/pci/if_bge.c

1157

autopoll = CSR_READ_4(sc, BGE_MI_MODE);

sys/dev/pci/if_bge.c

1169

data = CSR_READ_4(sc, BGE_MI_COMM);

sys/dev/pci/if_bge.c

1172

data = CSR_READ_4(sc, BGE_MI_COMM);

sys/dev/pci/if_bge.c

1225

mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &

sys/dev/pci/if_bge.c

1227

tx_mode = CSR_READ_4(sc, BGE_TX_MODE);

sys/dev/pci/if_bge.c

1228

rx_mode = CSR_READ_4(sc, BGE_RX_MODE);

sys/dev/pci/if_bge.c

1970

if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &

sys/dev/pci/if_bge.c

1986

CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);

sys/dev/pci/if_bge.c

2000

val = CSR_READ_4(sc, BGE_VCPU_STATUS);

sys/dev/pci/if_bge.c

2074

phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) &

sys/dev/pci/if_bge.c

2077

phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &

sys/dev/pci/if_bge.c

2117

mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);

sys/dev/pci/if_bge.c

2124

reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG +

sys/dev/pci/if_bge.c

2136

mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);

sys/dev/pci/if_bge.c

2144

reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG +

sys/dev/pci/if_bge.c

2158

reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);

sys/dev/pci/if_bge.c

2163

mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);

sys/dev/pci/if_bge.c

2171

reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG +

sys/dev/pci/if_bge.c

2181

reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);

sys/dev/pci/if_bge.c

2235

tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;

sys/dev/pci/if_bge.c

2290

mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &

sys/dev/pci/if_bge.c

2438

if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)

sys/dev/pci/if_bge.c

2455

if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)

sys/dev/pci/if_bge.c

2601

(CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);

sys/dev/pci/if_bge.c

2725

val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &

sys/dev/pci/if_bge.c

2746

val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK);

sys/dev/pci/if_bge.c

2763

if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))

sys/dev/pci/if_bge.c

2864

CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */

sys/dev/pci/if_bge.c

2916

val |= CSR_READ_4(sc, BGE_RDMA_MODE) &

sys/dev/pci/if_bge.c

2934

dmactl = CSR_READ_4(sc, rdmareg);

sys/dev/pci/if_bge.c

2959

CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |

sys/dev/pci/if_bge.c

2968

CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |

sys/dev/pci/if_bge.c

2973

CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |

sys/dev/pci/if_bge.c

2984

val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);

sys/dev/pci/if_bge.c

2991

val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);

sys/dev/pci/if_bge.c

3503

misccfg = CSR_READ_4(sc, BGE_MISC_CFG);

sys/dev/pci/if_bge.c

3606

else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL)

sys/dev/pci/if_bge.c

3948

macmode = CSR_READ_4(sc, BGE_MAC_MODE);

sys/dev/pci/if_bge.c

4209

mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;

sys/dev/pci/if_bge.c

4227

if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &

sys/dev/pci/if_bge.c

4266

val = CSR_READ_4(sc, BGE_PCIE_LINKCTL);

sys/dev/pci/if_bge.c

4280

(CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) ==

sys/dev/pci/if_bge.c

4297

i = CSR_READ_4(sc, BGE_VCPU_STATUS);

sys/dev/pci/if_bge.c

4300

i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);

sys/dev/pci/if_bge.c

4396

val = CSR_READ_4(sc, BGE_MARB_MODE);

sys/dev/pci/if_bge.c

4430

val = CSR_READ_4(sc, BGE_MAC_MODE);

sys/dev/pci/if_bge.c

4447

serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);

sys/dev/pci/if_bge.c

4459

v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG);

sys/dev/pci/if_bge.c

4755

pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE);

sys/dev/pci/if_bge.c

4811

(void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);

sys/dev/pci/if_bge.c

4815

(void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);

sys/dev/pci/if_bge.c

4849

CSR_READ_4(sc, BGE_RX_CPU_EVENT) |

sys/dev/pci/if_bge.c

4904

CSR_READ_4(sc, BGE_MAC_STATS +

sys/dev/pci/if_bge.c

4917

CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS));

sys/dev/pci/if_bge.c

4920

CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS));

sys/dev/pci/if_bge.c

4922

CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS));

sys/dev/pci/if_bge.c

4929

ucast = CSR_READ_4(sc, BGE_MAC_STATS +

sys/dev/pci/if_bge.c

4931

mcast = CSR_READ_4(sc, BGE_MAC_STATS +

sys/dev/pci/if_bge.c

4933

bcast = CSR_READ_4(sc, BGE_MAC_STATS +

sys/dev/pci/if_bge.c

4942

val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);

sys/dev/pci/if_bge.c

4960

CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))

sys/dev/pci/if_bge.c

5614

reg = CSR_READ_4(sc, BGE_CPMU_CTRL);

sys/dev/pci/if_bge.c

5619

reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);

sys/dev/pci/if_bge.c

5624

reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD);

sys/dev/pci/if_bge.c

5629

reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC);

sys/dev/pci/if_bge.c

5638

reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH);

sys/dev/pci/if_bge.c

5644

reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY);

sys/dev/pci/if_bge.c

5655

reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL);

sys/dev/pci/if_bge.c

5732

mode = CSR_READ_4(sc, BGE_TX_MODE);

sys/dev/pci/if_bge.c

5739

mode |= CSR_READ_4(sc, BGE_TX_MODE) &

sys/dev/pci/if_bge.c

5750

mode = CSR_READ_4(sc, BGE_RX_MODE);

sys/dev/pci/if_bge.c

5822

sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);

sys/dev/pci/if_bge.c

5825

sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);

sys/dev/pci/if_bge.c

5858

reg = CSR_READ_4(sc, BGE_CPMU_CTRL);

sys/dev/pci/if_bge.c

5872

reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK);

sys/dev/pci/if_bge.c

5912

if (CSR_READ_4(sc, BGE_MAC_STS) &

sys/dev/pci/if_bge.c

5916

if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)

sys/dev/pci/if_bge.c

6042

if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) {

sys/dev/pci/if_bge.c

6043

const uint32_t status = CSR_READ_4(sc, BGE_RX_STS);

sys/dev/pci/if_bge.c

6125

if ((CSR_READ_4(sc, reg) & bit) == 0)

sys/dev/pci/if_bge.c

6285

status = CSR_READ_4(sc, BGE_MAC_STS);

sys/dev/pci/if_bge.c

6310

status = CSR_READ_4(sc, BGE_MAC_STS);

sys/dev/pci/if_bge.c

6333

link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)?

sys/dev/pci/if_bge.c

6359

reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) &

sys/dev/pci/if_bge.c

6368

reg = CSR_READ_4(sc, BGE_MISC_CFG) &

sys/dev/pci/if_bge.c

955

if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)

sys/dev/pci/if_bge.c

963

access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);

sys/dev/pci/if_bge.c

970

if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {

sys/dev/pci/if_bge.c

982

byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);

sys/dev/pci/if_bgereg.h

2226

val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \

sys/dev/pci/if_bgevar.h

109

CSR_READ_4(sc, reg); \

sys/dev/pci/if_bgevar.h

113

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))

sys/dev/pci/if_bgevar.h

117

CSR_READ_4(sc, reg); \

sys/dev/pci/if_bgevar.h

120

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))

sys/dev/pci/if_bgevar.h

124

CSR_READ_4(sc, reg); \

sys/dev/pci/if_et.c

1023

intrs = CSR_READ_4(sc, ET_INTR_STATUS);

sys/dev/pci/if_et.c

1211

if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) {

sys/dev/pci/if_et.c

1286

pktfilt = CSR_READ_4(sc, ET_PKTFILT);

sys/dev/pci/if_et.c

1287

rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL);

sys/dev/pci/if_et.c

1711

if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) {

sys/dev/pci/if_et.c

1978

tx_done = CSR_READ_4(sc, ET_TX_DONE_POS);

sys/dev/pci/if_et.c

380

data = CSR_READ_4(sc, ET_MII_IND);

sys/dev/pci/if_et.c

394

data = CSR_READ_4(sc, ET_MII_STAT);

sys/dev/pci/if_et.c

426

data = CSR_READ_4(sc, ET_MII_IND);

sys/dev/pci/if_et.c

474

ctrl = CSR_READ_4(sc, ET_MAC_CTRL);

sys/dev/pci/if_et.c

476

cfg1 = CSR_READ_4(sc, ET_MAC_CFG1);

sys/dev/pci/if_et.c

479

cfg2 = CSR_READ_4(sc, ET_MAC_CFG2);

sys/dev/pci/if_et.c

523

cfg1 = CSR_READ_4(sc, ET_MAC_CFG1);

sys/dev/pci/if_ipw.c

1118

r = CSR_READ_4(sc, IPW_CSR_RX_READ);

sys/dev/pci/if_ipw.c

1227

r = CSR_READ_4(sc, IPW_CSR_TX_READ);

sys/dev/pci/if_ipw.c

1255

r = CSR_READ_4(sc, IPW_CSR_INTR);

sys/dev/pci/if_ipw.c

1273

r = CSR_READ_4(sc, IPW_CSR_INTR);

sys/dev/pci/if_ipw.c

146

return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA);

sys/dev/pci/if_ipw.c

1595

size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA);

sys/dev/pci/if_ipw.c

1600

addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA);

sys/dev/pci/if_ipw.c

1619

else if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED)

sys/dev/pci/if_ipw.c

1747

if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED)

sys/dev/pci/if_ipw.c

1754

CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) |

sys/dev/pci/if_ipw.c

1768

CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) |

sys/dev/pci/if_ipw.c

1773

if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY)

sys/dev/pci/if_ipw.c

1780

CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) |

sys/dev/pci/if_ipw.c

1785

CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) |

sys/dev/pci/if_ipw.c

1872

CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) |

sys/dev/pci/if_ipw.c

1883

CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) |

sys/dev/pci/if_ipw.c

2236

sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE);

sys/dev/pci/if_ipw.c

2237

sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE);

sys/dev/pci/if_iwi.c

1370

(void)CSR_READ_4(sc, IWI_CSR_CMD_RIDX);

sys/dev/pci/if_iwi.c

1393

hw = CSR_READ_4(sc, IWI_CSR_RX_RIDX);

sys/dev/pci/if_iwi.c

1442

hw = CSR_READ_4(sc, txq->csr_ridx);

sys/dev/pci/if_iwi.c

1481

if ((r = CSR_READ_4(sc, IWI_CSR_INTR)) == 0 || r == 0xffffffff)

sys/dev/pci/if_iwi.c

1498

if ((r = CSR_READ_4(sc, IWI_CSR_INTR)) == 0 || r == 0xffffffff)

sys/dev/pci/if_iwi.c

161

return CSR_READ_4(sc, IWI_CSR_INDIRECT_DATA);

sys/dev/pci/if_iwi.c

1868

size = uimin(CSR_READ_4(sc, IWI_CSR_TABLE0_SIZE), 128 - 1);

sys/dev/pci/if_iwi.c

1958

if (CSR_READ_4(sc, IWI_CSR_RST) & IWI_RST_MASTER_DISABLED)

sys/dev/pci/if_iwi.c

1965

CSR_WRITE_4(sc, IWI_CSR_RST, CSR_READ_4(sc, IWI_CSR_RST) |

sys/dev/pci/if_iwi.c

1979

CSR_WRITE_4(sc, IWI_CSR_CTL, CSR_READ_4(sc, IWI_CSR_CTL) |

sys/dev/pci/if_iwi.c

1987

if (CSR_READ_4(sc, IWI_CSR_CTL) & IWI_CTL_CLOCK_READY)

sys/dev/pci/if_iwi.c

1997

CSR_WRITE_4(sc, IWI_CSR_RST, CSR_READ_4(sc, IWI_CSR_RST) |

sys/dev/pci/if_iwi.c

2002

CSR_WRITE_4(sc, IWI_CSR_CTL, CSR_READ_4(sc, IWI_CSR_CTL) |

sys/dev/pci/if_iwi.c

2019

CSR_WRITE_4(sc, IWI_CSR_RST, CSR_READ_4(sc, IWI_CSR_RST) |

sys/dev/pci/if_iwi.c

2022

if (CSR_READ_4(sc, IWI_CSR_RST) & IWI_RST_MASTER_DISABLED)

sys/dev/pci/if_iwi.c

2033

CSR_WRITE_4(sc, IWI_CSR_RST, CSR_READ_4(sc, IWI_CSR_RST) &

sys/dev/pci/if_iwi.c

2161

sentinel = CSR_READ_4(sc, IWI_CSR_AUTOINC_ADDR);

sys/dev/pci/if_iwi.c

2164

CSR_WRITE_4(sc, IWI_CSR_RST, CSR_READ_4(sc, IWI_CSR_RST) &

sys/dev/pci/if_iwi.c

2190

CSR_WRITE_4(sc, IWI_CSR_CTL, CSR_READ_4(sc, IWI_CSR_CTL) |

sys/dev/pci/if_iwi.c

2815

return (CSR_READ_4(sc, IWI_CSR_IO) & IWI_IO_RADIO_ENABLED) == 0;

sys/dev/pci/if_iwi.c

887

rate = iwi_cvtrate(CSR_READ_4(sc, IWI_CSR_CURRENT_TX_RATE));

sys/dev/pci/if_kse.c

1190

if ((isr = CSR_READ_4(sc, INTST)) == 0)

sys/dev/pci/if_msk.c

2310

status = CSR_READ_4(sc, SK_Y2_ISSR2);

sys/dev/pci/if_msk.c

2318

status = CSR_READ_4(sc, SK_ISR);

sys/dev/pci/if_msk.c

2403

CSR_READ_4(sc_if->sk_softc, SK_CSR)));

sys/dev/pci/if_msk.c

247

return CSR_READ_4(sc, reg);

sys/dev/pci/if_re_pci.c

314

hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV;

sys/dev/pci/if_sk.c

2323

status = CSR_READ_4(sc, SK_ISSR);

sys/dev/pci/if_sk.c

2580

CSR_READ_4(sc_if->sk_softc, SK_CSR)));

sys/dev/pci/if_sk.c

263

return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg));

sys/dev/pci/if_sk.c

265

return CSR_READ_4(sc, reg);

sys/dev/pci/if_sk.c

2849

CSR_READ_4(sc, SK_ISSR);

sys/dev/pci/if_stge.c

1137

txstat = CSR_READ_4(sc, STGE_TxStatus);

sys/dev/pci/if_stge.c

1430

(void) CSR_READ_4(sc, STGE_OctetRcvOk);

sys/dev/pci/if_stge.c

1432

(void) CSR_READ_4(sc, STGE_FramesRcvdOk);

sys/dev/pci/if_stge.c

1439

(void) CSR_READ_4(sc, STGE_OctetXmtdOk);

sys/dev/pci/if_stge.c

1442

CSR_READ_4(sc, STGE_FramesXmtdOk));

sys/dev/pci/if_stge.c

1445

CSR_READ_4(sc, STGE_LateCollisions) +

sys/dev/pci/if_stge.c

1446

CSR_READ_4(sc, STGE_MultiColFrames) +

sys/dev/pci/if_stge.c

1447

CSR_READ_4(sc, STGE_SingleColFrames));

sys/dev/pci/if_stge.c

1467

ac = CSR_READ_4(sc, STGE_AsicCtrl);

sys/dev/pci/if_stge.c

1483

if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)

sys/dev/pci/if_stge.c

565

if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)

sys/dev/pci/if_stge.c

792

if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)

sys/dev/pci/if_ti.c

1155

intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);

sys/dev/pci/if_ti.c

1225

if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {

sys/dev/pci/if_ti.c

1229

if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {

sys/dev/pci/if_ti.c

1267

if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {

sys/dev/pci/if_ti.c

1277

rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK;

sys/dev/pci/if_ti.c

1309

cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG));

sys/dev/pci/if_ti.c

1317

if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG)

sys/dev/pci/if_ti.c

1334

CSR_READ_4(sc, PCI_COMMAND_STATUS_REG)

sys/dev/pci/if_ti.c

2158

if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE))

sys/dev/pci/if_ti.c

2415

prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);

sys/dev/pci/if_ti.c

244

ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;

sys/dev/pci/if_ti.c

2647

media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);

sys/dev/pci/if_ti.c

2657

media = CSR_READ_4(sc, TI_GCR_LINK_STAT);

sys/dev/pci/if_ti.c

268

device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));

sys/dev/pci/if_ti.c

277

device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));

sys/dev/pci/if_ti.c

285

device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));

sys/dev/pci/if_ti.c

296

device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));

sys/dev/pci/if_ti.c

307

if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)

sys/dev/pci/if_tireg.h

977

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))

sys/dev/pci/if_tireg.h

979

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))

sys/dev/pci/if_vge.c

1469

status = CSR_READ_4(sc, VGE_ISR);

sys/dev/pci/if_vge.c

279

CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (x))

sys/dev/pci/if_vge.c

286

CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(x))

sys/dev/pci/if_vr.c

346

CSR_READ_4(sc, reg) | (x))

sys/dev/pci/if_vr.c

350

CSR_READ_4(sc, reg) & ~(x))