sys/arch/evbarm/stand/boot2440/dm9000.c

348

(void) CSR_READ_2(l, MRCMDX); /* dummy read */

sys/arch/evbarm/stand/boot2440/dm9000.c

349

mark = CSR_READ_2(l, MRCMDX); /* mark in [7:0] */

sys/arch/evbarm/stand/boot2440/dm9000.c

357

stat = CSR_READ_2(l, MRCMD); /* stat in [15:8] */

sys/arch/evbarm/stand/boot2440/dm9000.c

358

len = CSR_READ_2(l, MRCMD);

sys/arch/evbarm/stand/boot2440/dm9000.c

363

(void) CSR_READ_2(l, MRCMD);

sys/arch/evbarm/stand/boot2440/dm9000.c

373

val = CSR_READ_2(l, MRCMD);

sys/arch/evbarm/stand/boot2440/dm9000.c

380

(void) CSR_READ_2(l, MRCMD);

sys/arch/sandpoint/stand/altboot/fxp.c

449

if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) &

sys/arch/sandpoint/stand/altboot/fxp.c

487

if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) &

sys/arch/sandpoint/stand/altboot/kse.c

138

i = CSR_READ_2(l, MARL);

sys/arch/sandpoint/stand/altboot/kse.c

141

i = CSR_READ_2(l, MARM);

sys/arch/sandpoint/stand/altboot/kse.c

144

i = CSR_READ_2(l, MARH);

sys/arch/sandpoint/stand/altboot/kse.c

157

val = CSR_READ_2(l, P1SR);

sys/arch/sandpoint/stand/altboot/kse.c

267

val = CSR_READ_2(l, P1SR);

sys/arch/sandpoint/stand/altboot/nvt.c

355

v = CSR_READ_2(l, VR_MIIDATA);

sys/arch/sandpoint/stand/altboot/pcn.c

156

(void)CSR_READ_2(l, PCN_16RESET);

sys/arch/sandpoint/stand/altboot/skg.c

321

reg = CSR_READ_2(l, YUKON_GPCR);

sys/arch/sandpoint/stand/altboot/skg.c

408

v = CSR_READ_2(l, YUKON_SMICR);

sys/arch/sandpoint/stand/altboot/skg.c

414

return CSR_READ_2(l, YUKON_SMIDR);

sys/arch/sandpoint/stand/altboot/skg.c

428

v = CSR_READ_2(l, YUKON_SMICR);

sys/arch/sandpoint/stand/altboot/stg.c

197

addr[i] = le16toh(CSR_READ_2(l, STGE_EepromData));

sys/arch/sandpoint/stand/altboot/stg.c

245

CSR_READ_2(l, STGE_DebugCtrl) | 0x0200);

sys/arch/sandpoint/stand/altboot/stg.c

247

CSR_READ_2(l, STGE_DebugCtrl) | 0x0010);

sys/arch/sandpoint/stand/altboot/stg.c

249

CSR_READ_2(l, STGE_DebugCtrl) | 0x0020);

sys/arch/sandpoint/stand/altboot/stg.c

552

if ((CSR_READ_2(l, STGE_EepromCtrl) & EC_EepromBusy) == 0)

sys/arch/sandpoint/stand/altboot/vge.c

437

v = CSR_READ_2(l, VR_MIIDATA);

sys/dev/ic/an.c

1384

fid = CSR_READ_2(sc, AN_RX_FID);

sys/dev/ic/an.c

1544

fid = CSR_READ_2(sc, AN_TX_CMP_FID);

sys/dev/ic/an.c

1583

status = CSR_READ_2(sc, AN_LINKSTAT);

sys/dev/ic/an.c

1606

if (CSR_READ_2(sc, AN_COMMAND) & AN_CMD_BUSY) {

sys/dev/ic/an.c

1609

CSR_READ_2(sc, AN_COMMAND));

sys/dev/ic/an.c

1624

if (CSR_READ_2(sc, AN_EVENT_STAT) & AN_EV_CMD)

sys/dev/ic/an.c

1629

status = CSR_READ_2(sc, AN_STATUS);

sys/dev/ic/an.c

1632

if (CSR_READ_2(sc, AN_COMMAND) & AN_CMD_BUSY)

sys/dev/ic/an.c

1649

CSR_READ_2(sc, AN_RESP0), CSR_READ_2(sc, AN_RESP1),

sys/dev/ic/an.c

1650

CSR_READ_2(sc, AN_RESP2));

sys/dev/ic/an.c

1668

if (CSR_READ_2(sc, AN_EVENT_STAT) & AN_EV_CMD)

sys/dev/ic/an.c

1684

status = CSR_READ_2(sc, AN_OFF0);

sys/dev/ic/an.c

1793

if (CSR_READ_2(sc, AN_EVENT_STAT) & AN_EV_ALLOC)

sys/dev/ic/an.c

1802

*idp = CSR_READ_2(sc, AN_ALLOC_FID);

sys/dev/ic/an.c

494

if (CSR_READ_2(sc, AN_SW0) != AN_MAGIC) {

sys/dev/ic/an.c

496

CSR_READ_2(sc, AN_SW0)));

sys/dev/ic/an.c

500

status = CSR_READ_2(sc, AN_EVENT_STAT);

sys/dev/ic/bwi.c

1213

return (CSR_READ_2(sc, data_reg));

sys/dev/ic/bwi.c

1227

ret = CSR_READ_2(sc, BWI_MOBJ_DATA_UNALIGN);

sys/dev/ic/bwi.c

1232

ret |= CSR_READ_2(sc, BWI_MOBJ_DATA);

sys/dev/ic/bwi.c

1779

if (CSR_READ_2(sc, 0x50e) & 0x80)

sys/dev/ic/bwi.c

1784

if (CSR_READ_2(sc, 0x50e) & 0x400)

sys/dev/ic/bwi.c

1789

if ((CSR_READ_2(sc, 0x690) & 0x100) == 0)

sys/dev/ic/bwi.c

3010

CSR_READ_2(sc, BWI_PHYINFO); /* dummy read */

sys/dev/ic/bwi.c

3055

return (CSR_READ_2(sc, BWI_PHY_DATA));

sys/dev/ic/bwi.c

3068

val = CSR_READ_2(sc, BWI_PHYINFO);

sys/dev/ic/bwi.c

3985

return (CSR_READ_2(sc, BWI_RF_DATA_LO));

sys/dev/ic/bwi.c

4016

val = CSR_READ_2(sc, BWI_RF_DATA_HI);

sys/dev/ic/bwi.c

4020

val |= CSR_READ_2(sc, BWI_RF_DATA_LO);

sys/dev/ic/bwi.c

4545

bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL);

sys/dev/ic/bwi.c

4581

bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);

sys/dev/ic/bwi.c

4582

rf_chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);

sys/dev/ic/bwi.c

5056

ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);

sys/dev/ic/bwi.c

5058

chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);

sys/dev/ic/bwi.c

5436

ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);

sys/dev/ic/bwi.c

5437

(void)CSR_READ_2(sc, BWI_BBP_ATTEN);

sys/dev/ic/bwi.c

5438

chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);

sys/dev/ic/bwi.c

5711

ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);

sys/dev/ic/bwi.c

5719

bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);

sys/dev/ic/bwi.c

5720

chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);

sys/dev/ic/bwi.c

6367

bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL);

sys/dev/ic/bwi.c

6462

return (CSR_READ_2(sc, ofs + BWI_SPROM_START));

sys/dev/ic/bwi.c

6714

val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);

sys/dev/ic/bwi.c

6800

val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);

sys/dev/ic/bwi.c

6821

val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);

sys/dev/ic/bwivar.h

102

CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))

sys/dev/ic/bwivar.h

107

CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))

sys/dev/ic/bwivar.h

97

CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))

sys/dev/ic/i82557.c

671

if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) &

sys/dev/ic/i82557.c

719

if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) &

sys/dev/ic/i82557.c

759

if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) &

sys/dev/ic/rtl8169.c

1597

status = CSR_READ_2(sc, RTK_ISR);

sys/dev/ic/rtl8169.c

355

*val = CSR_READ_2(sc, re8139_reg);

sys/dev/ic/rtl8169.c

525

status = CSR_READ_2(sc, RTK_ISR);

sys/dev/ic/rtl81x9.c

1183

status = CSR_READ_2(sc, RTK_ISR);

sys/dev/ic/rtl81x9.c

324

ack = CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN;

sys/dev/ic/rtl81x9.c

347

if (CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN)

sys/dev/ic/rtl81x9.c

450

*val = CSR_READ_2(sc, rtk8139_reg);

sys/dev/ic/rtl81x9.c

923

cur_rx = (CSR_READ_2(sc, RTK_CURRXADDR) + 16) % RTK_RXBUFLEN;

sys/dev/ic/rtl81x9.c

926

limit = CSR_READ_2(sc, RTK_CURRXBUF) % RTK_RXBUFLEN;

sys/dev/ic/wi.c

1661

fid = CSR_READ_2(sc, WI_RX_FID);

sys/dev/ic/wi.c

1788

fid = CSR_READ_2(sc, WI_TX_CMP_FID);

sys/dev/ic/wi.c

1864

fid = CSR_READ_2(sc, WI_ALLOC_FID);

sys/dev/ic/wi.c

1969

fid = CSR_READ_2(sc, WI_TX_CMP_FID);

sys/dev/ic/wi.c

2024

fid = CSR_READ_2(sc, WI_INFO_FID);

sys/dev/ic/wi.c

2783

if ((CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY) == 0)

sys/dev/ic/wi.c

2873

if (CSR_READ_2(sc, WI_EVENT_STAT) & WI_EV_CMD)

sys/dev/ic/wi.c

2895

status = CSR_READ_2(sc, WI_STATUS);

sys/dev/ic/wi.c

2928

status = CSR_READ_2(sc, WI_OFF0);

sys/dev/ic/wi.c

3022

if (CSR_READ_2(sc, WI_DATA0) != 0x1234 ||

sys/dev/ic/wi.c

3023

CSR_READ_2(sc, WI_DATA0) != 0x5678) {

sys/dev/ic/wi.c

3071

if (CSR_READ_2(sc, WI_EVENT_STAT) & WI_EV_ALLOC)

sys/dev/ic/wi.c

3079

*idp = CSR_READ_2(sc, WI_ALLOC_FID);

sys/dev/ic/wi.c

655

status = CSR_READ_2(sc, WI_EVENT_STAT);

sys/dev/ic/wi.c

691

status = CSR_READ_2(sc, WI_EVENT_STAT);

sys/dev/pci/if_alc.c

1069

linkcfg = CSR_READ_2(sc, sc->alc_expcap +

sys/dev/pci/if_alc.c

820

CSR_READ_2(sc, ALC_GPHY_CFG);

sys/dev/pci/if_alc.c

825

CSR_READ_2(sc, ALC_GPHY_CFG);

sys/dev/pci/if_ale.c

1346

prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX);

sys/dev/pci/if_kse.c

1331

uint16_t p1sr = CSR_READ_2(sc, P1SR);

sys/dev/pci/if_kse.c

1382

printf("p1sr: %04x, p2sr: %04x\n", CSR_READ_2(sc, P1SR), CSR_READ_2(sc, P2SR));

sys/dev/pci/if_kse.c

1425

*val = CSR_READ_2(sc, phy1csr[reg]);

sys/dev/pci/if_kse.c

1448

uint16_t p1sr = CSR_READ_2(sc, P1SR);

sys/dev/pci/if_kse.c

1512

val = CSR_READ_2(sc, IADR5) << 16;

sys/dev/pci/if_kse.c

1515

(void)CSR_READ_2(sc, IADR4);

sys/dev/pci/if_kse.c

1520

val |= CSR_READ_2(sc, IADR4); /* 15:0 */

sys/dev/pci/if_kse.c

1526

ee->pev[p][32].ev_count += CSR_READ_2(sc, IADR4); /* ev32 */

sys/dev/pci/if_kse.c

1528

ee->pev[p][33].ev_count += CSR_READ_2(sc, IADR4); /* ev33 */

sys/dev/pci/if_kse.c

1545

val = CSR_READ_2(sc, IADR5) << 16;

sys/dev/pci/if_kse.c

1547

(void)CSR_READ_2(sc, IADR4);

sys/dev/pci/if_kse.c

1551

(void)CSR_READ_2(sc, IADR4);

sys/dev/pci/if_kse.c

1553

(void)CSR_READ_2(sc, IADR4);

sys/dev/pci/if_kse.c

436

i = CSR_READ_2(sc, MARL);

sys/dev/pci/if_kse.c

439

i = CSR_READ_2(sc, MARM);

sys/dev/pci/if_kse.c

442

i = CSR_READ_2(sc, MARH);

sys/dev/pci/if_kse.c

801

i = CSR_READ_2(sc, SGCR3);

sys/dev/pci/if_msk.c

1018

CSR_READ_2(sc, SK_LINK_CTRL)));

sys/dev/pci/if_msk.c

2369

if (CSR_READ_2(sc, SK_STAT_BMU_PUTIDX) == sc->sk_status_idx) {

sys/dev/pci/if_msk.c

253

return CSR_READ_2(sc, reg);

sys/dev/pci/if_msk.c

935

status = CSR_READ_2(sc, SK_Y2_ASF_HCU_CCSR);

sys/dev/pci/if_sk.c

1165

DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR)));

sys/dev/pci/if_sk.c

1167

CSR_READ_2(sc, SK_LINK_CTRL)));

sys/dev/pci/if_sk.c

274

return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg));

sys/dev/pci/if_sk.c

276

return CSR_READ_2(sc, reg);

sys/dev/pci/if_stge.c

1089

if ((CSR_READ_2(sc, STGE_IntStatus) & IS_InterruptStatus) == 0)

sys/dev/pci/if_stge.c

1093

isr = CSR_READ_2(sc, STGE_IntStatusAck);

sys/dev/pci/if_stge.c

1437

(u_int) CSR_READ_2(sc, STGE_FramesLostRxErrors));

sys/dev/pci/if_stge.c

1450

(u_int) CSR_READ_2(sc, STGE_FramesAbortXSColls) +

sys/dev/pci/if_stge.c

1451

(u_int) CSR_READ_2(sc, STGE_FramesWEXDeferal));

sys/dev/pci/if_stge.c

1668

CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200);

sys/dev/pci/if_stge.c

1672

CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010);

sys/dev/pci/if_stge.c

1675

CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020);

sys/dev/pci/if_stge.c

1791

if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0)

sys/dev/pci/if_stge.c

1815

*data = CSR_READ_2(sc, STGE_EepromData);

sys/dev/pci/if_stge.c

583

enaddr[0] = CSR_READ_2(sc, STGE_StationAddress0) & 0xff;

sys/dev/pci/if_stge.c

584

enaddr[1] = CSR_READ_2(sc, STGE_StationAddress0) >> 8;

sys/dev/pci/if_stge.c

585

enaddr[2] = CSR_READ_2(sc, STGE_StationAddress1) & 0xff;

sys/dev/pci/if_stge.c

586

enaddr[3] = CSR_READ_2(sc, STGE_StationAddress1) >> 8;

sys/dev/pci/if_stge.c

587

enaddr[4] = CSR_READ_2(sc, STGE_StationAddress2) & 0xff;

sys/dev/pci/if_stge.c

588

enaddr[5] = CSR_READ_2(sc, STGE_StationAddress2) >> 8;

sys/dev/pci/if_vge.c

277

CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (x))

sys/dev/pci/if_vge.c

284

CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(x))

sys/dev/pci/if_vge.c

397

word = CSR_READ_2(sc, VGE_EERDDAT);

sys/dev/pci/if_vge.c

496

*val = CSR_READ_2(sc, VGE_MIIDATA);

sys/dev/pci/if_vr.c

338

CSR_READ_2(sc, reg) | (x))

sys/dev/pci/if_vr.c

342

CSR_READ_2(sc, reg) & ~(x))

sys/dev/pci/if_vr.c

425

if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON | VR_CMD_RX_ON))

sys/dev/pci/if_vr.c

440

if (!(CSR_READ_2(sc, VR_COMMAND) &

sys/dev/pci/if_vr.c

529

if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET))

sys/dev/pci/if_vr.c

813

if ((CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON) == 0)

sys/dev/pci/if_vr.c

859

if ((CSR_READ_2(sc, VR_COMMAND) &

sys/dev/pci/if_vr.c

929

status = CSR_READ_2(sc, VR_ISR);

sys/dev/pci/if_vte.c

1211

mdcsc = CSR_READ_2(sc, VTE_MDCSC);

sys/dev/pci/if_vte.c

1212

mcr = CSR_READ_2(sc, VTE_MCR1);

sys/dev/pci/if_vte.c

1216

if ((CSR_READ_2(sc, VTE_MCR1) & MCR1_MAC_RESET) == 0)

sys/dev/pci/if_vte.c

1358

DPRINTF(("before ipend 0x%x 0x%x\n", CSR_READ_2(sc, VTE_MIER),

sys/dev/pci/if_vte.c

1359

CSR_READ_2(sc, VTE_MISR)));

sys/dev/pci/if_vte.c

1375

DPRINTF(("ipend 0x%x 0x%x\n", CSR_READ_2(sc, VTE_MIER),

sys/dev/pci/if_vte.c

1376

CSR_READ_2(sc, VTE_MISR)));

sys/dev/pci/if_vte.c

1406

CSR_READ_2(sc, VTE_MISR);

sys/dev/pci/if_vte.c

1451

mcr = CSR_READ_2(sc, VTE_MCR0);

sys/dev/pci/if_vte.c

1458

mcr = CSR_READ_2(sc, VTE_MCR0);

sys/dev/pci/if_vte.c

1478

mcr = CSR_READ_2(sc, VTE_MCR0);

sys/dev/pci/if_vte.c

1483

mcr = CSR_READ_2(sc, VTE_MCR0);

sys/dev/pci/if_vte.c

1598

mcr = CSR_READ_2(sc, VTE_MCR0);

sys/dev/pci/if_vte.c

1672

CSR_READ_2(sc, VTE_MCR0);

sys/dev/pci/if_vte.c

347

if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0)

sys/dev/pci/if_vte.c

356

*val = CSR_READ_2(sc, VTE_MMRD);

sys/dev/pci/if_vte.c

371

if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0)

sys/dev/pci/if_vte.c

444

mid = CSR_READ_2(sc, VTE_MID0L);

sys/dev/pci/if_vte.c

447

mid = CSR_READ_2(sc, VTE_MID0M);

sys/dev/pci/if_vte.c

450

mid = CSR_READ_2(sc, VTE_MID0H);

sys/dev/pci/if_vte.c

873

mcr = CSR_READ_2(sc, VTE_MCR0);

sys/dev/pci/if_vte.c

898

CSR_READ_2(sc, VTE_CNT_RX_DONE);

sys/dev/pci/if_vte.c

899

CSR_READ_2(sc, VTE_CNT_MECNT0);

sys/dev/pci/if_vte.c

900

CSR_READ_2(sc, VTE_CNT_MECNT1);

sys/dev/pci/if_vte.c

901

CSR_READ_2(sc, VTE_CNT_MECNT2);

sys/dev/pci/if_vte.c

902

CSR_READ_2(sc, VTE_CNT_MECNT3);

sys/dev/pci/if_vte.c

903

CSR_READ_2(sc, VTE_CNT_TX_DONE);

sys/dev/pci/if_vte.c

904

CSR_READ_2(sc, VTE_CNT_MECNT4);

sys/dev/pci/if_vte.c

905

CSR_READ_2(sc, VTE_CNT_PAUSE);

sys/dev/pci/if_vte.c

919

CSR_READ_2(sc, VTE_MECISR);

sys/dev/pci/if_vte.c

922

stat->rx_frames += CSR_READ_2(sc, VTE_CNT_RX_DONE);

sys/dev/pci/if_vte.c

924

value = CSR_READ_2(sc, VTE_CNT_MECNT0);

sys/dev/pci/if_vte.c

928

value = CSR_READ_2(sc, VTE_CNT_MECNT1);

sys/dev/pci/if_vte.c

933

value = CSR_READ_2(sc, VTE_CNT_MECNT2);

sys/dev/pci/if_vte.c

937

value = CSR_READ_2(sc, VTE_CNT_MECNT3);

sys/dev/pci/if_vte.c

944

CSR_READ_2(sc, VTE_CNT_TX_DONE)); /* tx_frames */

sys/dev/pci/if_vte.c

946

value = CSR_READ_2(sc, VTE_CNT_MECNT4);

sys/dev/pci/if_vte.c

952

value = CSR_READ_2(sc, VTE_CNT_PAUSE);

sys/dev/pci/if_vte.c

968

status = CSR_READ_2(sc, VTE_MISR);

sys/dev/pci/if_vte.c

989

status = CSR_READ_2(sc, VTE_MISR);

sys/dev/pci/if_wi_pci.c

170

if (!(CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY))

sys/dev/pcmcia/if_wi_pcmcia.c

363

CSR_READ_2(sc, WI_COR) == WI_COR_IOMODE)

sys/dev/pcmcia/if_wi_pcmcia.c

446

if (CSR_READ_2(sc, WI_CNTL) == WI_CNTL_AUX_ENA_STAT)

sys/dev/pcmcia/if_wi_pcmcia.c

461

if (CSR_READ_2(sc, WI_EVENT_STAT) & WI_EV_CMD)

sys/dev/pcmcia/if_wi_pcmcia.c

547

hcr = CSR_READ_2(sc, WI_HCR);