CRU_WRITE
CRU_WRITE(sc, CLKSEL_CON(49), write_mask | write_val);
CRU_WRITE(sc, CLKSEL_CON(50), write_mask | write_val);
CRU_WRITE(sc, pll->con_base + PLL_CON3, val);
CRU_WRITE(sc, pll->con_base + PLL_CON0,
CRU_WRITE(sc, pll->con_base + PLL_CON1,
CRU_WRITE(sc, pll->con_base + PLL_CON2, val);
CRU_WRITE(sc, pll->con_base + PLL_CON3, val);
CRU_WRITE(sc, pll->con_base + PLL_CON3, val);
CRU_WRITE(sc, pll->con_base + PLL_CON3, val);
CRU_WRITE(sc, pll->con_base + PLL_CON0,
CRU_WRITE(sc, pll->con_base + PLL_CON1,
CRU_WRITE(sc, pll->con_base + PLL_CON2, val);
CRU_WRITE(sc, pll->con_base + PLL_CON3, val);
CRU_WRITE(sc, pll->mode_reg, write_mask | write_val);
CRU_WRITE(sc, pll->con_base + PLL_CON3, val);
CRU_WRITE(sc, reg, (1 << (shift + 16)) | (1 << shift));
CRU_WRITE(sc, reg, (1 << (shift + 16)) | (0 << shift));
CRU_WRITE(sc, arm->divs[i].reg, write_mask | write_val);
CRU_WRITE(sc, cpu_rate->divs[i].reg, write_mask | write_val);
CRU_WRITE(sc, arm->divs[i].reg, write_mask | write_val);
CRU_WRITE(sc, arm->mux_reg, write_mask | write_val);
CRU_WRITE(sc, composite->frac_reg, (den << 16) | num);
CRU_WRITE(sc, composite->muxdiv_reg, write_mask | write_val);
CRU_WRITE(sc, composite->muxdiv_reg, write_mask | write_val);
CRU_WRITE(sc, composite->gate_reg, write_mask | write_val);
CRU_WRITE(sc, gate->reg, write_mask | write_val);
CRU_WRITE(sc, mux->reg, write_mask | write_val);
CRU_WRITE(sc, pll->mode_reg,
CRU_WRITE(sc, pll->con_base + PLL_CON1,
CRU_WRITE(sc, pll->con_base + PLL_CON0,
CRU_WRITE(sc, pll->con_base + PLL_CON1,
CRU_WRITE(sc, pll->con_base + PLL_CON2,
CRU_WRITE(sc, pll->con_base + PLL_CON1,
CRU_WRITE(sc, pll->mode_reg,
CRU_WRITE(sc, pll->con_base + PLL_CON0,
CRU_WRITE(sc, pll->con_base + PLL_CON1,
CRU_WRITE(sc, pll->con_base + PLL_CON2, val);
CRU_WRITE(sc, pll->mode_reg, write_mask | write_val);