icr
ciaa.icr = 0x7f; /* and keyboard */
ciab.icr = 0x7f; /* and again */
ciaa.icr = 0x7f; /* and keyboard */
ciab.icr = 0x7f; /* and again */
dispatch_cia_ints (0, ciaa.icr);
dispatch_cia_ints (1, ciab.icr);
volatile unsigned char icr; char padd[0xff];
clockcia->icr = 1 << 0; /* disable timer A interrupt */
interval = clockcia->icr; /* and make sure it's clear */
clockcia->icr = (1<<7) | (1<<0);
clockcia->icr = (1<<7) | (1<<1);
ciab.icr = CIA_ICR_IR_SC | CIA_ICR_FLG;
ciab.icr = CIA_ICR_FLG;
ciab.icr = CIA_ICR_FLG;
ciaa.icr = CIA_ICR_SP; /* CIA SP interrupt disable */
ciaa.icr = CIA_ICR_IR_SC | CIA_ICR_SP;
ciaa.icr = CIA_ICR_IR_SC | CIA_ICR_SP; /* SP interrupt enable */
for (ints = 0; ! ((mask = ciaa.icr) & CIA_ICR_SP);
ciaa.icr = CIA_ICR_IR_SC | CIA_ICR_FLG;
ciaa.icr = CIA_ICR_FLG;
uint32_t icr = SPI_ICR_CCI;
icr |= SPI_ICR_CRFOI;
icr |= SPI_ICR_CRFUI;
icr |= SPI_ICR_CTFOI;
SPIREG_WRITE(sc, SPI_ICR, icr);
uint32_t icr;
icr = sun8i_crypto_read(sc, SUN8I_CRYPTO_ICR);
icr &= ~__SHIFTIN(SUN8I_CRYPTO_ICR_INTR_EN_CHAN(i),
sun8i_crypto_write(sc, SUN8I_CRYPTO_ICR, icr);
uint32_t icr;
icr = sun8i_crypto_read(sc, SUN8I_CRYPTO_ICR);
icr |= __SHIFTIN(SUN8I_CRYPTO_ICR_INTR_EN_CHAN(i),
sun8i_crypto_write(sc, SUN8I_CRYPTO_ICR, icr);
r->icr = 0;
uint32_t icr; /* 0x024 rw intr control reg */
pcireg_t bhlc, icr, lattimer;
icr = cardbus_conf_read(cc, cf, tag, PCI_INTERRUPT_REG);
device_xname(sc->sc_dev), function, icr, bhlc));
MIN(sc->sc_max_lattimer, MAX(0x10, 8 * PCI_MIN_GNT(icr)));
uint16_t icr;
icr = SUNSCPAL_READ_2(sc, sunscpal_icr);
icr |= SUNSCPAL_ICR_DMA_ENABLE |
SUNSCPAL_WRITE_2(sc, sunscpal_icr, icr);
uint16_t icr;
icr = SUNSCPAL_READ_2(sc, sunscpal_icr);
icr &= ~(SUNSCPAL_ICR_DMA_ENABLE | SUNSCPAL_ICR_WORD_MODE |
SUNSCPAL_WRITE_2(sc, sunscpal_icr, icr);
if (icr & (SUNSCPAL_ICR_BUS_ERROR)) {
snprintb(buffer, sizeof(buffer), SUNSCPAL_ICR_BITS, icr);
((icr & SUNSCPAL_ICR_ODD_LENGTH) != 0)) {
#define SUNSCPAL_BUS_PHASE(icr) ((icr) & SUNSCPAL_ICR_PHASE_MASK)
pcireg_t bhlc, csr, icr, lattimer;
icr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_INTERRUPT_REG);
lattimer = MAX(0x10, MIN(0xf8, 8 * PCI_MIN_GNT(icr)));
uint32_t icr;
icr = CSR_READ(sc, DGE_ICR);
if ((icr & sc->sc_icr) == 0)
rnd_add_uint32(&sc->rnd_source, icr);
if (icr & (ICR_RXDMT0 | ICR_RXT0)) {
icr & (ICR_RXDMT0 | ICR_RXT0)));
if (icr & ICR_TXDW) {
if (icr & ICR_TXQE)
if (icr & (ICR_LSC | ICR_RXSEQ)) {
dge_linkintr(sc, icr);
if (icr & ICR_RXO) {
dge_linkintr(struct dge_softc *sc, uint32_t icr)
if (icr & ICR_LSC) {
} else if (icr & ICR_RXSEQ) {
uint32_t icr;
icr = iavf_rd(sc, I40E_VFINT_ICR01);
if (icr == IAVF_REG_VFR) {
if (ISSET(icr, I40E_VFINT_ICR01_ADMINQ_MASK)) {
if (ISSET(icr, I40E_VFINT_ICR01_QUEUE_0_MASK)) {
uint32_t icr, rxintr, txintr;
icr = ixl_rd(sc, I40E_PFINT_ICR0);
if (ISSET(icr, I40E_PFINT_ICR0_ADMINQ_MASK)) {
if (ISSET(icr, I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK)) {
rxintr = icr & I40E_INTR_NOTX_RX_MASK;
txintr = icr & I40E_INTR_NOTX_TX_MASK;
uint32_t icr, mask, reg;
icr = ixl_rd(sc, I40E_PFINT_ICR0);
if (ISSET(icr, I40E_PFINT_ICR0_ADMINQ_MASK)) {
if (ISSET(icr, I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK)) {
if (ISSET(icr, I40E_PFINT_ICR0_GRST_MASK)) {
if (ISSET(icr, I40E_PFINT_ICR0_ECC_ERR_MASK))
if (ISSET(icr, I40E_PFINT_ICR0_PCI_EXCEPTION_MASK))
if (ISSET(icr, I40E_PFINT_ICR0_PE_CRITERR_MASK))
if (ISSET(icr, IXL_ICR0_CRIT_ERR_MASK)) {
if (ISSET(icr, I40E_PFINT_ICR0_HMC_ERR_MASK)) {
wm_linkintr_gmii(struct wm_softc *sc, uint32_t icr)
if ((icr & ICR_LSC) == 0) {
if (icr & ICR_RXSEQ)
wm_linkintr_tbi(struct wm_softc *sc, uint32_t icr)
if (icr & ICR_LSC) {
} else if (icr & ICR_RXSEQ)
wm_linkintr_serdes(struct wm_softc *sc, uint32_t icr)
if (icr & ICR_LSC) {
wm_linkintr(struct wm_softc *sc, uint32_t icr)
wm_linkintr_gmii(sc, icr);
wm_linkintr_serdes(sc, icr);
wm_linkintr_tbi(sc, icr);
uint32_t icr, rndval = 0;
icr = CSR_READ(sc, WMREG_ICR);
if ((icr & sc->sc_icr) == 0)
rndval = icr;
if (icr & ICR_TXDW) {
if (icr & (ICR_RXDMT0 | ICR_RXT0)) {
icr & (ICR_RXDMT0 | ICR_RXT0)));
if (icr & (ICR_LSC | ICR_RXSEQ)) {
wm_linkintr(sc, icr);
if ((icr & ICR_GPI(0)) != 0)
if (icr & ICR_RXO) {
pcireg_t classreg, cmd, icr, bhlc, bar, mask, bar64, mask64,
icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG);
pd->ipin = PCI_INTERRUPT_PIN(icr);
pd->iline = PCI_INTERRUPT_LINE(icr);
pd->min_gnt = PCI_MIN_GNT(icr);
pd->max_lat = PCI_MAX_LAT(icr);
icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT);
pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr);
#define PCI_MAX_LAT(icr) \
(((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK)
#define PCI_MIN_GNT(icr) \
(((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK)
#define PCI_INTERRUPT_GRANT(icr) \
(((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK)
#define PCI_INTERRUPT_LATENCY(icr) \
(((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK)
#define PCI_INTERRUPT_PIN(icr) \
(((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK)
#define PCI_INTERRUPT_LINE(icr) \
(((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK)