CLK_SET_RATE_PARENT
if (clkp->flags & CLK_SET_RATE_PARENT) {
if (clkp->flags & CLK_SET_RATE_PARENT) {
.base.flags = CLK_SET_RATE_PARENT, \
.base.flags = CLK_SET_RATE_PARENT, \
KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0);
.base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \
KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0);
.base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \
.base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \
.base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \
.base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \
.base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \
if (clkp->flags & CLK_SET_RATE_PARENT) {
if (clkp->flags & CLK_SET_RATE_PARENT) {
.base.flags = CLK_SET_RATE_PARENT, \
.base.flags = CLK_SET_RATE_PARENT, \
if (clkp->flags & CLK_SET_RATE_PARENT) {
if (clkp->flags & CLK_SET_RATE_PARENT) {
.base.flags = CLK_SET_RATE_PARENT, \
.base.flags = CLK_SET_RATE_PARENT, \
CLK_SET_RATE_PARENT),
CLK_SET_RATE_PARENT),
CLK_SET_RATE_PARENT),
__BIT(0), CLK_SET_RATE_PARENT),
__BIT(4), CLK_SET_RATE_PARENT),
__BIT(8), CLK_SET_RATE_PARENT),
__BIT(7), CLK_SET_RATE_PARENT),
__BIT(8), CLK_SET_RATE_PARENT),
__BIT(9), CLK_SET_RATE_PARENT),
__BIT(10), CLK_SET_RATE_PARENT),
__BIT(11), CLK_SET_RATE_PARENT),
__BIT(0), CLK_SET_RATE_PARENT),
__BIT(4), CLK_SET_RATE_PARENT),
__BIT(8), CLK_SET_RATE_PARENT),
__BIT(12), CLK_SET_RATE_PARENT),
KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0);
CLK_SET_RATE_PARENT, mout_epll_p),
CLK_SET_RATE_PARENT, mout_rpll_p),
__BIT(9), CLK_SET_RATE_PARENT),
__BIT(10), CLK_SET_RATE_PARENT),
__BIT(0), CLK_SET_RATE_PARENT),
__BIT(1), CLK_SET_RATE_PARENT),
__BIT(2), CLK_SET_RATE_PARENT),
__BIT(7), CLK_SET_RATE_PARENT),
__BIT(8), CLK_SET_RATE_PARENT),
__BIT(9), CLK_SET_RATE_PARENT),
__BIT(10), CLK_SET_RATE_PARENT),
__BIT(0), CLK_SET_RATE_PARENT),
__BIT(1), CLK_SET_RATE_PARENT),
__BIT(2), CLK_SET_RATE_PARENT),
__BIT(3), CLK_SET_RATE_PARENT),
__BIT(12), CLK_SET_RATE_PARENT),
__BIT(13), CLK_SET_RATE_PARENT),
__BIT(14), CLK_SET_RATE_PARENT),
__BIT(18), CLK_SET_RATE_PARENT),
__BIT(19), CLK_SET_RATE_PARENT),
__BIT(20), CLK_SET_RATE_PARENT),
__BIT(0), CLK_SET_RATE_PARENT),
__BIT(1), CLK_SET_RATE_PARENT),
__BIT(2), CLK_SET_RATE_PARENT),
__BIT(3), CLK_SET_RATE_PARENT),
__BIT(6), CLK_SET_RATE_PARENT),
__BIT(7), CLK_SET_RATE_PARENT),
__BIT(8), CLK_SET_RATE_PARENT),
__BIT(9), CLK_SET_RATE_PARENT),
__BIT(14), CLK_SET_RATE_PARENT),
__BIT(24), CLK_SET_RATE_PARENT),
KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0);
if (clkp->flags & CLK_SET_RATE_PARENT) {
if (clkp->flags & CLK_SET_RATE_PARENT) {
.base.flags = CLK_SET_RATE_PARENT, \
.base.flags = CLK_SET_RATE_PARENT, \
if (clkp->flags & CLK_SET_RATE_PARENT) {
JH71X0CLKC_MUX_FLAGS(JH7100_CLK_GMAC_TX, "gmac_tx", gmac_tx_parents, CLK_SET_RATE_PARENT),
JH71X0CLKC_MUXGATE_FLAGS(JH7110_SYSCLK_GMAC1_TX, "gmac1_tx", gmac1_tx_parents, CLK_SET_RATE_PARENT), // CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
JH71X0CLKC_MUX_FLAGS(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", gmac0_rx_parents, CLK_SET_RATE_PARENT), // CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
if (clk->flags & CLK_SET_RATE_PARENT) {
.flags = CLK_SET_RATE_PARENT, \
.flags = CLK_SET_RATE_PARENT, \
if (clk->flags & CLK_SET_RATE_PARENT)