etsec_write
etsec_write(sc, TSTAT, TSTAT_THLT | TSTAT_TXF);
etsec_write(sc, RSTAT, RSTAT_QHLT | RSTAT_RXF);
etsec_write(sc, DMACTRL, sc->sc_dmactrl);
etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN);
etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN);
etsec_write(sc, IMASK, sc->sc_imask);
etsec_write(sc, IMASK, sc->sc_imask & ~imask_gsc_mask);
etsec_write(sc, IEVENT, imask_gsc_mask);
etsec_write(sc, DMACTRL, sc->sc_dmactrl);
etsec_write(sc, IMASK, sc->sc_imask | imask_gsc_mask);
etsec_write(sc, MACCFG1, MACCFG1_SOFT_RESET);
etsec_write(sc, MACCFG1, 0);
etsec_write(sc, IMASK, 0);
etsec_write(sc, IEVENT, ~0);
etsec_write(sc, TBIPA, 0x1f);
etsec_write(sc, MIIMCFG, MIIMCFG_RESET);
etsec_write(sc, MIIMCFG, miimcfg);
etsec_write(sc, IGADDR(i), sc->sc_gaddr[i]);
etsec_write(sc, GADDR(i), sc->sc_gaddr[i+8]);
etsec_write(sc, MACnADDR1(i), (uint32_t)(macaddr >> 32));
etsec_write(sc, MACnADDR2(i), (uint32_t)(macaddr >> 0));
etsec_write(sc, RSTAT, RSTAT_QHLT & rxq->rxq_qmask);
etsec_write(sc, RSTAT, RSTAT_RXF & rxq->rxq_qmask);
etsec_write(sc, rxq->rxq_reg_rbase, rxq->rxq_descmap->dm_segs->ds_addr);
etsec_write(sc, TSTAT, txq->txq_qmask & TSTAT_THLT); /* W1C */
etsec_write(sc, TSTAT, TSTAT_TXF & txq->txq_qmask);
etsec_write(sc, txq->txq_reg_tbase, txq->txq_descmap->dm_segs->ds_addr);
etsec_write(sc, TSTAT, TSTAT_THLT & txq->txq_qmask);
etsec_write(sc, IEVENT, ievent); /* write 1 to clear */
etsec_write(sc, IMASK, sc->sc_imask);
etsec_write(sc, IEVENT, ievent); /* write 1 to clear */
etsec_write(sc, IMASK, sc->sc_imask);
etsec_write(sc, IEVENT, ievent); /* write 1 to clear */
etsec_write(sc, IMASK, sc->sc_imask);
etsec_write(sc, IMASK, sc->sc_imask);
etsec_write(sc, IMASK, sc->sc_imask);
etsec_write(sc, IMASK, sc->sc_imask);
etsec_write(sc, IMASK, sc->sc_imask);
etsec_write(sc, RXIC, reg);
etsec_write(sc, TXIC, reg);
etsec_write(sc, IMASK, 0);
etsec_write(sc, ATTR, ATTR_DEFAULT);
etsec_write(sc, ATTRELI, ATTRELI_DEFAULT);
etsec_write(sc, MAXFRM, sc->sc_maxfrm);
etsec_write(sc, MACSTNADDR1, (uint32_t)(macstnaddr >> 32));
etsec_write(sc, MACSTNADDR2, (uint32_t)(macstnaddr >> 0));
etsec_write(sc, MACCFG1, sc->sc_maccfg1);
etsec_write(sc, MACCFG2, sc->sc_maccfg2);
etsec_write(sc, ECNTRL, sc->sc_ecntrl);
etsec_write(sc, MRBLR, MCLBYTES);
etsec_write(sc, DMACTRL, sc->sc_dmactrl);
etsec_write(sc, TQUEUE, TQUEUE_EN0);
etsec_write(sc, TCTRL, sc->sc_tctrl); /* for TOE stuff */
etsec_write(sc, RQUEUE, RQUEUE_EN0 | RQUEUE_EX0);
etsec_write(sc, RCTRL, sc->sc_rctrl);