sys/arch/arm/nvidia/tegra_cec.c

193

CEC_WRITE(sc, CEC_SW_CONTROL_REG, 0);

sys/arch/arm/nvidia/tegra_cec.c

194

CEC_WRITE(sc, CEC_INPUT_FILTER_REG, 0);

sys/arch/arm/nvidia/tegra_cec.c

195

CEC_WRITE(sc, CEC_HW_CONTROL_REG, 0);

sys/arch/arm/nvidia/tegra_cec.c

196

CEC_WRITE(sc, CEC_INT_MASK_REG, 0);

sys/arch/arm/nvidia/tegra_cec.c

197

CEC_WRITE(sc, CEC_INT_STAT_REG, 0xffffffff);

sys/arch/arm/nvidia/tegra_cec.c

228

CEC_WRITE(sc, CEC_INT_STAT_REG, CEC_INT_RX_REGISTER_FULL);

sys/arch/arm/nvidia/tegra_cec.c

244

CEC_WRITE(sc, CEC_TX_REGISTER_REG, val);

sys/arch/arm/nvidia/tegra_cec.c

245

CEC_WRITE(sc, CEC_INT_STAT_REG,

sys/arch/arm/nvidia/tegra_cec.c

259

CEC_WRITE(sc, CEC_INT_STAT_REG, CEC_INT_TX_FRAME_TRANSMITTED);

sys/arch/arm/nvidia/tegra_cec.c

261

CEC_WRITE(sc, CEC_INT_STAT_REG,

sys/arch/arm/nvidia/tegra_cec.c

290

CEC_WRITE(sc, CEC_HW_CONTROL_REG, 0);

sys/arch/arm/nvidia/tegra_cec.c

291

CEC_WRITE(sc, CEC_INT_STAT_REG, 0xffffffff);

sys/arch/arm/nvidia/tegra_cec.c

292

CEC_WRITE(sc, CEC_HW_CONTROL_REG, val);

sys/arch/arm/nvidia/tegra_cec.c

303

CEC_WRITE(sc, CEC_INT_MASK_REG, CEC_INT_RX_REGISTER_FULL);

sys/arch/arm/nvidia/tegra_cec.c

304

CEC_WRITE(sc, CEC_HW_CONTROL_REG, CEC_HW_CONTROL_TX_RX_MODE);

sys/arch/arm/nvidia/tegra_cec.c

316

CEC_WRITE(sc, CEC_HW_CONTROL_REG, 0);

sys/arch/arm/nvidia/tegra_cec.c

317

CEC_WRITE(sc, CEC_INT_MASK_REG, 0);

sys/arch/arm/nvidia/tegra_cec.c

318

CEC_WRITE(sc, CEC_INT_STAT_REG, 0xffffffff);