sys/arch/arm/nvidia/tegra_cec.c

195

CEC_WRITE(sc, CEC_HW_CONTROL_REG, 0);

sys/arch/arm/nvidia/tegra_cec.c

289

val = CEC_READ(sc, CEC_HW_CONTROL_REG);

sys/arch/arm/nvidia/tegra_cec.c

290

CEC_WRITE(sc, CEC_HW_CONTROL_REG, 0);

sys/arch/arm/nvidia/tegra_cec.c

292

CEC_WRITE(sc, CEC_HW_CONTROL_REG, val);

sys/arch/arm/nvidia/tegra_cec.c

304

CEC_WRITE(sc, CEC_HW_CONTROL_REG, CEC_HW_CONTROL_TX_RX_MODE);

sys/arch/arm/nvidia/tegra_cec.c

316

CEC_WRITE(sc, CEC_HW_CONTROL_REG, 0);

sys/arch/arm/nvidia/tegra_cec.c

350

val = CEC_READ(sc, CEC_HW_CONTROL_REG);

sys/arch/arm/nvidia/tegra_cec.c

356

CEC_SET_CLEAR(sc, CEC_HW_CONTROL_REG,