CCU_READ
val = CCU_READ(sc, CPUX_AXI_CFG_REG);
val = CCU_READ(sc, nkmp->reg);
while ((CCU_READ(sc, PLL_STABLE_STATUS_REG) & nkmp->lock) == 0)
val = CCU_READ(sc, CPUX_AXI_CFG_REG);
val = CCU_READ(sc, SDMMC2_CLK_REG);
val = CCU_READ(sc, AHB2_CFG_REG);
val = CCU_READ(sc, AHB2_CFG_REG);
val = CCU_READ(sc, CPU_CLK_SRC_REG);
val = CCU_READ(sc, nkmp->reg);
while ((CCU_READ(sc, PLL_STABLE_STATUS_REG) & nkmp->lock) == 0)
val = CCU_READ(sc, CPU_CLK_SRC_REG);
const uint32_t val = CCU_READ(sc, reset->reg);
const uint32_t val = CCU_READ(sc, reset->reg);
val = CCU_READ(sc, div->reg);
val = CCU_READ(sc, div->reg);
val = CCU_READ(sc, div->reg);
val = CCU_READ(sc, div->reg);
val = CCU_READ(sc, div->reg);
val = CCU_READ(sc, fractional->reg);
val = CCU_READ(sc, fractional->reg);
val = CCU_READ(sc, fractional->reg);
val = CCU_READ(sc, fractional->reg);
val = CCU_READ(sc, fractional->reg);
val = CCU_READ(sc, gate->reg);
val = CCU_READ(sc, mux->reg);
val = CCU_READ(sc, mux->reg);
val = CCU_READ(sc, nkmp->reg);
val = CCU_READ(sc, nkmp->reg);
val = CCU_READ(sc, nkmp->reg);
val = CCU_READ(sc, nkmp->reg);
val = CCU_READ(sc, nm->reg);
val = CCU_READ(sc, nm->reg);
val = CCU_READ(sc, nm->reg);
val = CCU_READ(sc, nm->reg);
val = CCU_READ(sc, nm->reg);
val = CCU_READ(sc, nm->reg);
val = CCU_READ(sc, phase->reg);
val = CCU_READ(sc, phase->reg);
val = CCU_READ(sc, prediv->reg);
val = CCU_READ(sc, prediv->reg);
val = CCU_READ(sc, prediv->reg);