Symbol: _reg_write_2
sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c
107
_reg_write_2(SH4_GPIOIC, reg);
sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c
129
_reg_write_2(SH4_GPIOIC, reg);
sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c
158
_reg_write_2(SH4_GPIOIC, r);
sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c
63
_reg_write_2(SH4_GPIOIC, 0);
sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c
64
_reg_write_2(SH4_PDTRA, 0);
sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c
66
_reg_write_2(SH4_PDTRB, 0);
sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c
73
_reg_write_2(SH4_PDTRA, (1 << GPIO_PIN_CARD_PON)
sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c
125
_reg_write_2(SH4_PDTRA, reg);
sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c
140
_reg_write_2(SH4_PDTRA, reg);
sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c
182
_reg_write_2(SH4_PDTRA, reg);
sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c
815
_reg_write_2(SH4_PDTRA, reg);
sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c
824
_reg_write_2(SH4_PDTRA, reg);
sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c
829
_reg_write_2(SH4_PDTRA, reg);
sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c
844
_reg_write_2(SH4_PDTRA, reg);
sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c
849
_reg_write_2(SH4_PDTRA, reg);
sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c
854
_reg_write_2(SH4_PDTRA, reg);
sys/arch/evbsh3/evbsh3/machdep.c
366
_reg_write_2(SH3_BCR1, BSC_BCR1_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
378
_reg_write_2(SH_(BCR2), BSC_BCR2_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
386
_reg_write_2(SH3_WCR1, BSC_WCR1_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
401
_reg_write_2(SH3_WCR2, BSC_WCR2_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
418
_reg_write_2(SH3_MCR, BSC_MCR_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
431
_reg_write_2(0x1a000000, 0); /* ADDSET */
sys/arch/evbsh3/evbsh3/machdep.c
433
_reg_write_2(0x18000000, 0); /* ADDRST */
sys/arch/evbsh3/evbsh3/machdep.c
443
_reg_write_2(SH_(PCR), BSC_PCR_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
453
_reg_write_2(SH_(RTCSR), BSC_RTCSR_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
460
_reg_write_2(SH_(RTCNT), BSC_RTCNT_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
464
_reg_write_2(SH_(RTCOR), BSC_RTCOR_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
468
_reg_write_2(SH_(RFCR), BSC_RFCR_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
475
_reg_write_2(SH_(FRQCR), FRQCR_VAL);
sys/arch/evbsh3/t_sh7706lan/scimci.c
118
_reg_write_2((reg), _r); \
sys/arch/evbsh3/t_sh7706lan/scimci.c
134
_reg_write_2((reg), _r); \
sys/arch/evbsh3/t_sh7706lan/ssumci.c
120
_reg_write_2((reg), _r); \
sys/arch/evbsh3/t_sh7706lan/ssumci.c
136
_reg_write_2((reg), _r); \
sys/arch/evbsh3/t_sh7706lan/t_sh7706lan.c
47
_reg_write_2(SH7709_PHCR, 0x2800);
sys/arch/evbsh3/t_sh7706lan/t_sh7706lan.c
52
_reg_write_2(SH7709_SCPCR, reg);
sys/arch/evbsh3/t_sh7706lan/t_sh7706lan.c
55
_reg_write_2(SH7709_ICR1, 0x0aaa);
sys/arch/evbsh3/t_sh7706lan/t_sh7706lan.c
61
_reg_write_2(SH3_BCR2, reg);
sys/arch/hpc/stand/hpcboot/sh3/dev/sh4_dev.cpp
113
_reg_write_2(SH4_IPRA, 0);
sys/arch/hpc/stand/hpcboot/sh3/dev/sh4_dev.cpp
114
_reg_write_2(SH4_IPRB, 0);
sys/arch/hpc/stand/hpcboot/sh3/dev/sh4_dev.cpp
115
_reg_write_2(SH4_IPRC, 0);
sys/arch/hpc/stand/hpcboot/sh3/dev/sh4_dev.cpp
170
_reg_write_2(a, ~_reg_read_2(a) & 0xffff);
sys/arch/hpcsh/dev/hd64461/hd64461pcmcia.c
1102
_reg_write_2(SH3_BCR2, bcr2);
sys/arch/hpcsh/dev/hd64465/hd64465pcmcia.c
789
_reg_write_2(SH4_BCR2, r16);
sys/arch/hpcsh/dev/pfckbd.c
310
_reg_write_2(SH7709_PDCR, dc | scan[column].dc);
sys/arch/hpcsh/dev/pfckbd.c
311
_reg_write_2(SH7709_PECR, ec | scan[column].ec);
sys/arch/hpcsh/dev/pfckbd.c
331
_reg_write_2(SH7709_PDCR, dc | (0x5555 & PFCKBD_HP_PDCR_MASK));
sys/arch/hpcsh/dev/pfckbd.c
332
_reg_write_2(SH7709_PECR, ec | (0x5555 & PFCKBD_HP_PECR_MASK));
sys/arch/hpcsh/dev/pfckbd.c
408
_reg_write_2(SH7709_PCCR, cc | scan[i].cc);
sys/arch/hpcsh/dev/pfckbd.c
409
_reg_write_2(SH7709_PDCR, dc | scan[i].dc);
sys/arch/hpcsh/dev/pfckbd.c
410
_reg_write_2(SH7709_PECR, ec | scan[i].ec);
sys/arch/hpcsh/dev/pfckbd.c
433
_reg_write_2(SH7709_PCCR, cc | (0x5555 & PFCKBD_HITACHI_PCCR_MASK));
sys/arch/hpcsh/dev/pfckbd.c
434
_reg_write_2(SH7709_PDCR, dc | (0x5555 & PFCKBD_HITACHI_PDCR_MASK));
sys/arch/hpcsh/dev/pfckbd.c
435
_reg_write_2(SH7709_PECR, ec | (0x5555 & PFCKBD_HITACHI_PECR_MASK));
sys/arch/hpcsh/dev/pfckbd.c
458
_reg_write_2(SH7709_PCCR, cc | poll.cc);
sys/arch/hpcsh/dev/pfckbd.c
459
_reg_write_2(SH7709_PDCR, dc | poll.dc);
sys/arch/hpcsh/dev/pfckbd.c
460
_reg_write_2(SH7709_PECR, ec | poll.ec);
sys/arch/hpcsh/dev/pfckbd.c
477
_reg_write_2(SH7709_PCCR, cc | (0x5555 & PFCKBD_HITACHI_PCCR_MASK));
sys/arch/hpcsh/dev/pfckbd.c
478
_reg_write_2(SH7709_PDCR, dc | (0x5555 & PFCKBD_HITACHI_PDCR_MASK));
sys/arch/hpcsh/dev/pfckbd.c
479
_reg_write_2(SH7709_PECR, ec | (0x5555 & PFCKBD_HITACHI_PECR_MASK));
sys/arch/hpcsh/hpcsh/machdep.c
626
_reg_write_2(HD6446X_NIRR, 0x0000);
sys/arch/landisk/landisk/machdep.c
404
_reg_write_2(SH4_BCR2, BSC_BCR2_VAL);
sys/arch/landisk/landisk/machdep.c
409
_reg_write_2(SH4_BCR3, BSC_BCR3_VAL);
sys/arch/landisk/landisk/machdep.c
462
_reg_write_2(SH4_PCR, BSC_PCR_VAL);
sys/arch/landisk/landisk/machdep.c
472
_reg_write_2(SH4_RTCSR, BSC_RTCSR_VAL);
sys/arch/landisk/landisk/machdep.c
479
_reg_write_2(SH4_RTCNT, BSC_RTCNT_VAL);
sys/arch/landisk/landisk/machdep.c
483
_reg_write_2(SH4_RTCOR, BSC_RTCOR_VAL);
sys/arch/landisk/landisk/machdep.c
487
_reg_write_2(SH4_RFCR, BSC_RFCR_VAL);
sys/arch/landisk/landisk/machdep.c
494
_reg_write_2(SH4_FRQCR, FRQCR_VAL);
sys/arch/landisk/stand/boot/delay.c
99
_reg_write_2(TCR, TCR_TPSC);
sys/arch/mmeye/mmeye/machdep.c
369
_reg_write_2(SH3_BCR1, 0x1010);
sys/arch/mmeye/mmeye/machdep.c
378
_reg_write_2(SH3_BCR1, 0x1013);
sys/arch/mmeye/mmeye/machdep.c
390
_reg_write_2(SH3_BCR2, 0x2af4);
sys/arch/mmeye/mmeye/machdep.c
399
_reg_write_2(SH3_BCR2, 0x16f4);
sys/arch/mmeye/mmeye/machdep.c
406
_reg_write_2(SH3_WCR1, 0x3fff);
sys/arch/mmeye/mmeye/machdep.c
417
_reg_write_2(SH3_WCR2, 0x4bdd);
sys/arch/mmeye/mmeye/machdep.c
428
_reg_write_2(SH3_WCR2, 0xabfd);
sys/arch/mmeye/mmeye/machdep.c
438
_reg_write_2(SH3_MCR, 0x6135);
sys/arch/mmeye/mmeye/machdep.c
442
_reg_write_2(SH3_DCR, 0x0000);
sys/arch/mmeye/mmeye/machdep.c
449
_reg_write_2(SH3_PCR, 0x00ff);
sys/arch/mmeye/mmeye/machdep.c
457
_reg_write_2(SH4_BCR2, 0x6af9);
sys/arch/mmeye/mmeye/machdep.c
462
_reg_write_2(SH4_PCR, 0x4b2d);
sys/arch/mmeye/mmeye/machdep.c
472
_reg_write_2(SH_(RTCSR), 0xa594);
sys/arch/mmeye/mmeye/machdep.c
478
_reg_write_2(SH_(RTCNT), 0xa500);
sys/arch/mmeye/mmeye/machdep.c
484
_reg_write_2(SH3_RTCOR, 0xa50d);
sys/arch/mmeye/mmeye/machdep.c
486
_reg_write_2(SH4_RTCOR, 0xa575);
sys/arch/mmeye/mmeye/machdep.c
492
_reg_write_2(SH_(RFCR), 0xa400);
sys/arch/mmeye/mmeye/machdep.c
498
_reg_write_2(SH3_FRQCR, 0xa100); /* 100MHz */
sys/arch/mmeye/mmeye/machdep.c
500
_reg_write_2(SH3_FRQCR, 0x0112); /* 60MHz */
sys/arch/mmeye/mmeye/machdep.c
502
_reg_write_2(SH4_FRQCR, 0x0e0a);
sys/arch/mmeye/stand/boot/clock.c
41
_reg_write_2(SH_(TCR0), TCR_TPSC_P4);
sys/arch/playstation2/dev/emac3.c
89
_reg_write_2(a_, (v >> 16) & 0xffff);
sys/arch/playstation2/dev/emac3.c
90
_reg_write_2(a_ + 2, v & 0xffff);
sys/arch/playstation2/dev/if_smap.c
176
_reg_write_2(SPD_INTR_ENABLE_REG16, r);
sys/arch/playstation2/dev/if_smap.c
180
_reg_write_2(SPD_INTR_CLEAR_REG16, SPD_INTR_RXEND | SPD_INTR_TXEND |
sys/arch/playstation2/dev/if_smap.c
280
_reg_write_2(SPD_INTR_ENABLE_REG16, r);
sys/arch/playstation2/dev/if_smap.c
289
_reg_write_2(SPD_INTR_CLEAR_REG16, disable);
sys/arch/playstation2/dev/if_smap.c
293
_reg_write_2(SPD_INTR_CLEAR_REG16, SPD_INTR_TXEND);
sys/arch/playstation2/dev/if_smap.c
300
_reg_write_2(SPD_INTR_CLEAR_REG16, SPD_INTR_RXEND);
sys/arch/playstation2/dev/if_smap.c
352
_reg_write_2(SMAP_RXFIFO_PTR_REG16, d->ptr & 0x3ffc);
sys/arch/playstation2/dev/if_smap.c
400
_reg_write_2(SPD_INTR_ENABLE_REG16, r16);
sys/arch/playstation2/dev/if_smap.c
504
_reg_write_2(SMAP_TXFIFO_PTR_REG16, fifop);
sys/arch/playstation2/dev/if_smap.c
531
_reg_write_2(SPD_INTR_ENABLE_REG16, r16);
sys/arch/playstation2/dev/if_smap.c
565
_reg_write_2(SPD_INTR_CLEAR_REG16, SPD_INTR_RXEND | SPD_INTR_TXEND |
sys/arch/playstation2/dev/if_smap.c
572
_reg_write_2(SPD_INTR_ENABLE_REG16, r16);
sys/arch/playstation2/dev/sbus.c
255
_reg_write_2(SBUS_PCMCIA_CSC1_REG16, 0xffff);
sys/arch/playstation2/dev/sbus.c
262
_reg_write_2(SBUS_PCMCIA_TIMR_REG16, 0);
sys/arch/playstation2/dev/sbus.c
269
_reg_write_2(SBUS_PCMCIA_TIMR_REG16, 1);
sys/arch/playstation2/dev/sbus.c
277
_reg_write_2(SBUS_PCMCIA_TIMR_REG16, 1);
sys/arch/playstation2/dev/sbus.c
278
_reg_write_2(SBUS_PCMCIA_TIMR_REG16, r);
sys/arch/playstation2/dev/sbus.c
292
_reg_write_2(SBUS_PCMCIA3_TIMR_REG16, 0);
sys/arch/playstation2/dev/sbus.c
299
_reg_write_2(SBUS_PCMCIA3_TIMR_REG16, 1);
sys/arch/playstation2/dev/sbus.c
307
_reg_write_2(SBUS_PCMCIA3_TIMR_REG16, 1);
sys/arch/playstation2/dev/sbus.c
308
_reg_write_2(SBUS_PCMCIA3_TIMR_REG16, r);
sys/arch/playstation2/dev/spd.c
107
_reg_write_2(SPD_INTR_ENABLE_REG16, 0);
sys/arch/playstation2/dev/spd.c
108
_reg_write_2(SPD_INTR_CLEAR_REG16, _reg_read_2(SPD_INTR_STATUS_REG16));
sys/arch/playstation2/dev/spd.c
152
_reg_write_2(SPD_INTR_ENABLE_REG16, 0);
sys/arch/playstation2/dev/spd.c
153
_reg_write_2(SPD_INTR_ENABLE_REG16, r);
sys/arch/playstation2/dev/wdc_spd.c
238
_reg_write_2(SPD_INTR_ENABLE_REG16, r);
sys/arch/playstation2/dev/wdc_spd.c
248
_reg_write_2(SPD_INTR_ENABLE_REG16, r);
sys/arch/sh3/dev/rtc.c
233
_reg_write_2(SH4_RYRCNT, year);
sys/arch/sh3/sh3/clock.c
119
_reg_write_2(SH_(TCR0), 0);
sys/arch/sh3/sh3/clock.c
120
_reg_write_2(SH_(TCR1), 0);
sys/arch/sh3/sh3/clock.c
121
_reg_write_2(SH_(TCR2), 0);
sys/arch/sh3/sh3/clock.c
134
_reg_write_2(SH_(TCR0), TCR_TPSC_P16);
sys/arch/sh3/sh3/clock.c
138
_reg_write_2(SH_(TCR0),
sys/arch/sh3/sh3/clock.c
168
_reg_write_2(SH_(TCR1), TCR_TPSC_P4);
sys/arch/sh3/sh3/clock.c
247
_reg_write_2(SH_(TCR0), TCR_UNIE | TCR_TPSC_P16);
sys/arch/sh3/sh3/clock.c
250
_reg_write_2(SH_(TCR0), TCR_UNIE |
sys/arch/sh3/sh3/clock.c
267
_reg_write_2(SH_(TCR1), TCR_UNIE | TCR_TPSC_P4);
sys/arch/sh3/sh3/clock.c
273
_reg_write_2(SH_(TCR2), TCR_TPSC_P4);
sys/arch/sh3/sh3/interrupt.c
100
_reg_write_2(SH4_IPRA, 0);
sys/arch/sh3/sh3/interrupt.c
101
_reg_write_2(SH4_IPRB, 0);
sys/arch/sh3/sh3/interrupt.c
102
_reg_write_2(SH4_IPRC, 0);
sys/arch/sh3/sh3/interrupt.c
356
_reg_write_2(iprreg, r);
sys/arch/sh3/sh3/interrupt.c
77
_reg_write_2(SH7709_IPRC, 0);
sys/arch/sh3/sh3/interrupt.c
78
_reg_write_2(SH7709_IPRD, 0);
sys/arch/sh3/sh3/interrupt.c
79
_reg_write_2(SH7709_IPRE, 0);
sys/arch/sh3/sh3/interrupt.c
84
_reg_write_2(SH3_IPRA, 0);
sys/arch/sh3/sh3/interrupt.c
85
_reg_write_2(SH3_IPRB, 0);
sys/arch/sh3/sh3/interrupt.c
97
_reg_write_2(SH4_IPRD, 0);
sys/arch/sh3/sh3/sh3_machdep.c
195
_reg_write_2(SH_(BBRA), 0); /* disable channel A */
sys/arch/sh3/sh3/sh3_machdep.c
196
_reg_write_2(SH_(BBRB), 0); /* disable channel B */
sys/arch/sh3/sh3/sh3_machdep.c
212
_reg_write_2(SH4_BRCR, UBC_CTL_A_AFTER_INSN);