sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

105

reg = _reg_read_2(SH4_GPIOIC);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

127

reg = _reg_read_2(SH4_GPIOIC);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

156

r = _reg_read_2(SH4_GPIOIC);

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

119

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

134

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

163

bit = (_reg_read_2(SH4_PDTRA) & (1 << GPIO_PIN_RTC_SIO)) ? 1 : 0;

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

177

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

347

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

529

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

560

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

813

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

822

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

827

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

842

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

847

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

852

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/t_sh7706lan/scimci.c

115

_r = _reg_read_2((reg)); \

sys/arch/evbsh3/t_sh7706lan/scimci.c

132

_r = _reg_read_2((reg)); \

sys/arch/evbsh3/t_sh7706lan/ssumci.c

117

_r = _reg_read_2((reg)); \

sys/arch/evbsh3/t_sh7706lan/ssumci.c

134

_r = _reg_read_2((reg)); \

sys/arch/evbsh3/t_sh7706lan/t_sh7706lan.c

50

reg = _reg_read_2(SH7709_SCPCR);

sys/arch/evbsh3/t_sh7706lan/t_sh7706lan.c

58

reg = _reg_read_2(SH3_BCR2);

sys/arch/hpc/stand/hpcboot/sh3/dev/sh.h

337

while ((_reg_read_2(SH3_SCSSR2) & SCSSR2_TDFE) == 0)

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

107

DPRINTF((TEXT("ICR0 0x%08x\n"), _reg_read_2(SH3_ICR0)));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

108

DPRINTF((TEXT("ICR1 0x%08x\n"), _reg_read_2(SH3_ICR1)));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

109

DPRINTF((TEXT("ICR2 0x%08x\n"), _reg_read_2(SH3_ICR2)));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

110

DPRINTF((TEXT("PINTER 0x%08x\n"), _reg_read_2(SH3_PINTER)));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

111

DPRINTF((TEXT("IPRA 0x%08x\n"), _reg_read_2(SH3_IPRA)));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

112

DPRINTF((TEXT("IPRB 0x%08x\n"), _reg_read_2(SH3_IPRB)));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

113

DPRINTF((TEXT("IPRC 0x%08x\n"), _reg_read_2(SH3_IPRC)));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

114

DPRINTF((TEXT("IPRD 0x%08x\n"), _reg_read_2(SH3_IPRD)));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

115

DPRINTF((TEXT("IPRE 0x%08x\n"), _reg_read_2(SH3_IPRE)));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

134

bitdisp(_reg_read_2(SH3_PINTER));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

136

bitdisp(_reg_read_2(SH3_ICR2));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

138

r = _reg_read_2(SH3_ICR0);

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

142

r = _reg_read_2(SH3_ICR1);

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

171

bitdisp(_reg_read_2(SH3_ ## x))

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

194

bitdisp(_reg_read_2(SH3_P##x##CR))

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

208

bitdisp(_reg_read_2(SH3_SCPCR));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

268

r16 = _reg_read_2(tcr);

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

323

r16 = _reg_read_2(HD64461_SYSSTBCR_REG16);

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

344

r16 = _reg_read_2(HD64461_SYSSYSCR_REG16);

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

358

r16 = _reg_read_2(HD64461_SYSSCPUCR_REG16);

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

382

r16 = _reg_read_2(HD64461_INTCNIRR_REG16);

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

397

r16 = _reg_read_2(HD64461_INTCNIMR_REG16);

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

593

bitdisp(_reg_read_2(HD64461_GPA##x##R_REG16)); \

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

594

bitdisp(_reg_read_2(HD64461_GPB##x##R_REG16)); \

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

595

bitdisp(_reg_read_2(HD64461_GPC##x##R_REG16)); \

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

596

bitdisp(_reg_read_2(HD64461_GPD##x##R_REG16))

sys/arch/hpc/stand/hpcboot/sh3/dev/sh4_dev.cpp

105

r = _reg_read_2(SH4_ICR);

sys/arch/hpc/stand/hpcboot/sh3/dev/sh4_dev.cpp

119

DPRINTF((TEXT("%04x ", _reg_read_2(HD64465_NIRR))));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh4_dev.cpp

133

if (_reg_read_2(HD64465_SDIDR) != 0x8122) {

sys/arch/hpc/stand/hpcboot/sh3/dev/sh4_dev.cpp

139

bitdisp(_reg_read_2(HD64465_SMSCR));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh4_dev.cpp

141

bitdisp(_reg_read_2(HD64465_SPCCR));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh4_dev.cpp

144

bitdisp(_reg_read_2(HD64465_NIRR));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh4_dev.cpp

146

bitdisp(_reg_read_2(HD64465_NIMR));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh4_dev.cpp

148

bitdisp(_reg_read_2(HD64465_NITR));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh4_dev.cpp

153

bitdisp(_reg_read_2(HD64465_NIRR));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh4_dev.cpp

170

_reg_write_2(a, ~_reg_read_2(a) & 0xffff);

sys/arch/hpc/stand/hpcboot/sh3/dev/sh_dev.cpp

129

r16 = _reg_read_2(SH3_SCSSR2);

sys/arch/hpc/stand/hpcboot/sh3/dev/sh_dev.cpp

167

(_reg_read_2(tab->reg) >> tab->shift) & SH_IPR_MASK));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh_dev.h

94

return (uint32_t)_reg_read_2(va);

sys/arch/hpcsh/dev/hd64461/hd64461pcmcia.c

1097

bcr2 = _reg_read_2(SH3_BCR2);

sys/arch/hpcsh/dev/hd64465/hd64465.c

191

dbg_bit_print_msg(_reg_read_2(SH4_ICR), "SH4_ICR");

sys/arch/hpcsh/dev/hd64465/hd64465pcmcia.c

778

r16 = _reg_read_2(SH4_BCR2);

sys/arch/hpcsh/dev/pfckbd.c

305

dc = _reg_read_2(SH7709_PDCR) & ~PFCKBD_HP_PDCR_MASK;

sys/arch/hpcsh/dev/pfckbd.c

306

ec = _reg_read_2(SH7709_PECR) & ~PFCKBD_HP_PECR_MASK;

sys/arch/hpcsh/dev/pfckbd.c

402

cc = _reg_read_2(SH7709_PCCR) & ~PFCKBD_HITACHI_PCCR_MASK;

sys/arch/hpcsh/dev/pfckbd.c

403

dc = _reg_read_2(SH7709_PDCR) & ~PFCKBD_HITACHI_PDCR_MASK;

sys/arch/hpcsh/dev/pfckbd.c

404

ec = _reg_read_2(SH7709_PECR) & ~PFCKBD_HITACHI_PECR_MASK;

sys/arch/hpcsh/dev/pfckbd.c

453

cc = _reg_read_2(SH7709_PCCR) & ~PFCKBD_HITACHI_PCCR_MASK;

sys/arch/hpcsh/dev/pfckbd.c

454

dc = _reg_read_2(SH7709_PDCR) & ~PFCKBD_HITACHI_PDCR_MASK;

sys/arch/hpcsh/dev/pfckbd.c

455

ec = _reg_read_2(SH7709_PECR) & ~PFCKBD_HITACHI_PECR_MASK;

sys/arch/hpcsh/hpcsh/machdep.c

606

r = _reg_read_2(HD6446X_NIRR);

sys/arch/playstation2/dev/emac3.c

81

return (_reg_read_2(a_) << 16) | _reg_read_2(a_ + 2);

sys/arch/playstation2/dev/if_smap.c

173

r = _reg_read_2(SPD_INTR_ENABLE_REG16);

sys/arch/playstation2/dev/if_smap.c

273

cause = _reg_read_2(SPD_INTR_STATUS_REG16) &

sys/arch/playstation2/dev/if_smap.c

274

_reg_read_2(SPD_INTR_ENABLE_REG16);

sys/arch/playstation2/dev/if_smap.c

278

r = _reg_read_2(SPD_INTR_ENABLE_REG16);

sys/arch/playstation2/dev/if_smap.c

397

r16 = _reg_read_2(SPD_INTR_ENABLE_REG16);

sys/arch/playstation2/dev/if_smap.c

528

r16 = _reg_read_2(SPD_INTR_ENABLE_REG16);

sys/arch/playstation2/dev/if_smap.c

569

r16 = _reg_read_2(SPD_INTR_ENABLE_REG16);

sys/arch/playstation2/dev/sbus.c

254

if (_reg_read_2(SBUS_PCMCIA_CSC1_REG16) & 0x080)

sys/arch/playstation2/dev/sbus.c

275

u_int16_t r = _reg_read_2(SBUS_PCMCIA_TIMR_REG16);

sys/arch/playstation2/dev/sbus.c

305

u_int16_t r = _reg_read_2(SBUS_PCMCIA3_TIMR_REG16);

sys/arch/playstation2/dev/spd.c

108

_reg_write_2(SPD_INTR_CLEAR_REG16, _reg_read_2(SPD_INTR_STATUS_REG16));

sys/arch/playstation2/dev/spd.c

137

r = _reg_read_2(SPD_INTR_STATUS_REG16);

sys/arch/playstation2/dev/spd.c

151

r = _reg_read_2(SPD_INTR_ENABLE_REG16);

sys/arch/playstation2/dev/wdc_spd.c

236

r = _reg_read_2(SPD_INTR_ENABLE_REG16);

sys/arch/playstation2/dev/wdc_spd.c

246

r = _reg_read_2(SPD_INTR_ENABLE_REG16);

sys/arch/sh3/dev/rtc.c

170

year = _reg_read_2(SH4_RYRCNT) & 0x00ff;

sys/arch/sh3/dev/shpcic.c

118

if (_reg_read_2(SH4_BCR2) & BCR2_PORTEN)

sys/arch/sh3/dev/shpcic.c

161

_reg_write_4(SH4_PCIBCR2, _reg_read_2(SH4_BCR2));

sys/arch/sh3/dev/shpcic.c

168

_reg_write_4(SH4_PCIBCR3, _reg_read_2(SH4_BCR3));

sys/arch/sh3/sh3/interrupt.c

354

r = _reg_read_2(iprreg);