WRITE_REG
WRITE_REG(sc, CONREG,
WRITE_REG(sc, INTREG, (IMXSPI_TYPE(INTR_TC_EN) | IMXSPI(INTR_RR_EN)));
WRITE_REG(sc, STATREG, IMXSPI_TYPE(STAT_CLR));
WRITE_REG(sc, PERIODREG, 0x0);
WRITE_REG(sc, CONREG, contrl);
WRITE_REG(sc, CONREG, contrl);
WRITE_REG(sc, TXDATA, data);
WRITE_REG(sc, CONREG, READ_REG(sc, CONREG) | IMXSPI(CON_XCH));
WRITE_REG(sc, CONREG, chipselect);
WRITE_REG(sc, STATREG, sr);
WRITE_REG(reg, K_SMB_FREQ_100KHZ);
WRITE_REG(reg, 0); /* not in direct mode, no interrupts, will poll */
WRITE_REG(reg, (status & M_SMB_ERROR));
WRITE_REG(reg, (devaddr >> 8) & 0x7);
WRITE_REG(reg, (devaddr & 0xff) & 0xff);
WRITE_REG(reg, devaddr & 0xff);
WRITE_REG(reg, V_SMB_TT(K_SMB_TT_WR2BYTE) | V_SMB_ADDR(slaveaddr));
WRITE_REG(reg, V_SMB_TT(K_SMB_TT_WR1BYTE) | V_SMB_ADDR(slaveaddr));
WRITE_REG(reg, V_SMB_TT(K_SMB_TT_RD1BYTE) | V_SMB_ADDR(slaveaddr));
WRITE_REG(reg, (devaddr >> 8) & 0x7);
WRITE_REG(reg, devaddr & 0xff);
WRITE_REG(reg, (devaddr & 0xff) | ((b & 0xff) << 8));
WRITE_REG(reg, b & 0xff);
WRITE_REG(reg, V_SMB_TT(K_SMB_TT_WR3BYTE) | V_SMB_ADDR(slaveaddr));
WRITE_REG(reg, V_SMB_TT(K_SMB_TT_WR2BYTE) | V_SMB_ADDR(slaveaddr));
WRITE_REG(reg, V_SMB_TT(K_SMB_TT_RD1BYTE) | V_SMB_ADDR(slaveaddr));
WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_INTERRUPT_MASK, cpu->sb1cpu_imr_all);
WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_MAILBOX_SET_CPU, mbox_mask);
WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_MAILBOX_CLR_CPU, mbox_mask);
WRITE_REG(cpu->sb1cpu_imr_base + SB1250_I_MAP(i), K_INT_MAP_I0);
WRITE_REG(cpu->sb1cpu_imr_base + SB1250_I_MAP(K_INT_WATCHDOG_TIMER_0), K_INT_MAP_NMI);
WRITE_REG(cpu->sb1cpu_imr_base + SB1250_I_MAP(K_INT_WATCHDOG_TIMER_1), K_INT_MAP_NMI);
WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_INTERRUPT_MASK, cpu->sb1cpu_imr_all);
WRITE_REG(imr, imr_all);
WRITE_REG(MIPS_PHYS_TO_KSEG1(A_IMR_CPU0_BASE + R_IMR_INTERRUPT_MASK),
WRITE_REG(cpu->sb1cpu_imr_base + SB1250_I_MAP(num), K_INT_MAP_I4);
WRITE_REG(cpu->sb1cpu_imr_base + SB1250_I_MAP(num), K_INT_MAP_I1);
WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_INTERRUPT_MASK, cpu->sb1cpu_imr_all);
WRITE_REG(sc, HARMONY_RNXTADD, nextaddr);
WRITE_REG(sc, HARMONY_PNXTADD, nextaddr);
WRITE_REG(sc, HARMONY_GAINCTL, GAINCTL_OUTPUT_LEFT_M |
WRITE_REG(sc, HARMONY_RESET, RESET_RST);
WRITE_REG(sc, HARMONY_RESET, 0);
WRITE_REG(sc, HARMONY_OV, 0);
WRITE_REG(sc, HARMONY_DSTATUS, DSTATUS_IE);
WRITE_REG(sc, HARMONY_DSTATUS, 0);
WRITE_REG(sc, HARMONY_PNXTADD,
WRITE_REG(sc, HARMONY_RNXTADD,
WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS), 0);
WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS), 0);
WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS), 0);
WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS), 0);
WRITE_REG(ch->ch_output_reg, data);
WRITE_REG(MIPS_PHYS_TO_KSEG1(sbjcn_cons_addr + JTAG_CONS_OUTPUT), outbuf);
WRITE_REG(ch->ch_imr_base, 0);
WRITE_REG(ch->ch_base + 0x00, ch->ch_mode1);
WRITE_REG(ch->ch_base + 0x10, ch->ch_mode2);
WRITE_REG(ch->ch_base + 0x30, ch->ch_brc);
WRITE_REG(ch->ch_imr_base, ch->ch_imr);
WRITE_REG(ch->ch_imr_base, ch->ch_imr);
WRITE_REG(ch->ch_base + 0x70, c);
WRITE_REG(ch->ch_imr_base, ch->ch_imr);
WRITE_REG(ch->ch_imr_base, ch->ch_imr);
WRITE_REG(ch->ch_imr_base, ch->ch_imr);
WRITE_REG(ch->ch_imr_base, ch->ch_imr);
WRITE_REG(ch->ch_base + 0x70, c);
WRITE_REG(ch->ch_imr_base, ch->ch_imr);
WRITE_REG(base + 0x70, c);
WRITE_REG(imaskreg, 0); /* disable channel intrs */
WRITE_REG(chanregbase + 0x50, 2 << 4); /* reset receiver */
WRITE_REG(chanregbase + 0x50, 3 << 4); /* reset transmitter */
WRITE_REG(chanregbase + 0x00, mode1);
WRITE_REG(chanregbase + 0x10, mode2);
WRITE_REG(chanregbase + 0x30, brc);
WRITE_REG(chanregbase + 0x50,M_DUART_RX_EN | M_DUART_TX_EN);
WRITE_REG(MIPS_PHYS_TO_KSEG1((ch)->ch_sc->sc_addr + 0x2c0), \
WRITE_REG(MIPS_PHYS_TO_KSEG1((ch)->ch_sc->sc_addr + 0x2b0), \
WRITE_REG(MIPS_PHYS_TO_KSEG1(sc->sc_addr + 0x270), 0);
WRITE_REG(MIPS_PHYS_TO_KSEG1(sc->sc_addr + 0x210), 0x0f); /* XXX */
WRITE_REG(ch->ch_imr_base, ch->ch_imr);
WRITE_REG(ch->ch_imr_base, ch->ch_imr);
WRITE_REG(ch->ch_imr_base, ch->ch_imr);
WRITE_REG(ch->ch_imr_base, ch->ch_imr);
WRITE_REG(ch->ch_imr_base, ch->ch_imr);
WRITE_REG(ch->ch_base + 0x50, 0x60);
WRITE_REG(ch->ch_base + 0x50, 0x70);
WRITE_REG(sc->sc_addr_cfg, 0x00); /* XXX */
WRITE_REG(sc->sc_addr_cfg, 0x00); /* XXX */
WRITE_REG(sc->sc_addr_icnt, (tick/100) - 1); /* XXX */
WRITE_REG(sc->sc_addr_icnt, tick - 1); /* XXX */
WRITE_REG(sc->sc_addr_cfg, 0x03); /* XXX */
WRITE_REG(sc->sc_addr_cfg, 0x03); /* XXX */
WRITE_REG(sc->sc_addr_cfg, 0x00); /* XXX */
WRITE_REG(sc->sc_addr_cfg, 0x00); /* XXX */
WRITE_REG(sc->sc_addr + R_SCD_WDOG_CFG, M_SCD_WDOG_ENABLE);
WRITE_REG(sc->sc_addr + R_SCD_WDOG_CFG, M_SCD_WDOG_ENABLE);
WRITE_REG(sc->sc_addr + R_SCD_WDOG_CFG, 0);
WRITE_REG(sc->sc_addr + R_SCD_WDOG_INIT,
WRITE_REG(sc->sc_addr + R_SCD_WDOG_CFG, M_SCD_WDOG_ENABLE);
WRITE_REG(sc->sc_addr + R_SCD_WDOG_CFG, 0);
WRITE_REG(sc->sc_addr + R_SCD_WDOG_INIT,
WRITE_REG(reg, K_SMB_FREQ_100KHZ);
WRITE_REG(reg, 0); /* not in direct mode, no interrupts, will poll */
WRITE_REG(reg, (status & M_SMB_ERROR));
WRITE_REG(reg, (devaddr >> 8) & 0x7);
WRITE_REG(reg, (devaddr & 0xff) & 0xff);
WRITE_REG(reg, devaddr & 0xff);
WRITE_REG(reg, V_SMB_TT(K_SMB_TT_WR2BYTE) | V_SMB_ADDR(slaveaddr));
WRITE_REG(reg, V_SMB_TT(K_SMB_TT_WR1BYTE) | V_SMB_ADDR(slaveaddr));
WRITE_REG(reg, V_SMB_TT(K_SMB_TT_RD1BYTE) | V_SMB_ADDR(slaveaddr));
WRITE_REG(reg, (devaddr >> 8) & 0x7);
WRITE_REG(reg, devaddr & 0xff);
WRITE_REG(reg, (devaddr & 0xff) | ((b & 0xff) << 8));
WRITE_REG(reg, b & 0xff);
WRITE_REG(reg, V_SMB_TT(K_SMB_TT_WR3BYTE) | V_SMB_ADDR(slaveaddr));
WRITE_REG(reg, V_SMB_TT(K_SMB_TT_WR2BYTE) | V_SMB_ADDR(slaveaddr));
WRITE_REG(reg, V_SMB_TT(K_SMB_TT_RD1BYTE) | V_SMB_ADDR(slaveaddr));
WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_INTERRUPT_MASK, cpu->sb1cpu_imr_all);
WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_MAILBOX_SET_CPU, mbox_mask);
WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_MAILBOX_CLR_CPU, mbox_mask);
WRITE_REG(cpu->sb1cpu_imr_base + SB1250_I_MAP(i), K_INT_MAP_I0);
WRITE_REG(cpu->sb1cpu_imr_base + SB1250_I_MAP(K_INT_WATCHDOG_TIMER_0), K_INT_MAP_NMI);
WRITE_REG(cpu->sb1cpu_imr_base + SB1250_I_MAP(K_INT_WATCHDOG_TIMER_1), K_INT_MAP_NMI);
WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_INTERRUPT_MASK, cpu->sb1cpu_imr_all);
WRITE_REG(imr, imr_all);
WRITE_REG(MIPS_PHYS_TO_KSEG1(A_IMR_CPU0_BASE + R_IMR_INTERRUPT_MASK),
WRITE_REG(cpu->sb1cpu_imr_base + SB1250_I_MAP(num), K_INT_MAP_I4);
WRITE_REG(cpu->sb1cpu_imr_base + SB1250_I_MAP(num), K_INT_MAP_I1);
WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_INTERRUPT_MASK, cpu->sb1cpu_imr_all);
WRITE_REG(sc, TXP_H2A_2, BUS_ADDR_HI32(sc->sc_boot_dma.dma_paddr));
WRITE_REG(sc, TXP_H2A_1, BUS_ADDR_LO32(sc->sc_boot_dma.dma_paddr));
WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD);
WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL);
WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL);
WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL);
WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL);
WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF |
WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod));
WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite);
WRITE_REG(sc, TXP_IER, 0);
WRITE_REG(sc, TXP_IMR,
WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
WRITE_REG(sc, TXP_IER, 0);
WRITE_REG(sc, TXP_IMR,
WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL);
WRITE_REG(sc, TXP_SRR, 0);
WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0);
WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0);
WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr));
WRITE_REG(sc, TXP_H2A_2, le32toh(fileheader->hmac[0]));
WRITE_REG(sc, TXP_H2A_3, le32toh(fileheader->hmac[1]));
WRITE_REG(sc, TXP_H2A_4, le32toh(fileheader->hmac[2]));
WRITE_REG(sc, TXP_H2A_5, le32toh(fileheader->hmac[3]));
WRITE_REG(sc, TXP_H2A_6, le32toh(fileheader->hmac[4]));
WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE);
WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE);
WRITE_REG(sc, TXP_IER, ier);
WRITE_REG(sc, TXP_IMR, imr);
WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes));
WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum));
WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr));
WRITE_REG(sc, TXP_H2A_4, BUS_ADDR_HI32(dma.dma_paddr));
WRITE_REG(sc, TXP_H2A_5, BUS_ADDR_LO32(dma.dma_paddr));
WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE);
WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF |
WRITE_REG(sc, TXP_ISR, isr);
WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
WRITE_REG(sc, TXP_IMR,
WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr);
WRITE_REG(sc, BS_MCR4, q->q_mcr.dma_paddr);
WRITE_REG(sc, BS_CTRL, ctrl);
WRITE_REG(sc, BS_CFG, BS_CFG_RNG);
WRITE_REG(sc, BS_INT, BS_INT_DMAINT);
WRITE_REG(sc, BS_CTRL, ctrl);
WRITE_REG(sc, BS_CTRL, ctrl);
WRITE_REG(sc, BS_STAT, stat); /* IACK */
WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +