SCI_BUS_BSY
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
if ((*dev->sci_bus_csr & (SCI_BUS_BSY|SCI_BUS_SEL)) &&
(*dev->sci_bus_csr & (SCI_BUS_BSY|SCI_BUS_SEL)) &&
(*dev->sci_bus_csr & (SCI_BUS_BSY|SCI_BUS_SEL)))
while ((*dev->sci_bus_csr & SCI_BUS_BSY) == 0) {
if ((csr & SCI_BUS_BSY) == 0 || --wait < 0) {
if (!(csr & SCI_BUS_BSY) || --wait < 0) {
while ((*dev->sci_bus_csr & (SCI_BUS_REQ|SCI_BUS_BSY)) == SCI_BUS_BSY);
while (*dev->sci_bus_csr & SCI_BUS_BSY);
while ((*dev->sci_bus_csr & (SCI_BUS_REQ|SCI_BUS_BSY)) ==
SCI_BUS_BSY);
while (*dev->sci_bus_csr & SCI_BUS_BSY);
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY))
((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY))
((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ)))
if ((bus & SCI_BUS_BSY) == 0)
if (NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_BSY)
if ((NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_BSY) == 0) {
#define SCI_BUSY(sc) (NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_BSY)