RTW_READ
reg = RTW_READ(regs, RTW_CONFIG3);
RTW_WRITE(regs, RTW_FER, RTW_READ(regs, RTW_FER));
RTW_READ(&sc->sc_regs, RTW_FEMR) & ~RTW_FEMR_INTR);
uint32_t idr0 = RTW_READ(regs, RTW_IDR0),
idr1 = RTW_READ(regs, RTW_IDR1);
tsfth = RTW_READ(&sc->sc_regs, RTW_TSFTRH);
tsftl = RTW_READ(&sc->sc_regs, RTW_TSFTRL);
return (le32toh(RTW_READ(regs, tdb->tdb_basereg)) - tdb->tdb_base) /
tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL);
tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL);
anaparm = RTW_READ(regs, RTW_ANAPARM);
anaparm = RTW_READ(regs, RTW_ANAPARM);
dvname, reg, RTW_READ(regs, reg)))
anaparm = RTW_READ(regs, RTW_ANAPARM);
tcr = RTW_READ(regs, RTW_TCR);
device_xname(sc->sc_dev), RTW_READ(regs, RTW_MAR0),
RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR)));
tcr = RTW_READ(regs, RTW_TCR);
tsfth = RTW_READ(regs, RTW_TSFTRH);
tsftl = RTW_READ(regs, RTW_TSFTRL);
if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC)
switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) {
sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR);
anaparm = RTW_READ(regs, RTW_ANAPARM);
if (__SHIFTOUT(RTW_READ(regs, RTW_BB),
if ((RTW_READ(regs, RTW_PHYCFG) & RTW_PHYCFG_MAC_POLL) == 0) {
return __SHIFTOUT(RTW_READ(regs, RTW_BB), RTW_BB_RD_MASK);
(RTW_READ((regs), (reg)) & (mask))
RTW_WRITE((regs), (reg), RTW_READ((regs), (reg)) & ~(mask))