Symbol: READ_REG
sys/arch/arm/imx/imxspi.c
143
contrl = READ_REG(sc, CONREG);
sys/arch/arm/imx/imxspi.c
192
contrl = READ_REG(sc, CONREG);
sys/arch/arm/imx/imxspi.c
243
if (READ_REG(sc, STATREG) & IMXSPI(STAT_TF))
sys/arch/arm/imx/imxspi.c
260
if (!(READ_REG(sc, STATREG) & IMXSPI(INTR_TE_EN)))
sys/arch/arm/imx/imxspi.c
261
WRITE_REG(sc, CONREG, READ_REG(sc, CONREG) | IMXSPI(CON_XCH));
sys/arch/arm/imx/imxspi.c
273
if ((!(READ_REG(sc, STATREG) & IMXSPI(STAT_RR))))
sys/arch/arm/imx/imxspi.c
277
data = READ_REG(sc, RXDATA);
sys/arch/arm/imx/imxspi.c
310
chipselect = READ_REG(sc, CONREG);
sys/arch/arm/imx/imxspi.c
357
if ((intr = READ_REG(sc, INTREG)) == 0) {
sys/arch/arm/imx/imxspi.c
363
sr = READ_REG(sc, STATREG);
sys/arch/evbmips/sbmips/cpu.c
107
plldiv = G_SYS_PLL_DIV(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_CFG)));
sys/arch/evbmips/sbmips/cpu.c
81
part = G_SYS_PART(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_REVISION)));
sys/arch/evbmips/sbmips/rtc.c
443
status = READ_REG(reg);
sys/arch/evbmips/sbmips/rtc.c
524
err = READ_REG(reg);
sys/arch/evbmips/sbmips/sb1250_icu.c
197
mbox_mask = READ_REG(cpu->sb1cpu_imr_base + R_IMR_MAILBOX_CPU);
sys/arch/evbmips/sbmips/sb1250_icu.c
268
u_int sys_part = G_SYS_PART(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_REVISION)));
sys/arch/evbmips/sbmips/sb1250_icu.c
312
sstatus &= READ_REG(imr_base + R_IMR_INTERRUPT_SOURCE_STATUS);
sys/arch/hppa/gsc/harmony.c
186
(sc)->sc_acc |= READ_REG((sc), HARMONY_DIAG) & DIAG_CO; \
sys/arch/hppa/gsc/harmony.c
231
cntl = READ_REG(sc, HARMONY_ID);
sys/arch/hppa/gsc/harmony.c
313
cntl = READ_REG(sc, HARMONY_CNTL);
sys/arch/hppa/gsc/harmony.c
383
dstatus = READ_REG(sc, HARMONY_DSTATUS);
sys/arch/hppa/gsc/harmony.c
395
if (READ_REG(sc, HARMONY_OV) & OV_OV) {
sys/arch/hppa/gsc/harmony.c
492
reg = READ_REG(sc, HARMONY_CNTL);
sys/arch/hppa/gsc/harmony.c
517
reg = READ_REG(sc, HARMONY_DSTATUS);
sys/arch/mips/sibyte/dev/sbbuswatch.c
51
(void)READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_BUS_ERR_STATUS));
sys/arch/mips/sibyte/dev/sbbuswatch.c
75
bus_err_status = READ_REG(
sys/arch/mips/sibyte/dev/sbbuswatch.c
81
l2_errors = READ_REG(
sys/arch/mips/sibyte/dev/sbbuswatch.c
86
mem_io_errors = READ_REG(
sys/arch/mips/sibyte/dev/sbjcn.c
1051
while (((reg = READ_REG(ch->ch_input_reg)) != 0) && --timo)
sys/arch/mips/sibyte/dev/sbjcn.c
1473
inbuf = READ_REG(ch->ch_input_reg);
sys/arch/mips/sibyte/dev/sbjcn.c
1515
while ((ctrl_val = READ_REG(MIPS_PHYS_TO_KSEG1(sbjcn_cons_addr + JTAG_CONS_CONTROL))) == 0)
sys/arch/mips/sibyte/dev/sbjcn.c
1561
inbuf = READ_REG(MIPS_PHYS_TO_KSEG1(sbjcn_cons_addr + JTAG_CONS_INPUT));
sys/arch/mips/sibyte/dev/sbscn.c
1139
while (ISSET(READ_REG(ch->ch_base + 0x20), 0x01)
sys/arch/mips/sibyte/dev/sbscn.c
1146
READ_REG(ch->ch_base + 0x60);
sys/arch/mips/sibyte/dev/sbscn.c
1266
while (ch->ch_tbc && READ_REG(ch->ch_base + 0x20) & 0x04) {
sys/arch/mips/sibyte/dev/sbscn.c
1489
isr = READ_REG(ch->ch_isr_base) & ch->ch_imr;
sys/arch/mips/sibyte/dev/sbscn.c
1502
sr = READ_REG(ch->ch_base + 0x20);
sys/arch/mips/sibyte/dev/sbscn.c
1509
(void)READ_REG(ch->ch_base + 0x60);
sys/arch/mips/sibyte/dev/sbscn.c
1516
(void)READ_REG(ch->ch_base + 0x60);
sys/arch/mips/sibyte/dev/sbscn.c
1526
put[0] = READ_REG(ch->ch_base + 0x60);
sys/arch/mips/sibyte/dev/sbscn.c
1533
sr = READ_REG(ch->ch_base + 0x20);
sys/arch/mips/sibyte/dev/sbscn.c
1616
} while ((isr = (READ_REG(ch->ch_isr_base) & ch->ch_imr)) != 0);
sys/arch/mips/sibyte/dev/sbscn.c
1624
sr = READ_REG(ch->ch_base + 0x20);
sys/arch/mips/sibyte/dev/sbscn.c
1645
READ_REG(ch->ch_base + 0x20) & 0x04) {
sys/arch/mips/sibyte/dev/sbscn.c
1688
while ((READ_REG(base + 0x20) & 0x01) == 0)
sys/arch/mips/sibyte/dev/sbscn.c
1691
c = READ_REG(base + 0x60) & 0xff;
sys/arch/mips/sibyte/dev/sbscn.c
1705
while ((READ_REG(base + 0x20) & 0x08) == 0 && --timo)
sys/arch/mips/sibyte/dev/sbscn.c
1712
while ((READ_REG(base + 0x20) & 0x08) == 0 && --timo)
sys/arch/mips/sibyte/dev/sbscn.c
1736
while ((READ_REG(chanregbase + 0x20) & 0x08) == 0 && --timo)
sys/arch/mips/sibyte/dev/sbscn.c
255
((~READ_REG(MIPS_PHYS_TO_KSEG1((ch)->ch_sc->sc_addr + 0x280))) & (ch)->ch_i_mask)
sys/arch/mips/sibyte/dev/sbtimer.c
160
if (G_SYS_PLL_DIV(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_CFG))) == 0) {
sys/arch/sbmips/sbmips/cpu.c
106
plldiv = G_SYS_PLL_DIV(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_CFG)));
sys/arch/sbmips/sbmips/cpu.c
80
part = G_SYS_PART(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_REVISION)));
sys/arch/sbmips/sbmips/rtc.c
443
status = READ_REG(reg);
sys/arch/sbmips/sbmips/rtc.c
524
err = READ_REG(reg);
sys/arch/sbmips/sbmips/sb1250_icu.c
197
mbox_mask = READ_REG(cpu->sb1cpu_imr_base + R_IMR_MAILBOX_CPU);
sys/arch/sbmips/sbmips/sb1250_icu.c
268
u_int sys_part = G_SYS_PART(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_REVISION)));
sys/arch/sbmips/sbmips/sb1250_icu.c
312
sstatus &= READ_REG(imr_base + R_IMR_INTERRUPT_SOURCE_STATUS);
sys/dev/pci/if_txp.c
1193
r = READ_REG(sc, TXP_A2H_0);
sys/dev/pci/if_txp.c
1208
r = READ_REG(sc, TXP_A2H_0);
sys/dev/pci/if_txp.c
421
r = READ_REG(sc, TXP_A2H_0);
sys/dev/pci/if_txp.c
443
ier = READ_REG(sc, TXP_IER);
sys/dev/pci/if_txp.c
446
imr = READ_REG(sc, TXP_IMR);
sys/dev/pci/if_txp.c
450
r = READ_REG(sc, TXP_A2H_0);
sys/dev/pci/if_txp.c
500
r = READ_REG(sc, TXP_A2H_0);
sys/dev/pci/if_txp.c
522
r = READ_REG(sc, TXP_ISR);
sys/dev/pci/if_txp.c
535
r = READ_REG(sc, TXP_A2H_0);
sys/dev/pci/if_txp.c
642
isr = READ_REG(sc, TXP_ISR);
sys/dev/pci/if_txp.c
663
isr = READ_REG(sc, TXP_ISR);
sys/dev/pci/ubsec.c
1871
if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL)
sys/dev/pci/ubsec.c
1899
if (READ_REG(sc, BS_STAT) & BS_STAT_MCR4_FULL)
sys/dev/pci/ubsec.c
2179
ctrl = READ_REG(sc, BS_CTRL);
sys/dev/pci/ubsec.c
2205
ctrl = READ_REG(sc, BS_CTRL);
sys/dev/pci/ubsec.c
528
ctrl = READ_REG(sc, BS_CTRL);
sys/dev/pci/ubsec.c
645
stat = READ_REG(sc, BS_STAT);
sys/dev/pci/ubsec.c
773
volatile u_int32_t a = READ_REG(sc, BS_ERR);
sys/dev/pci/ubsec.c
843
if ((stat = READ_REG(sc, BS_STAT))
sys/dev/pci/ubsec.c
909
if ((stat = READ_REG(sc, BS_STAT))