Symbol: A_IMR_CPU0_BASE
sys/arch/evbmips/sbmips/sb1250_icu.c
275
vaddr_t imr = MIPS_PHYS_TO_KSEG1(A_IMR_CPU0_BASE + R_IMR_INTERRUPT_MASK);
sys/arch/evbmips/sbmips/sb1250_icu.c
280
WRITE_REG(MIPS_PHYS_TO_KSEG1(A_IMR_CPU0_BASE + R_IMR_INTERRUPT_MASK),
sys/arch/mips/sibyte/dev/sbscd.c
61
{ A_IMR_CPU0_BASE,
sys/arch/mips/sibyte/include/sb1250_regs.h
723
#define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING)
sys/arch/mips/sibyte/include/sb1250_regs.h
750
(A_IMR_CPU0_BASE + (cpu * IMR_REGISTER_SPACING) + reg)
sys/arch/sbmips/sbmips/sb1250_icu.c
275
vaddr_t imr = MIPS_PHYS_TO_KSEG1(A_IMR_CPU0_BASE + R_IMR_INTERRUPT_MASK);
sys/arch/sbmips/sbmips/sb1250_icu.c
280
WRITE_REG(MIPS_PHYS_TO_KSEG1(A_IMR_CPU0_BASE + R_IMR_INTERRUPT_MASK),