PSL_S
[IPL_NONE] = PSL_IPL0|PSL_S,
[IPL_SOFTCLOCK] = PSL_IPL1|PSL_S,
[IPL_VM] = PSL_IPL4|PSL_S,
[IPL_SCHED] = PSL_IPL4|PSL_S,
[IPL_HIGH] = PSL_IPL4|PSL_S,
[IPL_SCHED] = PSL_IPL6|PSL_S,
[IPL_HIGH] = PSL_IPL7|PSL_S,
needpsl = PSL_S | (supa->supio_ipl << 8);
needpsl = PSL_S|PSL_IPL6;
[IPL_NONE] = PSL_S | PSL_IPL0,
[IPL_SOFTCLOCK] = PSL_S | PSL_IPL1,
[IPL_SOFTBIO] = PSL_S | PSL_IPL1,
[IPL_SOFTNET] = PSL_S | PSL_IPL1,
[IPL_SOFTSERIAL] = PSL_S | PSL_IPL1,
[IPL_VM] = PSL_S | PSL_IPL4,
[IPL_SCHED] = PSL_S | PSL_IPL6,
[IPL_HIGH] = PSL_S | PSL_IPL7,
lesc->sc_splval = (va->va_irq << 8) | PSL_S; /* XXX */
if (rp[PS] & PSL_S) {
#define CLKF_USERMODE(framep) (((framep)->cf_sr & PSL_S) == 0)
#define splsoftclock() _splraise(PSL_S | MACHINE_PSL_IPL_SOFTCLOCK)
#define splsoftbio() _splraise(PSL_S | MACHINE_PSL_IPL_SOFTBIO)
#define splsoftnet() _splraise(PSL_S | MACHINE_PSL_IPL_SOFTNET)
#define splsoftserial() _splraise(PSL_S | MACHINE_PSL_IPL_SOFTSERIAL)
#define splvm() _splraise(PSL_S | MACHINE_PSL_IPL_VM)
#define splsched() _splraise(PSL_S | MACHINE_PSL_IPL_SCHED)
#define _spl0() _spl(PSL_S|PSL_IPL0)
#define spl1() _spl(PSL_S|PSL_IPL1)
#define spl2() _spl(PSL_S|PSL_IPL2)
#define spl3() _spl(PSL_S|PSL_IPL3)
#define spl4() _spl(PSL_S|PSL_IPL4)
#define spl5() _spl(PSL_S|PSL_IPL5)
#define spl6() _spl(PSL_S|PSL_IPL6)
#define spl7() _spl(PSL_S|PSL_IPL7)
#define splraise1() _splraise(PSL_S|PSL_IPL1)
#define splraise2() _splraise(PSL_S|PSL_IPL2)
#define splraise3() _splraise(PSL_S|PSL_IPL3)
#define splraise4() _splraise(PSL_S|PSL_IPL4)
#define splraise5() _splraise(PSL_S|PSL_IPL5)
#define splraise6() _splraise(PSL_S|PSL_IPL6)
#define splraise7() _splraise(PSL_S|PSL_IPL7)
#define PSL_LOWIPL (PSL_S)
#define PSL_HIGHIPL (PSL_S | PSL_IPL7)
#define PSL_USERCLR (PSL_S | PSL_IPL7 | PSL_MBZ)
#define IPLTOPSL(x) ((((x) & 0x7) << 8) | PSL_S)
#define USERMODE(ps) (((ps) & PSL_S) == 0)
if ((scp->sc_ps & (PSL_MBZ|PSL_IPL|PSL_S)) != 0)
if ((scp->sc_ps & (PSL_MBZ|PSL_IPL|PSL_S)) != 0)
[IPL_NONE] = PSL_S | PSL_IPL0,
[IPL_SOFTBIO] = PSL_S | MACHINE_PSL_IPL_SOFTBIO,
[IPL_SOFTCLOCK] = PSL_S | MACHINE_PSL_IPL_SOFTCLOCK,
[IPL_SOFTNET] = PSL_S | MACHINE_PSL_IPL_SOFTNET,
[IPL_SOFTSERIAL] = PSL_S | MACHINE_PSL_IPL_SOFTSERIAL,
[IPL_VM] = PSL_S | MACHINE_PSL_IPL_VM,
[IPL_SCHED] = PSL_S | MACHINE_PSL_IPL_SCHED,
[IPL_HIGH] = PSL_S | PSL_IPL7,
if (tf->tf_sr & PSL_S) {
if ((gr[_REG_PS] & (PSL_MBZ|PSL_IPL|PSL_S)) != 0)
if ((scp->sc_ps & (PSL_MBZ|PSL_IPL|PSL_S)) != 0)
.cf_sr = PSL_S,
ipl2psl_table[IPL_SOFTCLOCK] = PSL_S|PSL_IPL1;
ipl2psl_table[IPL_SOFTNET] = PSL_S|PSL_IPL1;
ipl2psl_table[IPL_SOFTSERIAL] = PSL_S|PSL_IPL1;
ipl2psl_table[IPL_SOFTBIO] = PSL_S|PSL_IPL1;
ipl2psl_table[IPL_HIGH] = PSL_S|PSL_IPL7;
ipl2psl_table[IPL_VM] = (PSL_S | PSL_IPL6);
ipl2psl_table[IPL_SCHED] = (PSL_S | PSL_IPL6);
ipl2psl_table[IPL_VM] = (PSL_S | PSL_IPL2);
ipl2psl_table[IPL_SCHED] = (PSL_S | PSL_IPL3);
ipl2psl_table[IPL_VM] = (PSL_S | PSL_IPL4);
ipl2psl_table[IPL_SCHED] = (PSL_S | PSL_IPL4);
#define PSL_USERCLR (PSL_S | PSL_IPL1F | PSL_MBZ)
[IPL_NONE] = PSL_S | PSL_IPL0,
[IPL_SOFTCLOCK] = PSL_S | PSL_IPL1,
[IPL_SOFTBIO] = PSL_S | PSL_IPL1,
[IPL_SOFTNET] = PSL_S | PSL_IPL1,
[IPL_SOFTSERIAL] = PSL_S | PSL_IPL1,
[IPL_VM] = PSL_S | PSL_IPL5,
[IPL_SCHED] = PSL_S | PSL_IPL6,
[IPL_HIGH] = PSL_S | PSL_IPL7,
[IPL_NONE] = PSL_S | PSL_IPL0,
[IPL_SOFTCLOCK] = PSL_S | PSL_IPL1,
[IPL_SOFTBIO] = PSL_S | PSL_IPL1,
[IPL_SOFTNET] = PSL_S | PSL_IPL1,
[IPL_SOFTSERIAL] = PSL_S | PSL_IPL1,
[IPL_VM] = PSL_S | PSL_IPL5,
[IPL_SCHED] = PSL_S | PSL_IPL7,
[IPL_HIGH] = PSL_S | PSL_IPL7,
frame->f_sr = scp->sc_ps & ~(PSL_MBZ|PSL_IPL|PSL_S);
frame->f_sr = tuc.uc_mc.mc_gregs.gr_sr & ~(PSL_MBZ|PSL_IPL|PSL_S);
uc->uc_mcontext.__gregs[_REG_PS] |= (PSL_MBZ|PSL_IPL|PSL_S);