PSL_DR
if ((msr & (PSL_IR|PSL_DR)) == 0) {
: "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI));
rmsr = omsr & ~(PSL_DR);
rmsr = omsr & ~(PSL_DR);
: : "r" (0), "K" (PSL_IR|PSL_DR|PSL_ME));
: : "r" (0), "K" (PSL_IR|PSL_DR));
if ((s & (PSL_IR | PSL_DR)) != (PSL_IR | PSL_DR)) \
#define PSL_USERSET (PSL_EE | PSL_PR | PSL_IR | PSL_DR | PSL_ME)
#define PSL_USERSET (PSL_EE | PSL_PR | PSL_IR | PSL_DR | PSL_ME)
#define PSL_USERSET (PSL_EE | PSL_PR | PSL_IR | PSL_DR)
#define PSL_DS PSL_DR /* B... data address space */
msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI;
cpu_psluserset = PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI;
: "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI));
if ((msr & (PSL_IR|PSL_DR)) == 0) {
: "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI));
if ((msr & PSL_DR) == 0) {
MTMSR(msr & ~PSL_DR);
MTMSR(msr & ~PSL_DR);
MTMSR(msr & ~(PSL_IR|PSL_DR));
MTMSR(msr & ~(PSL_IR|PSL_DR));
PSL_FE1 | PSL_IR | PSL_DR | PSL_RI));
msr = savemsr & ~PSL_DR;
__asm volatile ("mtmsr %0" : : "r"(msr|PSL_DR));
msr = savemsr & ~PSL_DR;
__asm volatile ("mtmsr %0" : : "r"(msr|PSL_DR));
mtmsr(msr|PSL_DR);
mtmsr(msr|PSL_DR);
msr = savemsr & ~PSL_DR;
__asm volatile ("mtmsr %0" : : "r"(msr|PSL_DR));
msr = savemsr|PSL_DR;
msr = savemsr & ~PSL_DR;
__asm volatile ("mtmsr %0" : : "r"(msr|PSL_DR));
msr &= ~(PSL_ME | PSL_DR | PSL_IR);
msr &= ~(PSL_ME | PSL_DR | PSL_IR);