PCI_COMMAND_IO_ENABLE
csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
v |= PCI_COMMAND_IO_ENABLE |
PCI_COMMAND_IO_ENABLE);
csr |= (PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE);
csr &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE);
if ((csr & PCI_COMMAND_IO_ENABLE) != 0)
if (!(p->csr & PCI_COMMAND_IO_ENABLE)) {
p->address, p->size, PCI_COMMAND_IO_ENABLE));
csr |= PCI_COMMAND_IO_ENABLE |
csr |= (PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE);
csr |= (PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE);
enable |= PCI_COMMAND_IO_ENABLE;
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
data |= PCI_COMMAND_IO_ENABLE;
if (data & PCI_COMMAND_IO_ENABLE)
data |= PCI_COMMAND_IO_ENABLE;
data |= PCI_COMMAND_IO_ENABLE;
csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE);
PCI_COMMAND_IO_ENABLE |
elroy_write32(&r->pci_cmdstat, htole32(PCI_COMMAND_IO_ENABLE |
csr &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE);
csr |= PCI_COMMAND_IO_ENABLE;
PCI_COMMAND_IO_ENABLE|
PCI_COMMAND_IO_ENABLE|
PCI_COMMAND_IO_ENABLE|
PCI_COMMAND_IO_ENABLE|
x |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
enable |= PCI_COMMAND_IO_ENABLE;
_reg_write_4(SH4_PCICONF1, PCI_COMMAND_IO_ENABLE
cmd | PCI_COMMAND_IO_ENABLE);
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE
| PCI_COMMAND_IO_ENABLE | PCI_COMMAND_PARITY_ENABLE);
PCI_COMMAND_IO_ENABLE;
val |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
val &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
, .r_mask = PCI_COMMAND_IO_ENABLE
if ((csr & PCI_COMMAND_IO_ENABLE) == 0 ||
(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE))
csr |= PCI_COMMAND_IO_ENABLE;
csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
command |= (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_IO_ENABLE |
csc->cc_csr |= PCI_COMMAND_IO_ENABLE;
reg &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE);
csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
csr &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE,
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE;
csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
csr &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
csr |= PCI_COMMAND_IO_ENABLE;
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
csr |= PCI_COMMAND_IO_ENABLE;
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE;
command |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE;
csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE);
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE);
if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
command | (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
command &= ~PCI_COMMAND_IO_ENABLE;
if (command & PCI_COMMAND_IO_ENABLE) {
csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE);
screg |= PCI_COMMAND_IO_ENABLE;
screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE |
data |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE
csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE);
(PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE));
csr |= PCI_COMMAND_IO_ENABLE;
cmd &= ~PCI_COMMAND_IO_ENABLE;
command |= PCI_COMMAND_IO_ENABLE;
psc->psc_csr |= PCI_COMMAND_IO_ENABLE;
csr &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
command |= PCI_COMMAND_IO_ENABLE |
if (!(command & PCI_COMMAND_IO_ENABLE)) {
reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
command |= PCI_COMMAND_IO_ENABLE;
command &= ~PCI_COMMAND_IO_ENABLE;
csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE
csr & ~PCI_COMMAND_IO_ENABLE);
PCI_COMMAND_IO_ENABLE : PCI_COMMAND_MEM_ENABLE;
csr & ~PCI_COMMAND_IO_ENABLE) ;
if ((cmd & PCI_COMMAND_IO_ENABLE) != 0) {
cmd |= PCI_COMMAND_IO_ENABLE;
PCI_COMMAND_IO_ENABLE);
cmd &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE|
if ((cmd & PCI_COMMAND_IO_ENABLE) != 0) {
onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE);
ioen = rval & PCI_COMMAND_IO_ENABLE;
cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
cmd |= PCI_COMMAND_IO_ENABLE;
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE);
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE);
csr & ~PCI_COMMAND_IO_ENABLE);
if ((csr & PCI_COMMAND_IO_ENABLE) == 0) {
csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE);
screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) !=
(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) {
command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE;
screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
& (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))
!= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))
csr |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE;
reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |