OUTW
OUTW(SSCOM_UCON, 0);
OUTW(SSCOM_UBRDIV, rate);
OUTW(SSCOM_ULCON, ULCON_PARITY_NONE|ULCON_LENGTH_8);
OUTW(SSCOM_UCON, UCON_TXMODE_INT|UCON_RXMODE_INT);
OUTW(SSCOM_UMCON, UMCON_RTS);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_RISC_DISABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_ENABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, bktr->capcontrol);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_ENABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, bktr->capcontrol);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_ENABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_ENABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, bktr->capcontrol);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_RISC_DISABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_RISC_DISABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_ENABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, bktr->capcontrol);
OUTW(bktr, BKTR_GPIO_DMA_CTL, INW(bktr, BKTR_GPIO_DMA_CTL) & ~FIFO_RISC_ENABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_RISC_DISABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_RISC_DISABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_RISC_DISABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_ENABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, bktr->capcontrol);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_ENABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_RISC_DISABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_RISC_DISABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_RISC_DISABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_RISC_DISABLED);
OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_RISC_DISABLED);