ATA_READ
sc->sc_bio.flags |= ATA_READ;
if (sc->sc_bio.flags & ATA_READ) {
if (sc->sc_bio.flags & ATA_READ) {
sc->sc_bio.flags |= ATA_READ;
*cmd = (xfer->c_bio.flags & ATA_READ) ?
dma_flags = (ata_bio->flags & ATA_READ) ? WDC_DMA_READ : 0;
cmd = (ata_bio->flags & ATA_READ) ?
cmd = (ata_bio->flags & ATA_READ) ?
cmd = (ata_bio->flags & ATA_READ) ?
if ((ata_bio->flags & ATA_READ) == 0) {
if ((ata_bio->flags & ATA_READ) != 0) {
fis[rhd_command] = (ata_bio->flags & ATA_READ) ?
(ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA;
xfer->c_bio.flags |= ATA_READ;
(ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) {
((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) |
(ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD :
if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR)
cmd = (ata_bio->flags & ATA_READ) ?
cmd = (ata_bio->flags & ATA_READ) ?
if ((ata_bio->flags & ATA_READ) == 0) {
if ((ata_bio->flags & ATA_READ) != 0) {
sc_xfer->xs_control & XS_CTL_DATA_IN ? ATA_READ : 0);
lop = (flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE;
sop = (flags & ATA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE;
(flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE;
cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA;
rw = (xfer->c_bio.flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE;
(ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) {
(ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD :
if ((xfer->c_flags & C_NCQ) != 0 && ata_bio->flags & ATA_READ)