sys/arch/evbppc/mpc85xx/machdep.c

1022

cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */

sys/arch/evbppc/mpc85xx/machdep.c

1230

cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST);

sys/arch/evbppc/mpc85xx/machdep.c

1231

while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST)

sys/arch/evbppc/mpc85xx/machdep.c

1234

cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */

sys/arch/evbppc/mpc85xx/machdep.c

1237

cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR));

sys/arch/powerpc/booke/e500_intr.c

465

OPENPIC_BASE + offset);

sys/arch/powerpc/booke/e500_intr.c

473

OPENPIC_BASE + offset, val);

sys/arch/powerpc/booke/e500_timer.c

74

OPENPIC_BASE + offset, val);

sys/arch/powerpc/booke/pci/pq3pci.c

1167

msig->msig_msir = OPENPIC_BASE + OPENPIC_MSIR(msig->msig_group);

sys/arch/powerpc/booke/pci/pq3pci.c

1481

sc->sc_bst->pbs_offset + OPENPIC_BASE + OPENPIC_MSIIR);