games/trek/phaser.c

107

int hitreqd[NBANKS];

games/trek/phaser.c

108

struct banks bank[NBANKS];

games/trek/phaser.c

156

for (i = 0; i < NBANKS; i++)

games/trek/phaser.c

164

for (i = 0; i < NBANKS; i++) {

games/trek/phaser.c

213

if (n > NBANKS)

games/trek/phaser.c

214

n = NBANKS;

games/trek/phaser.c

269

for (i = 0; i < NBANKS; i++) {

games/trek/phaser.c

282

for (i = 0; i < NBANKS; i++) {

games/trek/phaser.c

352

for (i = 0; i < NBANKS; i++)

sys/arch/arm/rockchip/rk3288_iomux.c

111

static int rk3288_iomux_offset[NBANKS][NPINSPERBANK / 8] = {

sys/arch/arm/rockchip/rk3288_iomux.c

129

if (bank >= NBANKS || idx >= NPINSPERBANK) {

sys/arch/arm/rockchip/rk3288_iomux.c

99

static uint32_t rk3288_iomux_flags[NBANKS][NPINSPERBANK / 8] = {

sys/arch/arm/rockchip/rk3588_iomux.c

275

static const struct regmask rk3588_pull_regmap[NBANKS * NPINPERBANK] = {

sys/arch/arm/rockchip/rk3588_iomux.c

463

static const struct regmask rk3588_schmitt_regmap[NBANKS * NPINPERBANK] = {

sys/arch/arm/rockchip/rk3588_iomux.c

651

static const struct regmaskreg rk3588_iomux_regmap[NBANKS * NPINPERBANK] = {

sys/arch/arm/rockchip/rk3588_iomux.c

68

#define NPINS (NBANKS * NPINPERBANK)

sys/arch/arm/rockchip/rk3588_iomux.c

83

static const struct regmask rk3588_drive_regmap[NBANKS * NPINPERBANK] = {

sys/arch/mips/cavium/octeon_intr.c

285

for (bank = 0; bank < NBANKS; bank++) {

sys/arch/mips/cavium/octeon_intr.c

296

for (bank = 0; bank < NBANKS; bank++) {

sys/arch/mips/cavium/octeonvar.h

93

uint64_t cpu_ip2_en[NBANKS];

sys/arch/mips/cavium/octeonvar.h

94

uint64_t cpu_ip3_en[NBANKS];

sys/arch/mips/cavium/octeonvar.h

95

uint64_t cpu_ip4_en[NBANKS];

sys/arch/mips/cavium/octeonvar.h

97

uint64_t cpu_ip2_enable[NBANKS];

sys/arch/mips/cavium/octeonvar.h

98

uint64_t cpu_ip3_enable[NBANKS];

sys/arch/mips/cavium/octeonvar.h

99

uint64_t cpu_ip4_enable[NBANKS];