#ifndef _nbio_6_3_2_OFFSET_HEADER
#define _nbio_6_3_2_OFFSET_HEADER
#define regBIF_BX0_SYSHUB_INDEX_OVLP 0x0008
#define regBIF_BX0_SYSHUB_INDEX_OVLP_BASE_IDX 0
#define regBIF_BX0_SYSHUB_DATA_OVLP 0x0009
#define regBIF_BX0_SYSHUB_DATA_OVLP_BASE_IDX 0
#define regBIF_BX0_SYSHUB_INDEX_HI_OVLP 0x000a
#define regBIF_BX0_SYSHUB_INDEX_HI_OVLP_BASE_IDX 0
#define regBIF_BX0_PCIE_INDEX 0x000c
#define regBIF_BX0_PCIE_INDEX_BASE_IDX 0
#define regBIF_BX0_PCIE_DATA 0x000d
#define regBIF_BX0_PCIE_DATA_BASE_IDX 0
#define regBIF_BX0_PCIE_INDEX2 0x000e
#define regBIF_BX0_PCIE_INDEX2_BASE_IDX 0
#define regBIF_BX0_PCIE_DATA2 0x000f
#define regBIF_BX0_PCIE_DATA2_BASE_IDX 0
#define regBIF_BX0_PCIE_INDEX_HI 0x0010
#define regBIF_BX0_PCIE_INDEX_HI_BASE_IDX 0
#define regBIF_BX0_PCIE_INDEX2_HI 0x0011
#define regBIF_BX0_PCIE_INDEX2_HI_BASE_IDX 0
#define regBIF_BX0_SBIOS_SCRATCH_0 0x0034
#define regBIF_BX0_SBIOS_SCRATCH_0_BASE_IDX 1
#define regBIF_BX0_SBIOS_SCRATCH_1 0x0035
#define regBIF_BX0_SBIOS_SCRATCH_1_BASE_IDX 1
#define regBIF_BX0_SBIOS_SCRATCH_2 0x0036
#define regBIF_BX0_SBIOS_SCRATCH_2_BASE_IDX 1
#define regBIF_BX0_SBIOS_SCRATCH_3 0x0037
#define regBIF_BX0_SBIOS_SCRATCH_3_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_0 0x0038
#define regBIF_BX0_BIOS_SCRATCH_0_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_1 0x0039
#define regBIF_BX0_BIOS_SCRATCH_1_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_2 0x003a
#define regBIF_BX0_BIOS_SCRATCH_2_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_3 0x003b
#define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_4 0x003c
#define regBIF_BX0_BIOS_SCRATCH_4_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_5 0x003d
#define regBIF_BX0_BIOS_SCRATCH_5_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_6 0x003e
#define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_7 0x003f
#define regBIF_BX0_BIOS_SCRATCH_7_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_8 0x0040
#define regBIF_BX0_BIOS_SCRATCH_8_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_9 0x0041
#define regBIF_BX0_BIOS_SCRATCH_9_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_10 0x0042
#define regBIF_BX0_BIOS_SCRATCH_10_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_11 0x0043
#define regBIF_BX0_BIOS_SCRATCH_11_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_12 0x0044
#define regBIF_BX0_BIOS_SCRATCH_12_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_13 0x0045
#define regBIF_BX0_BIOS_SCRATCH_13_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_14 0x0046
#define regBIF_BX0_BIOS_SCRATCH_14_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_15 0x0047
#define regBIF_BX0_BIOS_SCRATCH_15_BASE_IDX 1
#define regBIF_BX0_BIF_RLC_INTR_CNTL 0x004c
#define regBIF_BX0_BIF_RLC_INTR_CNTL_BASE_IDX 1
#define regBIF_BX0_BIF_VCE_INTR_CNTL 0x004d
#define regBIF_BX0_BIF_VCE_INTR_CNTL_BASE_IDX 1
#define regBIF_BX0_BIF_UVD_INTR_CNTL 0x004e
#define regBIF_BX0_BIF_UVD_INTR_CNTL_BASE_IDX 1
#define regBIF_BX0_BIF_Engine_INTR_CNTL 0x004f
#define regBIF_BX0_BIF_Engine_INTR_CNTL_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0 0x006c
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 0x006d
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1 0x006e
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 0x006f
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2 0x0070
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 0x0071
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3 0x0072
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 0x0073
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4 0x0074
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 0x0075
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5 0x0076
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 0x0077
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6 0x0078
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 0x0079
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7 0x007a
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 0x007b
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_CNTL 0x007c
#define regBIF_BX0_GFX_MMIOREG_CAM_CNTL_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL 0x007d
#define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL 0x007e
#define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f
#define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1
#define regBIF_BX0_DRIVER_SCRATCH_0 0x0080
#define regBIF_BX0_DRIVER_SCRATCH_0_BASE_IDX 1
#define regBIF_BX0_DRIVER_SCRATCH_1 0x0081
#define regBIF_BX0_DRIVER_SCRATCH_1_BASE_IDX 1
#define regBIF_BX0_DRIVER_SCRATCH_2 0x0082
#define regBIF_BX0_DRIVER_SCRATCH_2_BASE_IDX 1
#define regBIF_BX0_DRIVER_SCRATCH_3 0x0083
#define regBIF_BX0_DRIVER_SCRATCH_3_BASE_IDX 1
#define regBIF_BX0_DRIVER_SCRATCH_4 0x0084
#define regBIF_BX0_DRIVER_SCRATCH_4_BASE_IDX 1
#define regBIF_BX0_DRIVER_SCRATCH_5 0x0085
#define regBIF_BX0_DRIVER_SCRATCH_5_BASE_IDX 1
#define regBIF_BX0_DRIVER_SCRATCH_6 0x0086
#define regBIF_BX0_DRIVER_SCRATCH_6_BASE_IDX 1
#define regBIF_BX0_DRIVER_SCRATCH_7 0x0087
#define regBIF_BX0_DRIVER_SCRATCH_7_BASE_IDX 1
#define regBIF_BX0_DRIVER_SCRATCH_8 0x0088
#define regBIF_BX0_DRIVER_SCRATCH_8_BASE_IDX 1
#define regBIF_BX0_DRIVER_SCRATCH_9 0x0089
#define regBIF_BX0_DRIVER_SCRATCH_9_BASE_IDX 1
#define regBIF_BX0_DRIVER_SCRATCH_10 0x008a
#define regBIF_BX0_DRIVER_SCRATCH_10_BASE_IDX 1
#define regBIF_BX0_DRIVER_SCRATCH_11 0x008b
#define regBIF_BX0_DRIVER_SCRATCH_11_BASE_IDX 1
#define regBIF_BX0_DRIVER_SCRATCH_12 0x008c
#define regBIF_BX0_DRIVER_SCRATCH_12_BASE_IDX 1
#define regBIF_BX0_DRIVER_SCRATCH_13 0x008d
#define regBIF_BX0_DRIVER_SCRATCH_13_BASE_IDX 1
#define regBIF_BX0_DRIVER_SCRATCH_14 0x008e
#define regBIF_BX0_DRIVER_SCRATCH_14_BASE_IDX 1
#define regBIF_BX0_DRIVER_SCRATCH_15 0x008f
#define regBIF_BX0_DRIVER_SCRATCH_15_BASE_IDX 1
#define regBIF_BX0_FW_SCRATCH_0 0x0090
#define regBIF_BX0_FW_SCRATCH_0_BASE_IDX 1
#define regBIF_BX0_FW_SCRATCH_1 0x0091
#define regBIF_BX0_FW_SCRATCH_1_BASE_IDX 1
#define regBIF_BX0_FW_SCRATCH_2 0x0092
#define regBIF_BX0_FW_SCRATCH_2_BASE_IDX 1
#define regBIF_BX0_FW_SCRATCH_3 0x0093
#define regBIF_BX0_FW_SCRATCH_3_BASE_IDX 1
#define regBIF_BX0_FW_SCRATCH_4 0x0094
#define regBIF_BX0_FW_SCRATCH_4_BASE_IDX 1
#define regBIF_BX0_FW_SCRATCH_5 0x0095
#define regBIF_BX0_FW_SCRATCH_5_BASE_IDX 1
#define regBIF_BX0_FW_SCRATCH_6 0x0096
#define regBIF_BX0_FW_SCRATCH_6_BASE_IDX 1
#define regBIF_BX0_FW_SCRATCH_7 0x0097
#define regBIF_BX0_FW_SCRATCH_7_BASE_IDX 1
#define regBIF_BX0_FW_SCRATCH_8 0x0098
#define regBIF_BX0_FW_SCRATCH_8_BASE_IDX 1
#define regBIF_BX0_FW_SCRATCH_9 0x0099
#define regBIF_BX0_FW_SCRATCH_9_BASE_IDX 1
#define regBIF_BX0_FW_SCRATCH_10 0x009a
#define regBIF_BX0_FW_SCRATCH_10_BASE_IDX 1
#define regBIF_BX0_FW_SCRATCH_11 0x009b
#define regBIF_BX0_FW_SCRATCH_11_BASE_IDX 1
#define regBIF_BX0_FW_SCRATCH_12 0x009c
#define regBIF_BX0_FW_SCRATCH_12_BASE_IDX 1
#define regBIF_BX0_FW_SCRATCH_13 0x009d
#define regBIF_BX0_FW_SCRATCH_13_BASE_IDX 1
#define regBIF_BX0_FW_SCRATCH_14 0x009e
#define regBIF_BX0_FW_SCRATCH_14_BASE_IDX 1
#define regBIF_BX0_FW_SCRATCH_15 0x009f
#define regBIF_BX0_FW_SCRATCH_15_BASE_IDX 1
#define regBIF_BX0_SBIOS_SCRATCH_4 0x00a0
#define regBIF_BX0_SBIOS_SCRATCH_4_BASE_IDX 1
#define regBIF_BX0_SBIOS_SCRATCH_5 0x00a1
#define regBIF_BX0_SBIOS_SCRATCH_5_BASE_IDX 1
#define regBIF_BX0_SBIOS_SCRATCH_6 0x00a2
#define regBIF_BX0_SBIOS_SCRATCH_6_BASE_IDX 1
#define regBIF_BX0_SBIOS_SCRATCH_7 0x00a3
#define regBIF_BX0_SBIOS_SCRATCH_7_BASE_IDX 1
#define regBIF_BX0_SBIOS_SCRATCH_8 0x00a4
#define regBIF_BX0_SBIOS_SCRATCH_8_BASE_IDX 1
#define regBIF_BX0_SBIOS_SCRATCH_9 0x00a5
#define regBIF_BX0_SBIOS_SCRATCH_9_BASE_IDX 1
#define regBIF_BX0_SBIOS_SCRATCH_10 0x00a6
#define regBIF_BX0_SBIOS_SCRATCH_10_BASE_IDX 1
#define regBIF_BX0_SBIOS_SCRATCH_11 0x00a7
#define regBIF_BX0_SBIOS_SCRATCH_11_BASE_IDX 1
#define regBIF_BX0_SBIOS_SCRATCH_12 0x00a8
#define regBIF_BX0_SBIOS_SCRATCH_12_BASE_IDX 1
#define regBIF_BX0_SBIOS_SCRATCH_13 0x00a9
#define regBIF_BX0_SBIOS_SCRATCH_13_BASE_IDX 1
#define regBIF_BX0_SBIOS_SCRATCH_14 0x00aa
#define regBIF_BX0_SBIOS_SCRATCH_14_BASE_IDX 1
#define regBIF_BX0_SBIOS_SCRATCH_15 0x00ab
#define regBIF_BX0_SBIOS_SCRATCH_15_BASE_IDX 1
#define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED 0x0068
#define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED_BASE_IDX 2
#define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH 0x0069
#define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_BASE_IDX 2
#define regRCC_DWN_DEV0_0_DN_PCIE_CNTL 0x006b
#define regRCC_DWN_DEV0_0_DN_PCIE_CNTL_BASE_IDX 2
#define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL 0x006c
#define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_BASE_IDX 2
#define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 0x006d
#define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_BASE_IDX 2
#define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL 0x006e
#define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_BASE_IDX 2
#define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL 0x006f
#define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_BASE_IDX 2
#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 0x0070
#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_BASE_IDX 2
#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC 0x0071
#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_BASE_IDX 2
#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 0x0072
#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_BASE_IDX 2
#define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL 0x0074
#define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_BASE_IDX 2
#define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL 0x0075
#define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL_BASE_IDX 2
#define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL 0x0076
#define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_BASE_IDX 2
#define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2 0x0077
#define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_BASE_IDX 2
#define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC 0x0078
#define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_BASE_IDX 2
#define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP 0x0079
#define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_BASE_IDX 2
#define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH 0x004b
#define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH_BASE_IDX 2
#define regRCC_EP_DEV0_0_EP_PCIE_CNTL 0x004d
#define regRCC_EP_DEV0_0_EP_PCIE_CNTL_BASE_IDX 2
#define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL 0x004e
#define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_BASE_IDX 2
#define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS 0x004f
#define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_BASE_IDX 2
#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 0x0050
#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_BASE_IDX 2
#define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL 0x0051
#define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_BASE_IDX 2
#define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL 0x0052
#define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_BASE_IDX 2
#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x0054
#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_BASE_IDX 2
#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x0055
#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2
#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x0055
#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2
#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x0055
#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2
#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x0055
#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2
#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x0056
#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2
#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x0056
#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2
#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x0056
#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2
#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x0056
#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2
#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC 0x0057
#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_BASE_IDX 2
#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 0x0058
#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_BASE_IDX 2
#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP 0x005a
#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_BASE_IDX 2
#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x005b
#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2
#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL 0x005b
#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_BASE_IDX 2
#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x005b
#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2
#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x005c
#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2
#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x005c
#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2
#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x005c
#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2
#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x005c
#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2
#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x005d
#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2
#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x005d
#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2
#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x005d
#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2
#define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL 0x005d
#define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_BASE_IDX 2
#define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED 0x005e
#define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED_BASE_IDX 2
#define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL 0x0060
#define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_BASE_IDX 2
#define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID 0x0061
#define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 2
#define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL 0x0062
#define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_BASE_IDX 2
#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL 0x0063
#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_BASE_IDX 2
#define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL 0x0064
#define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 2
#define regRCC_EP_DEV0_0_EP_PCIE_DEVICE_CNTL3 0x0065
#define regRCC_EP_DEV0_0_EP_PCIE_DEVICE_CNTL3_BASE_IDX 2
#define regBIF_BX_PF0_MM_INDEX 0x0000
#define regBIF_BX_PF0_MM_INDEX_BASE_IDX 0
#define regBIF_BX_PF0_MM_DATA 0x0001
#define regBIF_BX_PF0_MM_DATA_BASE_IDX 0
#define regBIF_BX_PF0_MM_INDEX_HI 0x0006
#define regBIF_BX_PF0_MM_INDEX_HI_BASE_IDX 0
#define regBIF_BX_PF0_RSMU_INDEX 0x0000
#define regBIF_BX_PF0_RSMU_INDEX_BASE_IDX 1
#define regBIF_BX_PF0_RSMU_DATA 0x0001
#define regBIF_BX_PF0_RSMU_DATA_BASE_IDX 1
#define regBIF_BX_PF0_RSMU_INDEX_HI 0x0002
#define regBIF_BX_PF0_RSMU_INDEX_HI_BASE_IDX 1
#define regBIF_BX0_CC_BIF_BX_STRAP0 0x00e2
#define regBIF_BX0_CC_BIF_BX_STRAP0_BASE_IDX 2
#define regBIF_BX0_CC_BIF_BX_PINSTRAP0 0x00e4
#define regBIF_BX0_CC_BIF_BX_PINSTRAP0_BASE_IDX 2
#define regBIF_BX0_BIF_MM_INDACCESS_CNTL 0x00e6
#define regBIF_BX0_BIF_MM_INDACCESS_CNTL_BASE_IDX 2
#define regBIF_BX0_BUS_CNTL 0x00e7
#define regBIF_BX0_BUS_CNTL_BASE_IDX 2
#define regBIF_BX0_BIF_SCRATCH0 0x00e8
#define regBIF_BX0_BIF_SCRATCH0_BASE_IDX 2
#define regBIF_BX0_BIF_SCRATCH1 0x00e9
#define regBIF_BX0_BIF_SCRATCH1_BASE_IDX 2
#define regBIF_BX0_BX_RESET_EN 0x00ed
#define regBIF_BX0_BX_RESET_EN_BASE_IDX 2
#define regBIF_BX0_MM_CFGREGS_CNTL 0x00ee
#define regBIF_BX0_MM_CFGREGS_CNTL_BASE_IDX 2
#define regBIF_BX0_BX_RESET_CNTL 0x00f0
#define regBIF_BX0_BX_RESET_CNTL_BASE_IDX 2
#define regBIF_BX0_INTERRUPT_CNTL 0x00f1
#define regBIF_BX0_INTERRUPT_CNTL_BASE_IDX 2
#define regBIF_BX0_INTERRUPT_CNTL2 0x00f2
#define regBIF_BX0_INTERRUPT_CNTL2_BASE_IDX 2
#define regBIF_BX0_CLKREQB_PAD_CNTL 0x00f8
#define regBIF_BX0_CLKREQB_PAD_CNTL_BASE_IDX 2
#define regBIF_BX0_BIF_FEATURES_CONTROL_MISC 0x00fb
#define regBIF_BX0_BIF_FEATURES_CONTROL_MISC_BASE_IDX 2
#define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC 0x00fc
#define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 2
#define regBIF_BX0_BIF_DOORBELL_CNTL 0x00fd
#define regBIF_BX0_BIF_DOORBELL_CNTL_BASE_IDX 2
#define regBIF_BX0_BIF_DOORBELL_INT_CNTL 0x00fe
#define regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX 2
#define regBIF_BX0_BIF_FB_EN 0x0100
#define regBIF_BX0_BIF_FB_EN_BASE_IDX 2
#define regBIF_BX0_BIF_INTR_CNTL 0x0101
#define regBIF_BX0_BIF_INTR_CNTL_BASE_IDX 2
#define regBIF_BX0_BIF_MST_TRANS_PENDING_VF 0x0109
#define regBIF_BX0_BIF_MST_TRANS_PENDING_VF_BASE_IDX 2
#define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF 0x010a
#define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 2
#define regBIF_BX0_BACO_CNTL 0x010b
#define regBIF_BX0_BACO_CNTL_BASE_IDX 2
#define regBIF_BX0_BIF_BACO_EXIT_TIME0 0x010c
#define regBIF_BX0_BIF_BACO_EXIT_TIME0_BASE_IDX 2
#define regBIF_BX0_BIF_BACO_EXIT_TIMER1 0x010d
#define regBIF_BX0_BIF_BACO_EXIT_TIMER1_BASE_IDX 2
#define regBIF_BX0_BIF_BACO_EXIT_TIMER2 0x010e
#define regBIF_BX0_BIF_BACO_EXIT_TIMER2_BASE_IDX 2
#define regBIF_BX0_BIF_BACO_EXIT_TIMER3 0x010f
#define regBIF_BX0_BIF_BACO_EXIT_TIMER3_BASE_IDX 2
#define regBIF_BX0_BIF_BACO_EXIT_TIMER4 0x0110
#define regBIF_BX0_BIF_BACO_EXIT_TIMER4_BASE_IDX 2
#define regBIF_BX0_MEM_TYPE_CNTL 0x0111
#define regBIF_BX0_MEM_TYPE_CNTL_BASE_IDX 2
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL 0x0113
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 2
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_0 0x0114
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_0_BASE_IDX 2
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_1 0x0115
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_1_BASE_IDX 2
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_2 0x0116
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_2_BASE_IDX 2
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_3 0x0117
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_3_BASE_IDX 2
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_4 0x0118
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_4_BASE_IDX 2
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_5 0x0119
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_5_BASE_IDX 2
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_6 0x011a
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_6_BASE_IDX 2
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_7 0x011b
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_7_BASE_IDX 2
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_8 0x011c
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_8_BASE_IDX 2
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_9 0x011d
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_9_BASE_IDX 2
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_10 0x011e
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_10_BASE_IDX 2
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_11 0x011f
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_11_BASE_IDX 2
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_12 0x0120
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_12_BASE_IDX 2
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_13 0x0121
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_13_BASE_IDX 2
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_14 0x0122
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_14_BASE_IDX 2
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_15 0x0123
#define regBIF_BX0_NBIF_GFX_ADDR_LUT_15_BASE_IDX 2
#define regBIF_BX0_VF_REGWR_EN 0x0124
#define regBIF_BX0_VF_REGWR_EN_BASE_IDX 2
#define regBIF_BX0_VF_DOORBELL_EN 0x0125
#define regBIF_BX0_VF_DOORBELL_EN_BASE_IDX 2
#define regBIF_BX0_VF_FB_EN 0x0126
#define regBIF_BX0_VF_FB_EN_BASE_IDX 2
#define regBIF_BX0_VF_REGWR_STATUS 0x0127
#define regBIF_BX0_VF_REGWR_STATUS_BASE_IDX 2
#define regBIF_BX0_VF_DOORBELL_STATUS 0x0128
#define regBIF_BX0_VF_DOORBELL_STATUS_BASE_IDX 2
#define regBIF_BX0_VF_FB_STATUS 0x0129
#define regBIF_BX0_VF_FB_STATUS_BASE_IDX 2
#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL 0x012d
#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2
#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL 0x012e
#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2
#define regBIF_BX0_BIF_RB_CNTL 0x012f
#define regBIF_BX0_BIF_RB_CNTL_BASE_IDX 2
#define regBIF_BX0_BIF_RB_BASE 0x0130
#define regBIF_BX0_BIF_RB_BASE_BASE_IDX 2
#define regBIF_BX0_BIF_RB_RPTR 0x0131
#define regBIF_BX0_BIF_RB_RPTR_BASE_IDX 2
#define regBIF_BX0_BIF_RB_WPTR 0x0132
#define regBIF_BX0_BIF_RB_WPTR_BASE_IDX 2
#define regBIF_BX0_BIF_RB_WPTR_ADDR_HI 0x0133
#define regBIF_BX0_BIF_RB_WPTR_ADDR_HI_BASE_IDX 2
#define regBIF_BX0_BIF_RB_WPTR_ADDR_LO 0x0134
#define regBIF_BX0_BIF_RB_WPTR_ADDR_LO_BASE_IDX 2
#define regBIF_BX0_MAILBOX_INDEX 0x0135
#define regBIF_BX0_MAILBOX_INDEX_BASE_IDX 2
#define regBIF_BX0_BACO_AZ_ENHANCE_CTRL 0x0141
#define regBIF_BX0_BACO_AZ_ENHANCE_CTRL_BASE_IDX 2
#define regBIF_BX0_BIF_MP1_INTR_CTRL 0x0142
#define regBIF_BX0_BIF_MP1_INTR_CTRL_BASE_IDX 2
#define regBIF_BX0_BIF_PERSTB_PAD_CNTL 0x0145
#define regBIF_BX0_BIF_PERSTB_PAD_CNTL_BASE_IDX 2
#define regBIF_BX0_BIF_PX_EN_PAD_CNTL 0x0146
#define regBIF_BX0_BIF_PX_EN_PAD_CNTL_BASE_IDX 2
#define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL 0x0147
#define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 2
#define regBIF_BX0_BIF_CLKREQB_PAD_CNTL 0x0148
#define regBIF_BX0_BIF_CLKREQB_PAD_CNTL_BASE_IDX 2
#define regBIF_BX0_BIF_PWRBRK_PAD_CNTL 0x0149
#define regBIF_BX0_BIF_PWRBRK_PAD_CNTL_BASE_IDX 2
#define regBIF_BX0_BIF_GPUIOV_SCH_CFG_SIZE 0x0165
#define regBIF_BX0_BIF_GPUIOV_SCH_CFG_SIZE_BASE_IDX 2
#define regRCC_DEV0_0_RCC_ERR_INT_CNTL 0x0086
#define regRCC_DEV0_0_RCC_ERR_INT_CNTL_BASE_IDX 2
#define regRCC_DEV0_0_RCC_BACO_CNTL_MISC 0x0087
#define regRCC_DEV0_0_RCC_BACO_CNTL_MISC_BASE_IDX 2
#define regRCC_DEV0_0_RCC_RESET_EN 0x0088
#define regRCC_DEV0_0_RCC_RESET_EN_BASE_IDX 2
#define regRCC_DEV0_0_RCC_VDM_SUPPORT 0x0089
#define regRCC_DEV0_0_RCC_VDM_SUPPORT_BASE_IDX 2
#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 0x008a
#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 2
#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 0x008b
#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 2
#define regRCC_DEV0_0_RCC_GPUIOV_REGION 0x008c
#define regRCC_DEV0_0_RCC_GPUIOV_REGION_BASE_IDX 2
#define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN 0x008d
#define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN_BASE_IDX 2
#define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL 0x008e
#define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 2
#define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x008f
#define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 2
#define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE 0x008f
#define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 2
#define regRCC_DEV0_0_RCC_PEER_REG_RANGE0 0x00be
#define regRCC_DEV0_0_RCC_PEER_REG_RANGE0_BASE_IDX 2
#define regRCC_DEV0_0_RCC_PEER_REG_RANGE1 0x00bf
#define regRCC_DEV0_0_RCC_PEER_REG_RANGE1_BASE_IDX 2
#define regRCC_DEV0_0_RCC_BUS_CNTL 0x00c1
#define regRCC_DEV0_0_RCC_BUS_CNTL_BASE_IDX 2
#define regRCC_DEV0_0_RCC_CONFIG_CNTL 0x00c2
#define regRCC_DEV0_0_RCC_CONFIG_CNTL_BASE_IDX 2
#define regRCC_DEV0_0_RCC_CONFIG_F0_BASE 0x00c6
#define regRCC_DEV0_0_RCC_CONFIG_F0_BASE_BASE_IDX 2
#define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE 0x00c7
#define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE_BASE_IDX 2
#define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE 0x00c8
#define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 2
#define regRCC_DEV0_0_RCC_XDMA_LO 0x00c9
#define regRCC_DEV0_0_RCC_XDMA_LO_BASE_IDX 2
#define regRCC_DEV0_0_RCC_XDMA_HI 0x00ca
#define regRCC_DEV0_0_RCC_XDMA_HI_BASE_IDX 2
#define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC 0x00cb
#define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_BASE_IDX 2
#define regRCC_DEV0_0_RCC_BUSNUM_CNTL1 0x00cc
#define regRCC_DEV0_0_RCC_BUSNUM_CNTL1_BASE_IDX 2
#define regRCC_DEV0_0_RCC_BUSNUM_LIST0 0x00cd
#define regRCC_DEV0_0_RCC_BUSNUM_LIST0_BASE_IDX 2
#define regRCC_DEV0_0_RCC_BUSNUM_LIST1 0x00ce
#define regRCC_DEV0_0_RCC_BUSNUM_LIST1_BASE_IDX 2
#define regRCC_DEV0_0_RCC_BUSNUM_CNTL2 0x00cf
#define regRCC_DEV0_0_RCC_BUSNUM_CNTL2_BASE_IDX 2
#define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM 0x00d0
#define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2
#define regRCC_DEV0_0_RCC_HOST_BUSNUM 0x00d1
#define regRCC_DEV0_0_RCC_HOST_BUSNUM_BASE_IDX 2
#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI 0x00d2
#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 2
#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO 0x00d3
#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 2
#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI 0x00d4
#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 2
#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO 0x00d5
#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 2
#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI 0x00d6
#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 2
#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO 0x00d7
#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 2
#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI 0x00d8
#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 2
#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO 0x00d9
#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 2
#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0 0x00da
#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0_BASE_IDX 2
#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1 0x00db
#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1_BASE_IDX 2
#define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL 0x00dd
#define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL_BASE_IDX 2
#define regRCC_DEV0_0_RCC_CMN_LINK_CNTL 0x00de
#define regRCC_DEV0_0_RCC_CMN_LINK_CNTL_BASE_IDX 2
#define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE 0x00df
#define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 2
#define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL 0x00e0
#define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_BASE_IDX 2
#define regRCC_DEV0_0_RCC_MH_ARB_CNTL 0x00e1
#define regRCC_DEV0_0_RCC_MH_ARB_CNTL_BASE_IDX 2
#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO 0x0400
#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI 0x0401
#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA 0x0402
#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL 0x0403
#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO 0x0404
#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI 0x0405
#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA 0x0406
#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL 0x0407
#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO 0x0408
#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI 0x0409
#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA 0x040a
#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL 0x040b
#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO 0x040c
#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI 0x040d
#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA 0x040e
#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL 0x040f
#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_LO 0x0410
#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_HI 0x0411
#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_MSG_DATA 0x0412
#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_CONTROL 0x0413
#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_LO 0x0414
#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_HI 0x0415
#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_MSG_DATA 0x0416
#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_CONTROL 0x0417
#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_LO 0x0418
#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_HI 0x0419
#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_MSG_DATA 0x041a
#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_CONTROL 0x041b
#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_LO 0x041c
#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_HI 0x041d
#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_MSG_DATA 0x041e
#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_CONTROL 0x041f
#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_LO 0x0420
#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_HI 0x0421
#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_MSG_DATA 0x0422
#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_CONTROL 0x0423
#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_GFXMSIX_PBA 0x0800
#define regRCC_DEV0_EPF0_GFXMSIX_PBA_BASE_IDX 3
#define regRCC_STRAP0_RCC_BIF_STRAP0 0x0000
#define regRCC_STRAP0_RCC_BIF_STRAP0_BASE_IDX 2
#define regRCC_STRAP0_RCC_BIF_STRAP1 0x0001
#define regRCC_STRAP0_RCC_BIF_STRAP1_BASE_IDX 2
#define regRCC_STRAP0_RCC_BIF_STRAP10 0x0002
#define regRCC_STRAP0_RCC_BIF_STRAP10_BASE_IDX 2
#define regRCC_STRAP0_RCC_BIF_STRAP11 0x0003
#define regRCC_STRAP0_RCC_BIF_STRAP11_BASE_IDX 2
#define regRCC_STRAP0_RCC_BIF_STRAP12 0x0004
#define regRCC_STRAP0_RCC_BIF_STRAP12_BASE_IDX 2
#define regRCC_STRAP0_RCC_BIF_STRAP13 0x0005
#define regRCC_STRAP0_RCC_BIF_STRAP13_BASE_IDX 2
#define regRCC_STRAP0_RCC_BIF_STRAP2 0x0006
#define regRCC_STRAP0_RCC_BIF_STRAP2_BASE_IDX 2
#define regRCC_STRAP0_RCC_BIF_STRAP3 0x0007
#define regRCC_STRAP0_RCC_BIF_STRAP3_BASE_IDX 2
#define regRCC_STRAP0_RCC_BIF_STRAP4 0x0008
#define regRCC_STRAP0_RCC_BIF_STRAP4_BASE_IDX 2
#define regRCC_STRAP0_RCC_BIF_STRAP5 0x0009
#define regRCC_STRAP0_RCC_BIF_STRAP5_BASE_IDX 2
#define regRCC_STRAP0_RCC_BIF_STRAP6 0x000a
#define regRCC_STRAP0_RCC_BIF_STRAP6_BASE_IDX 2
#define regRCC_STRAP0_RCC_BIF_STRAP7 0x000b
#define regRCC_STRAP0_RCC_BIF_STRAP7_BASE_IDX 2
#define regRCC_STRAP0_RCC_BIF_STRAP8 0x000c
#define regRCC_STRAP0_RCC_BIF_STRAP8_BASE_IDX 2
#define regRCC_STRAP0_RCC_BIF_STRAP9 0x000d
#define regRCC_STRAP0_RCC_BIF_STRAP9_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0 0x000e
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1 0x000f
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10 0x0010
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11 0x0011
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12 0x0012
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13 0x0013
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14 0x0014
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP15 0x0015
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP15_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP16 0x0016
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP16_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP17 0x0017
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP17_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP18 0x0018
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP18_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2 0x0019
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3 0x001a
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4 0x001b
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5 0x001c
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6 0x001d
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7 0x001e
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8 0x001f
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9 0x0020
#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0 0x0021
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1 0x0022
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13 0x0023
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14 0x0024
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15 0x0025
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16 0x0026
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17 0x0027
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18 0x0028
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP19 0x0029
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP19_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2 0x002a
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP22 0x002b
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP22_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP23 0x002c
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP23_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP24 0x002d
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP24_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3 0x002e
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4 0x002f
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5 0x0030
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8 0x0031
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9 0x0032
#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0 0x0033
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP1 0x0034
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP1_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP10 0x0035
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP10_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP11 0x0036
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP11_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP12 0x0037
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP12_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP13 0x0038
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP13_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP14 0x0039
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP14_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP15 0x003a
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP15_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP16 0x003b
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP16_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP17 0x003c
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP17_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP18 0x003d
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP18_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP19 0x003e
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP19_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2 0x003f
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20 0x0040
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21 0x0041
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23 0x0042
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24 0x0043
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3 0x0044
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4 0x0045
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5 0x0046
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6 0x0047
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7 0x0048
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP8 0x0049
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP8_BASE_IDX 2
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP9 0x004a
#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP9_BASE_IDX 2
#define regBIF_BX_PF0_BIF_BME_STATUS 0x00eb
#define regBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX 2
#define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG 0x00ec
#define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
#define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
#define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
#define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
#define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ 0x0106
#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2
#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE 0x0107
#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2
#define regBIF_BX_PF0_BIF_TRANS_PENDING 0x0108
#define regBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX 2
#define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
#define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 0x0136
#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 0x0137
#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 0x0138
#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 0x0139
#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 0x013a
#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 0x013b
#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 0x013c
#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 0x013d
#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
#define regBIF_BX_PF0_MAILBOX_CONTROL 0x013e
#define regBIF_BX_PF0_MAILBOX_CONTROL_BASE_IDX 2
#define regBIF_BX_PF0_MAILBOX_INT_CNTL 0x013f
#define regBIF_BX_PF0_MAILBOX_INT_CNTL_BASE_IDX 2
#define regBIF_BX_PF0_BIF_VMHV_MAILBOX 0x0140
#define regBIF_BX_PF0_BIF_VMHV_MAILBOX_BASE_IDX 2
#define regBIF_BX_PF0_PARTITION_COMPUTE_CAP 0x0161
#define regBIF_BX_PF0_PARTITION_COMPUTE_CAP_BASE_IDX 2
#define regBIF_BX_PF0_PARTITION_MEM_CAP 0x0162
#define regBIF_BX_PF0_PARTITION_MEM_CAP_BASE_IDX 2
#define regBIF_BX_PF0_PARTITION_COMPUTE_STATUS 0x0163
#define regBIF_BX_PF0_PARTITION_COMPUTE_STATUS_BASE_IDX 2
#define regBIF_BX_PF0_PARTITION_MEM_STATUS 0x0164
#define regBIF_BX_PF0_PARTITION_MEM_STATUS_BASE_IDX 2
#define regRCC_DEV0_EPF0_RCC_ERR_LOG 0x0085
#define regRCC_DEV0_EPF0_RCC_ERR_LOG_BASE_IDX 2
#define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x00c0
#define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX 2
#define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE 0x00c3
#define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2
#define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED 0x00c4
#define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_BASE_IDX 2
#define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5
#define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
#define regGDC0_NGDC_SDP_PORT_CTRL 0x0180
#define regGDC0_NGDC_SDP_PORT_CTRL_BASE_IDX 2
#define regGDC0_SHUB_REGS_IF_CTL 0x0181
#define regGDC0_SHUB_REGS_IF_CTL_BASE_IDX 2
#define regGDC0_NGDC_MGCG_CTRL 0x0187
#define regGDC0_NGDC_MGCG_CTRL_BASE_IDX 2
#define regGDC0_S2A_MISC_CNTL 0x0188
#define regGDC0_S2A_MISC_CNTL_BASE_IDX 2
#define regGDC0_NGDC_MCA_SMN_CTRL0 0x018b
#define regGDC0_NGDC_MCA_SMN_CTRL0_BASE_IDX 2
#define regGDC0_NGDC_EARLY_WAKEUP_CTRL 0x018c
#define regGDC0_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX 2
#define regGDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL 0x0198
#define regGDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL_BASE_IDX 2
#define regGDC0_GDC_DMA_SION_PCTRL 0x0199
#define regGDC0_GDC_DMA_SION_PCTRL_BASE_IDX 2
#define regGDC0_NGDC_MP4SDP_CNTL 0x019b
#define regGDC0_NGDC_MP4SDP_CNTL_BASE_IDX 2
#define regGDC0_DOORBELL_VCN_TARGET_VF0 0x01f3
#define regGDC0_DOORBELL_VCN_TARGET_VF0_BASE_IDX 2
#define regGDC0_DOORBELL_VCN_TARGET_VF1 0x01f3
#define regGDC0_DOORBELL_VCN_TARGET_VF1_BASE_IDX 2
#define regGDC0_DOORBELL_VCN_TARGET_VF2 0x01f4
#define regGDC0_DOORBELL_VCN_TARGET_VF2_BASE_IDX 2
#define regGDC0_DOORBELL_VCN_TARGET_VF3 0x01f4
#define regGDC0_DOORBELL_VCN_TARGET_VF3_BASE_IDX 2
#define regGDC0_DOORBELL_VCN_TARGET_VF4 0x01f5
#define regGDC0_DOORBELL_VCN_TARGET_VF4_BASE_IDX 2
#define regGDC0_DOORBELL_VCN_TARGET_VF5 0x01f5
#define regGDC0_DOORBELL_VCN_TARGET_VF5_BASE_IDX 2
#define regGDC0_DOORBELL_VCN_TARGET_VF6 0x01f6
#define regGDC0_DOORBELL_VCN_TARGET_VF6_BASE_IDX 2
#define regGDC0_DOORBELL_VCN_TARGET_VF7 0x01f6
#define regGDC0_DOORBELL_VCN_TARGET_VF7_BASE_IDX 2
#define regGDC0_DOORBELL_ACCESS_EN_PF 0x01f7
#define regGDC0_DOORBELL_ACCESS_EN_PF_BASE_IDX 2
#define regGDC0_DOORBELL_ACCESS_EN_VF0 0x01f7
#define regGDC0_DOORBELL_ACCESS_EN_VF0_BASE_IDX 2
#define regGDC0_DOORBELL_ACCESS_EN_VF1 0x01f8
#define regGDC0_DOORBELL_ACCESS_EN_VF1_BASE_IDX 2
#define regGDC0_DOORBELL_ACCESS_EN_VF2 0x01f8
#define regGDC0_DOORBELL_ACCESS_EN_VF2_BASE_IDX 2
#define regGDC0_DOORBELL_ACCESS_EN_VF3 0x01f9
#define regGDC0_DOORBELL_ACCESS_EN_VF3_BASE_IDX 2
#define regGDC0_DOORBELL_ACCESS_EN_VF4 0x01f9
#define regGDC0_DOORBELL_ACCESS_EN_VF4_BASE_IDX 2
#define regGDC0_DOORBELL_ACCESS_EN_VF5 0x01fa
#define regGDC0_DOORBELL_ACCESS_EN_VF5_BASE_IDX 2
#define regGDC0_DOORBELL_ACCESS_EN_VF6 0x01fa
#define regGDC0_DOORBELL_ACCESS_EN_VF6_BASE_IDX 2
#define regGDC0_DOORBELL_ACCESS_EN_VF7 0x01fb
#define regGDC0_DOORBELL_ACCESS_EN_VF7_BASE_IDX 2
#define regGDC0_NGDC_CNDI_BUS_PORT_CTRL 0x01fc
#define regGDC0_NGDC_CNDI_BUS_PORT_CTRL_BASE_IDX 2
#define regGDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL 0x01fd
#define regGDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL 0x01cb
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1 0x01cc
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL 0x01cd
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1 0x01ce
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL 0x01cf
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1 0x01d0
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL 0x01d1
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1 0x01d2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL 0x01d3
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1 0x01d4
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL 0x01d5
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1 0x01d6
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL 0x01d7
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1 0x01d8
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL 0x01d9
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1 0x01da
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL 0x01db
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1 0x01dc
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL 0x01dd
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1 0x01de
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL 0x01df
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1 0x01e0
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL 0x01e1
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1 0x01e2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL 0x01e3
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1 0x01e4
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL 0x01e5
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1 0x01e6
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL 0x01e7
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1 0x01e8
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL 0x01e9
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1 0x01ea
#define regGDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1_BASE_IDX 2
#define regGDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG 0x01eb
#define regGDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX 2
#define regGDC_S2A0_NBIF_GFX_DOORBELL_STATUS 0x01ec
#define regGDC_S2A0_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 2
#define cfgBIF_CFG_DEV0_EPF0_VENDOR_ID 0x0000
#define cfgBIF_CFG_DEV0_EPF0_DEVICE_ID 0x0002
#define cfgBIF_CFG_DEV0_EPF0_COMMAND 0x0004
#define cfgBIF_CFG_DEV0_EPF0_STATUS 0x0006
#define cfgBIF_CFG_DEV0_EPF0_REVISION_ID 0x0008
#define cfgBIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x0009
#define cfgBIF_CFG_DEV0_EPF0_SUB_CLASS 0x000a
#define cfgBIF_CFG_DEV0_EPF0_BASE_CLASS 0x000b
#define cfgBIF_CFG_DEV0_EPF0_CACHE_LINE 0x000c
#define cfgBIF_CFG_DEV0_EPF0_LATENCY 0x000d
#define cfgBIF_CFG_DEV0_EPF0_HEADER 0x000e
#define cfgBIF_CFG_DEV0_EPF0_BIST 0x000f
#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_1 0x0010
#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_2 0x0014
#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_3 0x0018
#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_4 0x001c
#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_5 0x0020
#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_6 0x0024
#define cfgBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR 0x0028
#define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID 0x002c
#define cfgBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR 0x0030
#define cfgBIF_CFG_DEV0_EPF0_CAP_PTR 0x0034
#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_LINE 0x003c
#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_PIN 0x003d
#define cfgBIF_CFG_DEV0_EPF0_MIN_GRANT 0x003e
#define cfgBIF_CFG_DEV0_EPF0_MAX_LATENCY 0x003f
#define cfgVENDOR_CAP_LIST 0x0048
#define cfgADAPTER_ID_W 0x004c
#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP_LIST 0x0050
#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP 0x0052
#define cfgBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL 0x0054
#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST 0x0064
#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP 0x0066
#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP 0x0068
#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL 0x006c
#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS 0x006e
#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP2 0x0088
#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x008c
#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS2 0x008e
#define cfgBIF_CFG_DEV0_EPF0_MSI_CAP_LIST 0x00a0
#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL 0x00a2
#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO 0x00a4
#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI 0x00a8
#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA 0x00a8
#define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA 0x00aa
#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK 0x00ac
#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 0x00ac
#define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 0x00ae
#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK_64 0x00b0
#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING 0x00b0
#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING_64 0x00b4
#define cfgBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST 0x00c0
#define cfgBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL 0x00c2
#define cfgBIF_CFG_DEV0_EPF0_MSIX_TABLE 0x00c4
#define cfgBIF_CFG_DEV0_EPF0_MSIX_PBA 0x00c8
#define cfgBIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST 0x0600
#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604
#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS 0x0608
#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK 0x060c
#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY 0x0610
#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS 0x0614
#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK 0x0618
#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL 0x061c
#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 0x0620
#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 0x0624
#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 0x0628
#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 0x062c
#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG4 0x063c
#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 0x063c
#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG5 0x0640
#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 0x0640
#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG6 0x0644
#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 0x0644
#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG7 0x0648
#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 0x0648
#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG8 0x064c
#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG9 0x0650
#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG10 0x0654
#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG11 0x0658
#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG12 0x065c
#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG13 0x0660
#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0664
#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 0x0668
#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 0x066c
#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST 0x06dc
#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP 0x06e0
#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL 0x06e2
#define cfgBIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST 0x071c
#define cfgBIF_CFG_DEV0_EPF0_RTR_DATA1 0x0720
#define cfgBIF_CFG_DEV0_EPF0_RTR_DATA2 0x0724
#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST 0x0728
#define cfgPCIE_PWR_BUDGET_DATA_SELECT 0x072c
#define cfgPCIE_PWR_BUDGET_DATA 0x0730
#define cfgPCIE_PWR_BUDGET_CAP 0x0734
#define cfgPCIE_DPA_ENH_CAP_LIST 0x0738
#define cfgPCIE_DPA_CAP 0x073c
#define cfgPCIE_DPA_LATENCY_INDICATOR 0x0740
#define cfgPCIE_DPA_STATUS 0x0744
#define cfgPCIE_DPA_CNTL 0x0746
#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0748
#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0749
#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x074a
#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x074b
#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x074c
#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x074d
#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x074e
#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x074f
#define cfgPCIE_LTR_ENH_CAP_LIST 0x0768
#define cfgPCIE_LTR_CAP 0x076c
#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST 0x0770
#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP 0x0774
#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL 0x0776
#define cfgPCIE_BAR_ENH_CAP_LIST 0x0778
#define cfgPCIE_BAR1_CAP 0x077c
#define cfgPCIE_BAR1_CNTL 0x0780
#define cfgPCIE_BAR2_CAP 0x0784
#define cfgPCIE_BAR2_CNTL 0x0788
#define cfgPCIE_BAR3_CAP 0x078c
#define cfgPCIE_BAR3_CNTL 0x0790
#define cfgPCIE_BAR4_CAP 0x0794
#define cfgPCIE_BAR4_CNTL 0x0798
#define cfgPCIE_BAR5_CAP 0x079c
#define cfgPCIE_BAR5_CNTL 0x07a0
#define cfgPCIE_BAR6_CAP 0x07a4
#define cfgPCIE_BAR6_CNTL 0x07a8
#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST 0x07ac
#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CAP 0x07b0
#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL 0x07b2
#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST 0x07b4
#define cfgPCIE_PAGE_REQ_CNTL 0x07b8
#define cfgPCIE_PAGE_REQ_STATUS 0x07ba
#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x07bc
#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC 0x07c0
#define cfgPCIE_PASID_ENH_CAP_LIST 0x07c4
#define cfgPCIE_PASID_CAP 0x07c8
#define cfgPCIE_PASID_CNTL 0x07ca
#define cfgPCIE_SRIOV_ENH_CAP_LIST 0x07cc
#define cfgPCIE_SRIOV_CAP 0x07d0
#define cfgPCIE_SRIOV_CONTROL 0x07d4
#define cfgPCIE_SRIOV_STATUS 0x07d6
#define cfgPCIE_SRIOV_INITIAL_VFS 0x07d8
#define cfgPCIE_SRIOV_TOTAL_VFS 0x07da
#define cfgPCIE_SRIOV_NUM_VFS 0x07dc
#define cfgPCIE_SRIOV_FUNC_DEP_LINK 0x07de
#define cfgPCIE_SRIOV_FIRST_VF_OFFSET 0x07e0
#define cfgPCIE_SRIOV_VF_STRIDE 0x07e2
#define cfgPCIE_SRIOV_VF_DEVICE_ID 0x07e6
#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x07e8
#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE 0x07ec
#define cfgPCIE_SRIOV_VF_BASE_ADDR_0 0x07f0
#define cfgPCIE_SRIOV_VF_BASE_ADDR_1 0x07f4
#define cfgPCIE_SRIOV_VF_BASE_ADDR_2 0x07f8
#define cfgPCIE_SRIOV_VF_BASE_ADDR_3 0x07fc
#define cfgPCIE_SRIOV_VF_BASE_ADDR_4 0x0800
#define cfgPCIE_SRIOV_VF_BASE_ADDR_5 0x0804
#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x0808
#define cfgPCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x08e0
#define cfgPCIE_VF_RESIZE_BAR1_CAP 0x08e4
#define cfgPCIE_VF_RESIZE_BAR1_CNTL 0x08e8
#define cfgPCIE_VF_RESIZE_BAR2_CAP 0x08ec
#define cfgPCIE_VF_RESIZE_BAR2_CNTL 0x08f0
#define cfgPCIE_VF_RESIZE_BAR3_CAP 0x08f4
#define cfgPCIE_VF_RESIZE_BAR3_CNTL 0x08f8
#define cfgPCIE_VF_RESIZE_BAR4_CAP 0x08fc
#define cfgPCIE_VF_RESIZE_BAR4_CNTL 0x0900
#define cfgPCIE_VF_RESIZE_BAR5_CAP 0x0904
#define cfgPCIE_VF_RESIZE_BAR5_CNTL 0x0908
#define cfgPCIE_VF_RESIZE_BAR6_CAP 0x090c
#define cfgPCIE_VF_RESIZE_BAR6_CNTL 0x0910
#define cfgPCIE_DOE_ENH_CAP_LIST 0x0914
#define cfgPCIE_DOE_CAP 0x0918
#define cfgPCIE_DOE_CNTL 0x091c
#define cfgPCIE_DOE_STS 0x0920
#define cfgPCIE_DOE_WMBOX 0x0924
#define cfgPCIE_DOE_RMBOX 0x0928
#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x09ac
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x09b0
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x09b4
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x09b8
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x09bc
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x09c0
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x09c4
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x09c8
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x09cc
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x09d4
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x09dc
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x09e0
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0 0x0a04
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 0x0a08
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 0x0a0c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 0x0a10
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 0x0a14
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0 0x0a1c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1 0x0a20
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2 0x0a24
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3 0x0a28
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4 0x0a2c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5 0x0a30
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6 0x0a34
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7 0x0a38
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8 0x0a3c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0 0x0a4c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1 0x0a50
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2 0x0a54
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3 0x0a58
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4 0x0a5c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5 0x0a60
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6 0x0a64
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7 0x0a68
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8 0x0a6c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0 0x0a7c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1 0x0a80
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2 0x0a84
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3 0x0a88
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4 0x0a8c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5 0x0a90
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6 0x0a94
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7 0x0a98
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8 0x0a9c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0 0x0aac
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1 0x0ab0
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2 0x0ab4
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3 0x0ab8
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4 0x0abc
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5 0x0ac0
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6 0x0ac4
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7 0x0ac8
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8 0x0acc
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0 0x0adc
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1 0x0ae0
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2 0x0ae4
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3 0x0ae8
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4 0x0aec
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5 0x0af0
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6 0x0af4
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7 0x0af8
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8 0x0afc
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0 0x0b0c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1 0x0b10
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2 0x0b14
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3 0x0b18
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4 0x0b1c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5 0x0b20
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6 0x0b24
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7 0x0b28
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8 0x0b2c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0 0x0b3c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1 0x0b40
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2 0x0b44
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3 0x0b48
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4 0x0b4c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5 0x0b50
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6 0x0b54
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7 0x0b58
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8 0x0b5c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0 0x0b6c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1 0x0b70
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2 0x0b74
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3 0x0b78
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4 0x0b7c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5 0x0b80
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6 0x0b84
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7 0x0b88
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8 0x0b8c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0 0x0b9c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1 0x0ba0
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2 0x0ba4
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3 0x0ba8
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4 0x0bac
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5 0x0bb0
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6 0x0bb4
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7 0x0bb8
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8 0x0bbc
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0 0x0bcc
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1 0x0bd0
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2 0x0bd4
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3 0x0bd8
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4 0x0bdc
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5 0x0be0
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6 0x0be4
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7 0x0be8
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8 0x0bec
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0 0x0bfc
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1 0x0c00
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2 0x0c04
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3 0x0c08
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4 0x0c0c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5 0x0c10
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6 0x0c14
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7 0x0c18
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8 0x0c1c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0 0x0c2c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1 0x0c30
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2 0x0c34
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3 0x0c38
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4 0x0c3c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5 0x0c40
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6 0x0c44
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7 0x0c48
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8 0x0c4c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0 0x0c5c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1 0x0c60
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2 0x0c64
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3 0x0c68
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4 0x0c6c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5 0x0c70
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6 0x0c74
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7 0x0c78
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8 0x0c7c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0 0x0c8c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1 0x0c90
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2 0x0c94
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3 0x0c98
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4 0x0c9c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5 0x0ca0
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6 0x0ca4
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7 0x0ca8
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8 0x0cac
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0 0x0cbc
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1 0x0cc0
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2 0x0cc4
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3 0x0cc8
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4 0x0ccc
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5 0x0cd0
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6 0x0cd4
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7 0x0cd8
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8 0x0cdc
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0 0x0cec
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1 0x0cf0
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2 0x0cf4
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3 0x0cf8
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4 0x0cfc
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5 0x0d00
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6 0x0d04
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7 0x0d08
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8 0x0d0c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0 0x0d1c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1 0x0d20
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2 0x0d24
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3 0x0d28
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4 0x0d2c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5 0x0d30
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6 0x0d34
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7 0x0d38
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8 0x0d3c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0 0x0d4c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1 0x0d50
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2 0x0d54
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3 0x0d58
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4 0x0d5c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5 0x0d60
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6 0x0d64
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7 0x0d68
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8 0x0d6c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0 0x0d7c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1 0x0d80
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2 0x0d84
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3 0x0d88
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4 0x0d8c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5 0x0d90
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6 0x0d94
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7 0x0d98
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8 0x0d9c
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0 0x0dac
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1 0x0db0
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2 0x0db4
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3 0x0db8
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4 0x0dbc
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5 0x0dc0
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6 0x0dc4
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7 0x0dc8
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8 0x0dcc
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE 0x0ddc
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE 0x0de0
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE 0x0de4
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE 0x0de8
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS 0x0dec
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS 0x0df0
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS 0x0df4
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS 0x0df8
#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP 0x0070
#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL 0x0074
#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS 0x0076
#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP2 0x0090
#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL2 0x0094
#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS2 0x0096
#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 0x0108
#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 0x010c
#define cfgBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST 0x0110
#define cfgBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 0x0114
#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS 0x0118
#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL 0x011c
#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL 0x011e
#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0120
#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0122
#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0124
#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0126
#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0128
#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL 0x012a
#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL 0x012c
#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL 0x012e
#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0130
#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0132
#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0134
#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0136
#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0138
#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL 0x013a
#define cfgBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST 0x01b8
#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_16GT 0x01bc
#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT 0x01c0
#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT 0x01c4
#define cfgBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x01c8
#define cfgBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x01cc
#define cfgBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x01d0
#define cfgBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT 0x01d8
#define cfgBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT 0x01d9
#define cfgBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT 0x01da
#define cfgBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT 0x01db
#define cfgBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT 0x01dc
#define cfgBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT 0x01dd
#define cfgBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT 0x01de
#define cfgBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT 0x01df
#define cfgBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT 0x01e0
#define cfgBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT 0x01e1
#define cfgBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT 0x01e2
#define cfgBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT 0x01e3
#define cfgBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT 0x01e4
#define cfgBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT 0x01e5
#define cfgBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT 0x01e6
#define cfgBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT 0x01e7
#define cfgBIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST 0x01f8
#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_32GT 0x01fc
#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT 0x0200
#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT 0x0204
#define cfgBIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1 0x0208
#define cfgBIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA2 0x020c
#define cfgBIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1 0x0210
#define cfgBIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA2 0x0214
#define cfgBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_32GT 0x0218
#define cfgBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_32GT 0x0219
#define cfgBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_32GT 0x021a
#define cfgBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_32GT 0x021b
#define cfgBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_32GT 0x021c
#define cfgBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_32GT 0x021d
#define cfgBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_32GT 0x021e
#define cfgBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_32GT 0x021f
#define cfgBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_32GT 0x0220
#define cfgBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_32GT 0x0221
#define cfgBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_32GT 0x0222
#define cfgBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_32GT 0x0223
#define cfgBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_32GT 0x0224
#define cfgBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_32GT 0x0225
#define cfgBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_32GT 0x0226
#define cfgBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_32GT 0x0227
#define cfgBIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST 0x0238
#define cfgBIF_CFG_DEV0_EPF0_AP_CAP 0x023c
#define cfgBIF_CFG_DEV0_EPF0_AP_CNTL 0x0240
#define cfgBIF_CFG_DEV0_EPF0_AP_DATA1 0x0244
#define cfgBIF_CFG_DEV0_EPF0_AP_DATA2 0x0248
#define cfgBIF_CFG_DEV0_EPF0_AP_SEL_EN_MASK 0x024c
#define cfgBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST 0x0250
#define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP 0x0254
#define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS 0x0256
#define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL 0x0258
#define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS 0x025a
#define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL 0x025c
#define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS 0x025e
#define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL 0x0260
#define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS 0x0262
#define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL 0x0264
#define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS 0x0266
#define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL 0x0268
#define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS 0x026a
#define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL 0x026c
#define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS 0x026e
#define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL 0x0270
#define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS 0x0272
#define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL 0x0274
#define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS 0x0276
#define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL 0x0278
#define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS 0x027a
#define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL 0x027c
#define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS 0x027e
#define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL 0x0280
#define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS 0x0282
#define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL 0x0284
#define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS 0x0286
#define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL 0x0288
#define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS 0x028a
#define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL 0x028c
#define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS 0x028e
#define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL 0x0290
#define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS 0x0292
#define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL 0x0294
#define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS 0x0296
#define cfgBIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST 0x0400
#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST 0x0404
#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 0x0408
#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 0x040c
#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL 0x0410
#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS 0x0412
#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP 0x0414
#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL 0x0418
#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS 0x041e
#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP 0x0420
#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL 0x0424
#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS 0x042a
#define cfgBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST 0x0430
#define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP 0x0434
#define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS 0x0438
#define cfgBIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST 0x0e00
#define cfgBIF_CFG_DEV0_EPF0_IDE_CAP 0x0e04
#define cfgBIF_CFG_DEV0_EPF0_IDE_CNTL 0x0e08
#define cfgBIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL 0x0e0c
#define cfgBIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_STATUS 0x0e10
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CAP 0x0e14
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL 0x0e18
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_STATUS 0x0e1c
#define cfgBIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG1 0x0e20
#define cfgBIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2 0x0e24
#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1 0x0e28
#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG2 0x0e2c
#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG3 0x0e30
#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1 0x0e34
#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG2 0x0e38
#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG3 0x0e3c
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CAP 0x0e40
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL 0x0e44
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_STATUS 0x0e48
#define cfgBIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG1 0x0e4c
#define cfgBIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2 0x0e50
#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1 0x0e54
#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG2 0x0e58
#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG3 0x0e5c
#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1 0x0e60
#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG2 0x0e64
#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG3 0x0e68
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CAP 0x0e6c
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL 0x0e70
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_STATUS 0x0e74
#define cfgBIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG1 0x0e78
#define cfgBIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2 0x0e7c
#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1 0x0e80
#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG2 0x0e84
#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG3 0x0e88
#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1 0x0e8c
#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG2 0x0e90
#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG3 0x0e94
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CAP 0x0e98
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL 0x0e9c
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_STATUS 0x0ea0
#define cfgBIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG1 0x0ea4
#define cfgBIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2 0x0ea8
#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1 0x0eac
#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG2 0x0eb0
#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG3 0x0eb4
#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1 0x0eb8
#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG2 0x0ebc
#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG3 0x0ec0
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CAP 0x0ec4
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL 0x0ec8
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_STATUS 0x0ecc
#define cfgBIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG1 0x0ed0
#define cfgBIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2 0x0ed4
#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1 0x0ed8
#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG2 0x0edc
#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG3 0x0ee0
#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1 0x0ee4
#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG2 0x0ee8
#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG3 0x0eec
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CAP 0x0ef0
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL 0x0ef4
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_STATUS 0x0ef8
#define cfgBIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG1 0x0efc
#define cfgBIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2 0x0f00
#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1 0x0f04
#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG2 0x0f08
#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG3 0x0f0c
#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1 0x0f10
#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG2 0x0f14
#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG3 0x0f18
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CAP 0x0f1c
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL 0x0f20
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_STATUS 0x0f24
#define cfgBIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG1 0x0f28
#define cfgBIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2 0x0f2c
#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1 0x0f30
#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG2 0x0f34
#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG3 0x0f38
#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1 0x0f3c
#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG2 0x0f40
#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG3 0x0f44
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CAP 0x0f48
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL 0x0f4c
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_STATUS 0x0f50
#define cfgBIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG1 0x0f54
#define cfgBIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2 0x0f58
#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1 0x0f5c
#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG2 0x0f60
#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG3 0x0f64
#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1 0x0f68
#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG2 0x0f6c
#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG3 0x0f70
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CAP 0x0f74
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL 0x0f78
#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_STATUS 0x0f7c
#define cfgBIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG1 0x0f80
#define cfgBIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2 0x0f84
#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1 0x0f88
#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG2 0x0f8c
#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG3 0x0f90
#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1 0x0f94
#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG2 0x0f98
#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG3 0x0f9c
#define regBIF_CFG_DEV0_RC0_VENDOR_ID 0x0000
#define regBIF_CFG_DEV0_RC0_VENDOR_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_DEVICE_ID 0x0000
#define regBIF_CFG_DEV0_RC0_DEVICE_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_COMMAND 0x0001
#define regBIF_CFG_DEV0_RC0_COMMAND_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_STATUS 0x0001
#define regBIF_CFG_DEV0_RC0_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_REVISION_ID 0x0002
#define regBIF_CFG_DEV0_RC0_REVISION_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PROG_INTERFACE 0x0002
#define regBIF_CFG_DEV0_RC0_PROG_INTERFACE_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SUB_CLASS 0x0002
#define regBIF_CFG_DEV0_RC0_SUB_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_BASE_CLASS 0x0002
#define regBIF_CFG_DEV0_RC0_BASE_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_CACHE_LINE 0x0003
#define regBIF_CFG_DEV0_RC0_CACHE_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LATENCY 0x0003
#define regBIF_CFG_DEV0_RC0_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_HEADER 0x0003
#define regBIF_CFG_DEV0_RC0_HEADER_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_BIST 0x0003
#define regBIF_CFG_DEV0_RC0_BIST_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_BASE_ADDR_1 0x0004
#define regBIF_CFG_DEV0_RC0_BASE_ADDR_1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_BASE_ADDR_2 0x0005
#define regBIF_CFG_DEV0_RC0_BASE_ADDR_2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY 0x0006
#define regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT 0x0007
#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SECONDARY_STATUS 0x0007
#define regBIF_CFG_DEV0_RC0_SECONDARY_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT 0x0008
#define regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT 0x0009
#define regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER 0x000a
#define regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER 0x000b
#define regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI 0x000c
#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_CAP_PTR 0x000d
#define regBIF_CFG_DEV0_RC0_CAP_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR 0x000e
#define regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_INTERRUPT_LINE 0x000f
#define regBIF_CFG_DEV0_RC0_INTERRUPT_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_INTERRUPT_PIN 0x000f
#define regBIF_CFG_DEV0_RC0_INTERRUPT_PIN_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL 0x000f
#define regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL 0x0010
#define regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PMI_CAP_LIST 0x0014
#define regBIF_CFG_DEV0_RC0_PMI_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PMI_CAP 0x0014
#define regBIF_CFG_DEV0_RC0_PMI_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL 0x0015
#define regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST 0x0016
#define regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_CAP 0x0016
#define regBIF_CFG_DEV0_RC0_PCIE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_DEVICE_CAP 0x0017
#define regBIF_CFG_DEV0_RC0_DEVICE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL 0x0018
#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS 0x0018
#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LINK_CAP 0x0019
#define regBIF_CFG_DEV0_RC0_LINK_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LINK_CNTL 0x001a
#define regBIF_CFG_DEV0_RC0_LINK_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LINK_STATUS 0x001a
#define regBIF_CFG_DEV0_RC0_LINK_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SLOT_CAP 0x001b
#define regBIF_CFG_DEV0_RC0_SLOT_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SLOT_CNTL 0x001c
#define regBIF_CFG_DEV0_RC0_SLOT_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SLOT_STATUS 0x001c
#define regBIF_CFG_DEV0_RC0_SLOT_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_ROOT_CNTL 0x001d
#define regBIF_CFG_DEV0_RC0_ROOT_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_ROOT_CAP 0x001d
#define regBIF_CFG_DEV0_RC0_ROOT_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_ROOT_STATUS 0x001e
#define regBIF_CFG_DEV0_RC0_ROOT_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_DEVICE_CAP2 0x001f
#define regBIF_CFG_DEV0_RC0_DEVICE_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL2 0x0020
#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS2 0x0020
#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LINK_CAP2 0x0021
#define regBIF_CFG_DEV0_RC0_LINK_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LINK_CNTL2 0x0022
#define regBIF_CFG_DEV0_RC0_LINK_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LINK_STATUS2 0x0022
#define regBIF_CFG_DEV0_RC0_LINK_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SLOT_CAP2 0x0023
#define regBIF_CFG_DEV0_RC0_SLOT_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SLOT_CNTL2 0x0024
#define regBIF_CFG_DEV0_RC0_SLOT_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SLOT_STATUS2 0x0024
#define regBIF_CFG_DEV0_RC0_SLOT_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_MSI_CAP_LIST 0x0028
#define regBIF_CFG_DEV0_RC0_MSI_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL 0x0028
#define regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO 0x0029
#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI 0x002a
#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA 0x002a
#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA 0x002a
#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 0x002b
#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64 0x002b
#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SSID_CAP_LIST 0x0030
#define regBIF_CFG_DEV0_RC0_SSID_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SSID_CAP 0x0031
#define regBIF_CFG_DEV0_RC0_SSID_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0040
#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR 0x0041
#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 0x0042
#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 0x0043
#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0x0044
#define regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 0x0045
#define regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS 0x0046
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0x0047
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0x0047
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0048
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0048
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0049
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0049
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0x004a
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0x004a
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0x004b
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0x004b
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0x004c
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0x004c
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0x004d
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0x004d
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0x004e
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0x004e
#define regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST 0x006e
#define regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LINK_CAP_16GT 0x006f
#define regBIF_CFG_DEV0_RC0_LINK_CAP_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT 0x0070
#define regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT 0x0071
#define regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0072
#define regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0073
#define regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0074
#define regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT 0x0076
#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT 0x0076
#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT 0x0076
#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT 0x0076
#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT 0x0077
#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT 0x0077
#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT 0x0077
#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT 0x0077
#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT 0x0078
#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT 0x0078
#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT 0x0078
#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT 0x0078
#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT 0x0079
#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT 0x0079
#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT 0x0079
#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT 0x0079
#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST 0x007e
#define regBIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LINK_CAP_32GT 0x007f
#define regBIF_CFG_DEV0_RC0_LINK_CAP_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LINK_CNTL_32GT 0x0080
#define regBIF_CFG_DEV0_RC0_LINK_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LINK_STATUS_32GT 0x0081
#define regBIF_CFG_DEV0_RC0_LINK_STATUS_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1 0x0082
#define regBIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2 0x0083
#define regBIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1 0x0084
#define regBIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2 0x0085
#define regBIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT 0x0086
#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT 0x0086
#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT 0x0086
#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT 0x0086
#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT 0x0087
#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT 0x0087
#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT 0x0087
#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT 0x0087
#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT 0x0088
#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT 0x0088
#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT 0x0088
#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT 0x0088
#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT 0x0089
#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT 0x0089
#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT 0x0089
#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT 0x0089
#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST 0x008e
#define regBIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_AP_CAP 0x008f
#define regBIF_CFG_DEV0_RC0_AP_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_AP_CNTL 0x0090
#define regBIF_CFG_DEV0_RC0_AP_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_AP_DATA1 0x0091
#define regBIF_CFG_DEV0_RC0_AP_DATA1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_AP_DATA2 0x0092
#define regBIF_CFG_DEV0_RC0_AP_DATA2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_AP_SEL_EN_MASK 0x0093
#define regBIF_CFG_DEV0_RC0_AP_SEL_EN_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST 0x0094
#define regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP 0x0095
#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS 0x0095
#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL 0x0096
#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS 0x0096
#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL 0x0097
#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS 0x0097
#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL 0x0098
#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS 0x0098
#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL 0x0099
#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS 0x0099
#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL 0x009a
#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS 0x009a
#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL 0x009b
#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS 0x009b
#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL 0x009c
#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS 0x009c
#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL 0x009d
#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS 0x009d
#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL 0x009e
#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS 0x009e
#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL 0x009f
#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS 0x009f
#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL 0x00a0
#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS 0x00a0
#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL 0x00a1
#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS 0x00a1
#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL 0x00a2
#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS 0x00a2
#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL 0x00a3
#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS 0x00a3
#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL 0x00a4
#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS 0x00a4
#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL 0x00a5
#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS 0x00a5
#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST 0x0100
#define regBIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST 0x0101
#define regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 0x0102
#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 0x0103
#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL 0x0104
#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS 0x0104
#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP 0x0105
#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL 0x0106
#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS 0x0107
#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP 0x0108
#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL 0x0109
#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS 0x010a
#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST 0x010c
#define regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP 0x010d
#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS 0x010e
#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST 0x0180
#define regBIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0181
#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS 0x0182
#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK 0x0183
#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY 0x0184
#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS 0x0185
#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK 0x0186
#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL 0x0187
#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 0x0188
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 0x0189
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 0x018a
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 0x018b
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD 0x018c
#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS 0x018d
#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID 0x018e
#define regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG4 0x018f
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG4_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 0x018f
#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG5 0x0190
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG5_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 0x0190
#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG6 0x0191
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG6_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 0x0191
#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG7 0x0192
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG7_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 0x0192
#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG8 0x0193
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG8_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG9 0x0194
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG9_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG10 0x0195
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG10_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG11 0x0196
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG11_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG12 0x0197
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG12_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG13 0x0198
#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG13_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0199
#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 0x019a
#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 0x019b
#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST 0x01b7
#define regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP 0x01b8
#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL 0x01b8
#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST 0x01c7
#define regBIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_RTR_DATA1 0x01c8
#define regBIF_CFG_DEV0_RC0_RTR_DATA1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_RTR_DATA2 0x01c9
#define regBIF_CFG_DEV0_RC0_RTR_DATA2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST 0x0380
#define regBIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_CAP 0x0381
#define regBIF_CFG_DEV0_RC0_IDE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_CNTL 0x0382
#define regBIF_CFG_DEV0_RC0_IDE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL 0x0383
#define regBIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS 0x0384
#define regBIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CAP 0x0385
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL 0x0386
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS 0x0387
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG1 0x0388
#define regBIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2 0x0389
#define regBIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1 0x038a
#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG2 0x038b
#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG3 0x038c
#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1 0x038d
#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG2 0x038e
#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG3 0x038f
#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CAP 0x0390
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL 0x0391
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS 0x0392
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG1 0x0393
#define regBIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2 0x0394
#define regBIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1 0x0395
#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG2 0x0396
#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG3 0x0397
#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1 0x0398
#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG2 0x0399
#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG3 0x039a
#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CAP 0x039b
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL 0x039c
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS 0x039d
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG1 0x039e
#define regBIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2 0x039f
#define regBIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1 0x03a0
#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG2 0x03a1
#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG3 0x03a2
#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1 0x03a3
#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG2 0x03a4
#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG3 0x03a5
#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CAP 0x03a6
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL 0x03a7
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS 0x03a8
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG1 0x03a9
#define regBIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2 0x03aa
#define regBIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1 0x03ab
#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG2 0x03ac
#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG3 0x03ad
#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1 0x03ae
#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG2 0x03af
#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG3 0x03b0
#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CAP 0x03b1
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL 0x03b2
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS 0x03b3
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG1 0x03b4
#define regBIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2 0x03b5
#define regBIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1 0x03b6
#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG2 0x03b7
#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG3 0x03b8
#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1 0x03b9
#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG2 0x03ba
#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG3 0x03bb
#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CAP 0x03bc
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL 0x03bd
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS 0x03be
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG1 0x03bf
#define regBIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2 0x03c0
#define regBIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1 0x03c1
#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG2 0x03c2
#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG3 0x03c3
#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1 0x03c4
#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG2 0x03c5
#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG3 0x03c6
#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CAP 0x03c7
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL 0x03c8
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS 0x03c9
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG1 0x03ca
#define regBIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2 0x03cb
#define regBIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1 0x03cc
#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG2 0x03cd
#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG3 0x03ce
#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1 0x03cf
#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG2 0x03d0
#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG3 0x03d1
#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CAP 0x03d2
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL 0x03d3
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS 0x03d4
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG1 0x03d5
#define regBIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2 0x03d6
#define regBIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1 0x03d7
#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG2 0x03d8
#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG3 0x03d9
#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1 0x03da
#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG2 0x03db
#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG3 0x03dc
#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CAP 0x03dd
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL 0x03de
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS 0x03df
#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG1 0x03e0
#define regBIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2 0x03e1
#define regBIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1 0x03e2
#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG2 0x03e3
#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG3 0x03e4
#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1 0x03e5
#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG2 0x03e6
#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG3 0x03e7
#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0x10000
#define regBIF_CFG_DEV0_EPF0_0_VENDOR_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0x10000
#define regBIF_CFG_DEV0_EPF0_0_DEVICE_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_COMMAND 0x10001
#define regBIF_CFG_DEV0_EPF0_0_COMMAND_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_STATUS 0x10001
#define regBIF_CFG_DEV0_EPF0_0_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_REVISION_ID 0x10002
#define regBIF_CFG_DEV0_EPF0_0_REVISION_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0x10002
#define regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0x10002
#define regBIF_CFG_DEV0_EPF0_0_SUB_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0x10002
#define regBIF_CFG_DEV0_EPF0_0_BASE_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0x10003
#define regBIF_CFG_DEV0_EPF0_0_CACHE_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LATENCY 0x10003
#define regBIF_CFG_DEV0_EPF0_0_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_HEADER 0x10003
#define regBIF_CFG_DEV0_EPF0_0_HEADER_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_BIST 0x10003
#define regBIF_CFG_DEV0_EPF0_0_BIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0x10004
#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0x10005
#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0x10006
#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0x10007
#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0x10008
#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0x10009
#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR 0x1000a
#define regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0x1000b
#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0x1000c
#define regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_CAP_PTR 0x1000d
#define regBIF_CFG_DEV0_EPF0_0_CAP_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0x1000f
#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0x1000f
#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0x1000f
#define regBIF_CFG_DEV0_EPF0_0_MIN_GRANT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0x1000f
#define regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0x10012
#define regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0x10013
#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0x10014
#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP 0x10014
#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0x10015
#define regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0x10019
#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0x10019
#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0x1001a
#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0x1001b
#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0x1001b
#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0x10022
#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0x10023
#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0x10023
#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0x10028
#define regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0x10028
#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0x10029
#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0x1002a
#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0x1002a
#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA 0x1002a
#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK 0x1002b
#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0x1002b
#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64 0x1002b
#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0x1002c
#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0x1002c
#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0x1002d
#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0x10030
#define regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0x10030
#define regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0x10031
#define regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0x10032
#define regBIF_CFG_DEV0_EPF0_0_MSIX_PBA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST 0x10180
#define regBIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x10182
#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0x10183
#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x10184
#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0x10185
#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0x10186
#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x10187
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0x10188
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0x10189
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0x1018a
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0x1018b
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG4 0x1018f
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x1018f
#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG5 0x10190
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x10190
#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG6 0x10191
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x10191
#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG7 0x10192
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x10192
#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG8 0x10193
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG9 0x10194
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG9_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG10 0x10195
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG10_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG11 0x10196
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG11_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG12 0x10197
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG12_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG13 0x10198
#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG13_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x10199
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0x1019a
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0x1019b
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x101b7
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0x101b8
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0x101b8
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST 0x101c7
#define regBIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_RTR_DATA1 0x101c8
#define regBIF_CFG_DEV0_EPF0_0_RTR_DATA1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_RTR_DATA2 0x101c9
#define regBIF_CFG_DEV0_EPF0_0_RTR_DATA2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x101ca
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x101cb
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0x101cc
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0x101cd
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x101ce
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0x101cf
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x101d0
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0x101d1
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0x101d1
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x101d2
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x101d2
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x101d2
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x101d2
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x101d3
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x101d3
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x101d3
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x101d3
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x101da
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0x101db
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x101dc
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0x101dd
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0x101dd
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x101de
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0x101df
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0x101e0
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0x101e1
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0x101e2
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0x101e3
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0x101e4
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0x101e5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0x101e6
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0x101e7
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0x101e8
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0x101e9
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0x101ea
#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST 0x101eb
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP 0x101ec
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL 0x101ec
#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x101ed
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL 0x101ee
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS 0x101ee
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x101ef
#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x101f0
#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0x101f1
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0x101f2
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0x101f2
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0x101f3
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0x101f4
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0x101f5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0x101f5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0x101f6
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0x101f6
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0x101f7
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0x101f7
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x101f8
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0x101f8
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0x101f9
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x101fa
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x101fb
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x101fc
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x101fd
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x101fe
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x101ff
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x10200
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x10201
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x10202
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x10238
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP 0x10239
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL 0x1023a
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP 0x1023b
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL 0x1023c
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP 0x1023d
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL 0x1023e
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP 0x1023f
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL 0x10240
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP 0x10241
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL 0x10242
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP 0x10243
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL 0x10244
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST 0x10245
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP 0x10246
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL 0x10247
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS 0x10248
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_WMBOX 0x10249
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_WMBOX_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_RMBOX 0x1024a
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_RMBOX_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x1026b
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x1026c
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x1026d
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x1026e
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x1026f
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x10270
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x10271
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x10272
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x10273
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x10275
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x10277
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x10278
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0 0x10281
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 0x10282
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 0x10283
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 0x10284
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 0x10285
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0 0x10287
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1 0x10288
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2 0x10289
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3 0x1028a
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4 0x1028b
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5 0x1028c
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6 0x1028d
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7 0x1028e
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8 0x1028f
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0 0x10293
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1 0x10294
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2 0x10295
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3 0x10296
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4 0x10297
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5 0x10298
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6 0x10299
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7 0x1029a
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8 0x1029b
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0 0x1029f
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1 0x102a0
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2 0x102a1
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3 0x102a2
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4 0x102a3
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5 0x102a4
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6 0x102a5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7 0x102a6
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8 0x102a7
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0 0x102ab
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1 0x102ac
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2 0x102ad
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3 0x102ae
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4 0x102af
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5 0x102b0
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6 0x102b1
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7 0x102b2
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8 0x102b3
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0 0x102b7
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1 0x102b8
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2 0x102b9
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3 0x102ba
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4 0x102bb
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5 0x102bc
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6 0x102bd
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7 0x102be
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8 0x102bf
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0 0x102c3
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1 0x102c4
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2 0x102c5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3 0x102c6
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4 0x102c7
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5 0x102c8
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6 0x102c9
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7 0x102ca
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8 0x102cb
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0 0x102cf
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1 0x102d0
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2 0x102d1
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3 0x102d2
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4 0x102d3
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5 0x102d4
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6 0x102d5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7 0x102d6
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8 0x102d7
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0 0x102db
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1 0x102dc
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2 0x102dd
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3 0x102de
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4 0x102df
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5 0x102e0
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6 0x102e1
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7 0x102e2
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8 0x102e3
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0 0x102e7
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1 0x102e8
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2 0x102e9
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3 0x102ea
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4 0x102eb
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5 0x102ec
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6 0x102ed
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7 0x102ee
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8 0x102ef
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0 0x102f3
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1 0x102f4
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2 0x102f5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3 0x102f6
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4 0x102f7
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5 0x102f8
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6 0x102f9
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7 0x102fa
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8 0x102fb
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0 0x102ff
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1 0x10300
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2 0x10301
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3 0x10302
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4 0x10303
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5 0x10304
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6 0x10305
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7 0x10306
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8 0x10307
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0 0x1030b
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1 0x1030c
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2 0x1030d
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3 0x1030e
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4 0x1030f
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5 0x10310
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6 0x10311
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7 0x10312
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8 0x10313
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0 0x10317
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1 0x10318
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2 0x10319
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3 0x1031a
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4 0x1031b
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5 0x1031c
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6 0x1031d
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7 0x1031e
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8 0x1031f
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0 0x10323
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1 0x10324
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2 0x10325
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3 0x10326
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4 0x10327
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5 0x10328
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6 0x10329
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7 0x1032a
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8 0x1032b
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0 0x1032f
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1 0x10330
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2 0x10331
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3 0x10332
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4 0x10333
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5 0x10334
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6 0x10335
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7 0x10336
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8 0x10337
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0 0x1033b
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1 0x1033c
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2 0x1033d
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3 0x1033e
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4 0x1033f
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5 0x10340
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6 0x10341
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7 0x10342
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8 0x10343
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0 0x10347
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1 0x10348
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2 0x10349
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3 0x1034a
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4 0x1034b
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5 0x1034c
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6 0x1034d
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7 0x1034e
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8 0x1034f
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0 0x10353
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1 0x10354
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2 0x10355
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3 0x10356
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4 0x10357
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5 0x10358
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6 0x10359
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7 0x1035a
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8 0x1035b
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0 0x1035f
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1 0x10360
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2 0x10361
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3 0x10362
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4 0x10363
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5 0x10364
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6 0x10365
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7 0x10366
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8 0x10367
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0 0x1036b
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1 0x1036c
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2 0x1036d
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3 0x1036e
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4 0x1036f
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5 0x10370
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6 0x10371
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7 0x10372
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8 0x10373
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE 0x10377
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE 0x10378
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE 0x10379
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE 0x1037a
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS 0x1037b
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS 0x1037c
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS 0x1037d
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS 0x1037e
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP 0x1001c
#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0x1001d
#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0x1001d
#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0x10024
#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0x10025
#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0x10025
#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x10041
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x10042
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x10043
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x10044
#define regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0x10045
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0x10046
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x10047
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x10047
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x10048
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x10048
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x10049
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x10049
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x1004a
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x1004a
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x1004b
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x1004b
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x1004c
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x1004c
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x1004d
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x1004d
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x1004e
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x1004e
#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x1006e
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT 0x1006f
#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT 0x10070
#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT 0x10071
#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x10072
#define regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x10073
#define regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x10074
#define regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0x10076
#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0x10076
#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0x10076
#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0x10076
#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0x10077
#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0x10077
#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0x10077
#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0x10077
#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0x10078
#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0x10078
#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0x10078
#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0x10078
#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0x10079
#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0x10079
#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0x10079
#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0x10079
#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST 0x1007e
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT 0x1007f
#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT 0x10080
#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT 0x10081
#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1 0x10082
#define regBIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2 0x10083
#define regBIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1 0x10084
#define regBIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2 0x10085
#define regBIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT 0x10086
#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT 0x10086
#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT 0x10086
#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT 0x10086
#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT 0x10087
#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT 0x10087
#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT 0x10087
#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT 0x10087
#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT 0x10088
#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT 0x10088
#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT 0x10088
#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT 0x10088
#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT 0x10089
#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT 0x10089
#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT 0x10089
#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT 0x10089
#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST 0x1008e
#define regBIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_AP_CAP 0x1008f
#define regBIF_CFG_DEV0_EPF0_0_AP_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_AP_CNTL 0x10090
#define regBIF_CFG_DEV0_EPF0_0_AP_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_AP_DATA1 0x10091
#define regBIF_CFG_DEV0_EPF0_0_AP_DATA1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_AP_DATA2 0x10092
#define regBIF_CFG_DEV0_EPF0_0_AP_DATA2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK 0x10093
#define regBIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST 0x10094
#define regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP 0x10095
#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS 0x10095
#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0x10096
#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0x10096
#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0x10097
#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0x10097
#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0x10098
#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0x10098
#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0x10099
#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0x10099
#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0x1009a
#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0x1009a
#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0x1009b
#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0x1009b
#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0x1009c
#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0x1009c
#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0x1009d
#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0x1009d
#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0x1009e
#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0x1009e
#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0x1009f
#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0x1009f
#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0x100a0
#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0x100a0
#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0x100a1
#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0x100a1
#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0x100a2
#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0x100a2
#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0x100a3
#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0x100a3
#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0x100a4
#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0x100a4
#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0x100a5
#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0x100a5
#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST 0x10100
#define regBIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x10101
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x10102
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x10103
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0x10104
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0x10104
#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x10105
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x10106
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x10107
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x10108
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x10109
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x1010a
#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0x1010c
#define regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP 0x1010d
#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS 0x1010e
#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST 0x10380
#define regBIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_CAP 0x10381
#define regBIF_CFG_DEV0_EPF0_0_IDE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_CNTL 0x10382
#define regBIF_CFG_DEV0_EPF0_0_IDE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL 0x10383
#define regBIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS 0x10384
#define regBIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CAP 0x10385
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL 0x10386
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS 0x10387
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG1 0x10388
#define regBIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2 0x10389
#define regBIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1 0x1038a
#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG2 0x1038b
#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG3 0x1038c
#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1 0x1038d
#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG2 0x1038e
#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG3 0x1038f
#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CAP 0x10390
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL 0x10391
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS 0x10392
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG1 0x10393
#define regBIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2 0x10394
#define regBIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1 0x10395
#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG2 0x10396
#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG3 0x10397
#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1 0x10398
#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG2 0x10399
#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG3 0x1039a
#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CAP 0x1039b
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL 0x1039c
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS 0x1039d
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG1 0x1039e
#define regBIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2 0x1039f
#define regBIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1 0x103a0
#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG2 0x103a1
#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG3 0x103a2
#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1 0x103a3
#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG2 0x103a4
#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG3 0x103a5
#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CAP 0x103a6
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL 0x103a7
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS 0x103a8
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG1 0x103a9
#define regBIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2 0x103aa
#define regBIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1 0x103ab
#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG2 0x103ac
#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG3 0x103ad
#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1 0x103ae
#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG2 0x103af
#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG3 0x103b0
#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CAP 0x103b1
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL 0x103b2
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS 0x103b3
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG1 0x103b4
#define regBIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2 0x103b5
#define regBIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1 0x103b6
#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG2 0x103b7
#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG3 0x103b8
#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1 0x103b9
#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG2 0x103ba
#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG3 0x103bb
#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CAP 0x103bc
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL 0x103bd
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS 0x103be
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG1 0x103bf
#define regBIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2 0x103c0
#define regBIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1 0x103c1
#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG2 0x103c2
#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG3 0x103c3
#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1 0x103c4
#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG2 0x103c5
#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG3 0x103c6
#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CAP 0x103c7
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL 0x103c8
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS 0x103c9
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG1 0x103ca
#define regBIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2 0x103cb
#define regBIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1 0x103cc
#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG2 0x103cd
#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG3 0x103ce
#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1 0x103cf
#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG2 0x103d0
#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG3 0x103d1
#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CAP 0x103d2
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL 0x103d3
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS 0x103d4
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG1 0x103d5
#define regBIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2 0x103d6
#define regBIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1 0x103d7
#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG2 0x103d8
#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG3 0x103d9
#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1 0x103da
#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG2 0x103db
#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG3 0x103dc
#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CAP 0x103dd
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL 0x103de
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS 0x103df
#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG1 0x103e0
#define regBIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2 0x103e1
#define regBIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1 0x103e2
#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG2 0x103e3
#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG3 0x103e4
#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1 0x103e5
#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG2 0x103e6
#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG3 0x103e7
#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID 0x10000
#define regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID 0x10000
#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_COMMAND 0x10001
#define regBIF_CFG_DEV0_EPF0_VF0_COMMAND_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_STATUS 0x10001
#define regBIF_CFG_DEV0_EPF0_VF0_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID 0x10002
#define regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE 0x10002
#define regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS 0x10002
#define regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS 0x10002
#define regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE 0x10003
#define regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_LATENCY 0x10003
#define regBIF_CFG_DEV0_EPF0_VF0_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_HEADER 0x10003
#define regBIF_CFG_DEV0_EPF0_VF0_HEADER_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_BIST 0x10003
#define regBIF_CFG_DEV0_EPF0_VF0_BIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 0x10004
#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 0x10005
#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 0x10006
#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 0x10007
#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 0x10008
#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 0x10009
#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR 0x1000a
#define regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID 0x1000b
#define regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR 0x1000c
#define regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR 0x1000d
#define regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST 0x10019
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP 0x10019
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP 0x1001a
#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL 0x1001b
#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS 0x1001b
#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP 0x1001c
#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL 0x1001d
#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS 0x1001d
#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 0x10022
#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 0x10023
#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 0x10023
#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 0x10024
#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 0x10025
#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 0x10025
#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST 0x10028
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL 0x10028
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO 0x10029
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 0x1002c
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING 0x1002c
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 0x1002d
#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST 0x10030
#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL 0x10030
#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE 0x10031
#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA 0x10032
#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x10041
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 0x10042
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 0x10043
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3 0x100b7
#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3 0x100b8
#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3 0x100b9
#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST 0x10100
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST 0x10180
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS 0x10182
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK 0x10183
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY 0x10184
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS 0x10185
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK 0x10186
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL 0x10187
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 0x10188
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 0x10189
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 0x1018a
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 0x1018b
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG4 0x1018f
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 0x1018f
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG5 0x10190
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 0x10190
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG6 0x10191
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 0x10191
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG7 0x10192
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 0x10192
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG8 0x10193
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG9 0x10194
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG9_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG10 0x10195
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG10_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG11 0x10196
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG11_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG12 0x10197
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG12_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG13 0x10198
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG13_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST 0x101c7
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_RTR_DATA1 0x101c8
#define regBIF_CFG_DEV0_EPF0_VF0_RTR_DATA1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_RTR_DATA2 0x101c9
#define regBIF_CFG_DEV0_EPF0_VF0_RTR_DATA2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST 0x101dc
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP 0x101dd
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL 0x101dd
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST 0x101eb
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP 0x101ec
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL 0x101ec
#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID 0x10000
#define regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID 0x10000
#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_COMMAND 0x10001
#define regBIF_CFG_DEV0_EPF0_VF1_COMMAND_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_STATUS 0x10001
#define regBIF_CFG_DEV0_EPF0_VF1_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID 0x10002
#define regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE 0x10002
#define regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS 0x10002
#define regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS 0x10002
#define regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE 0x10003
#define regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_LATENCY 0x10003
#define regBIF_CFG_DEV0_EPF0_VF1_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_HEADER 0x10003
#define regBIF_CFG_DEV0_EPF0_VF1_HEADER_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_BIST 0x10003
#define regBIF_CFG_DEV0_EPF0_VF1_BIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 0x10004
#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 0x10005
#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 0x10006
#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 0x10007
#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 0x10008
#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 0x10009
#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR 0x1000a
#define regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID 0x1000b
#define regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR 0x1000c
#define regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR 0x1000d
#define regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST 0x10019
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP 0x10019
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP 0x1001a
#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL 0x1001b
#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS 0x1001b
#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP 0x1001c
#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL 0x1001d
#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS 0x1001d
#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 0x10022
#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 0x10023
#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 0x10023
#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 0x10024
#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 0x10025
#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 0x10025
#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST 0x10028
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL 0x10028
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO 0x10029
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 0x1002c
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING 0x1002c
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 0x1002d
#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST 0x10030
#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL 0x10030
#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE 0x10031
#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA 0x10032
#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR 0x10041
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 0x10042
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 0x10043
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3 0x100b7
#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3 0x100b8
#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3 0x100b9
#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST 0x10100
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST 0x10180
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS 0x10182
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK 0x10183
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY 0x10184
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS 0x10185
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK 0x10186
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL 0x10187
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 0x10188
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 0x10189
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 0x1018a
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 0x1018b
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG4 0x1018f
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 0x1018f
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG5 0x10190
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 0x10190
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG6 0x10191
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 0x10191
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG7 0x10192
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 0x10192
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG8 0x10193
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG9 0x10194
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG9_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG10 0x10195
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG10_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG11 0x10196
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG11_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG12 0x10197
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG12_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG13 0x10198
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG13_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST 0x101c7
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_RTR_DATA1 0x101c8
#define regBIF_CFG_DEV0_EPF0_VF1_RTR_DATA1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_RTR_DATA2 0x101c9
#define regBIF_CFG_DEV0_EPF0_VF1_RTR_DATA2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST 0x101dc
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP 0x101dd
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL 0x101dd
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST 0x101eb
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP 0x101ec
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL 0x101ec
#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID 0x10000
#define regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID 0x10000
#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_COMMAND 0x10001
#define regBIF_CFG_DEV0_EPF0_VF2_COMMAND_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_STATUS 0x10001
#define regBIF_CFG_DEV0_EPF0_VF2_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID 0x10002
#define regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE 0x10002
#define regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS 0x10002
#define regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS 0x10002
#define regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE 0x10003
#define regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_LATENCY 0x10003
#define regBIF_CFG_DEV0_EPF0_VF2_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_HEADER 0x10003
#define regBIF_CFG_DEV0_EPF0_VF2_HEADER_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_BIST 0x10003
#define regBIF_CFG_DEV0_EPF0_VF2_BIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 0x10004
#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 0x10005
#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 0x10006
#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 0x10007
#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 0x10008
#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 0x10009
#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR 0x1000a
#define regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID 0x1000b
#define regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR 0x1000c
#define regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR 0x1000d
#define regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST 0x10019
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP 0x10019
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP 0x1001a
#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL 0x1001b
#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS 0x1001b
#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP 0x1001c
#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL 0x1001d
#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS 0x1001d
#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 0x10022
#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 0x10023
#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 0x10023
#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 0x10024
#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 0x10025
#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 0x10025
#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST 0x10028
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL 0x10028
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO 0x10029
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 0x1002c
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING 0x1002c
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 0x1002d
#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST 0x10030
#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL 0x10030
#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE 0x10031
#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA 0x10032
#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR 0x10041
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 0x10042
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 0x10043
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3 0x100b7
#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3 0x100b8
#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3 0x100b9
#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST 0x10100
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST 0x10180
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS 0x10182
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK 0x10183
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY 0x10184
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS 0x10185
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK 0x10186
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL 0x10187
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 0x10188
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 0x10189
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 0x1018a
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 0x1018b
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG4 0x1018f
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 0x1018f
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG5 0x10190
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 0x10190
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG6 0x10191
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 0x10191
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG7 0x10192
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 0x10192
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG8 0x10193
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG9 0x10194
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG9_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG10 0x10195
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG10_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG11 0x10196
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG11_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG12 0x10197
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG12_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG13 0x10198
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG13_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST 0x101c7
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_RTR_DATA1 0x101c8
#define regBIF_CFG_DEV0_EPF0_VF2_RTR_DATA1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_RTR_DATA2 0x101c9
#define regBIF_CFG_DEV0_EPF0_VF2_RTR_DATA2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST 0x101dc
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP 0x101dd
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL 0x101dd
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST 0x101eb
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP 0x101ec
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL 0x101ec
#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID 0x10000
#define regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID 0x10000
#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_COMMAND 0x10001
#define regBIF_CFG_DEV0_EPF0_VF3_COMMAND_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_STATUS 0x10001
#define regBIF_CFG_DEV0_EPF0_VF3_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID 0x10002
#define regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE 0x10002
#define regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS 0x10002
#define regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS 0x10002
#define regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE 0x10003
#define regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_LATENCY 0x10003
#define regBIF_CFG_DEV0_EPF0_VF3_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_HEADER 0x10003
#define regBIF_CFG_DEV0_EPF0_VF3_HEADER_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_BIST 0x10003
#define regBIF_CFG_DEV0_EPF0_VF3_BIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 0x10004
#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 0x10005
#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 0x10006
#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 0x10007
#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 0x10008
#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 0x10009
#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR 0x1000a
#define regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID 0x1000b
#define regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR 0x1000c
#define regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR 0x1000d
#define regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST 0x10019
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP 0x10019
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP 0x1001a
#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL 0x1001b
#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS 0x1001b
#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP 0x1001c
#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL 0x1001d
#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS 0x1001d
#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 0x10022
#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 0x10023
#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 0x10023
#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 0x10024
#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 0x10025
#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 0x10025
#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST 0x10028
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL 0x10028
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO 0x10029
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 0x1002c
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING 0x1002c
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 0x1002d
#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST 0x10030
#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL 0x10030
#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE 0x10031
#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA 0x10032
#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR 0x10041
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 0x10042
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 0x10043
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3 0x100b7
#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3 0x100b8
#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3 0x100b9
#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST 0x10100
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST 0x10180
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS 0x10182
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK 0x10183
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY 0x10184
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS 0x10185
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK 0x10186
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL 0x10187
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 0x10188
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 0x10189
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 0x1018a
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 0x1018b
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG4 0x1018f
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 0x1018f
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG5 0x10190
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 0x10190
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG6 0x10191
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 0x10191
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG7 0x10192
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 0x10192
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG8 0x10193
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG9 0x10194
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG9_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG10 0x10195
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG10_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG11 0x10196
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG11_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG12 0x10197
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG12_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG13 0x10198
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG13_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST 0x101c7
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_RTR_DATA1 0x101c8
#define regBIF_CFG_DEV0_EPF0_VF3_RTR_DATA1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_RTR_DATA2 0x101c9
#define regBIF_CFG_DEV0_EPF0_VF3_RTR_DATA2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST 0x101dc
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP 0x101dd
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL 0x101dd
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST 0x101eb
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP 0x101ec
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL 0x101ec
#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID 0x10000
#define regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID 0x10000
#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_COMMAND 0x10001
#define regBIF_CFG_DEV0_EPF0_VF4_COMMAND_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_STATUS 0x10001
#define regBIF_CFG_DEV0_EPF0_VF4_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID 0x10002
#define regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE 0x10002
#define regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS 0x10002
#define regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS 0x10002
#define regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE 0x10003
#define regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_LATENCY 0x10003
#define regBIF_CFG_DEV0_EPF0_VF4_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_HEADER 0x10003
#define regBIF_CFG_DEV0_EPF0_VF4_HEADER_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_BIST 0x10003
#define regBIF_CFG_DEV0_EPF0_VF4_BIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 0x10004
#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 0x10005
#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 0x10006
#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 0x10007
#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 0x10008
#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 0x10009
#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR 0x1000a
#define regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID 0x1000b
#define regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR 0x1000c
#define regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR 0x1000d
#define regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST 0x10019
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP 0x10019
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP 0x1001a
#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL 0x1001b
#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS 0x1001b
#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP 0x1001c
#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL 0x1001d
#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS 0x1001d
#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 0x10022
#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 0x10023
#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 0x10023
#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 0x10024
#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 0x10025
#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 0x10025
#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST 0x10028
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL 0x10028
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO 0x10029
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 0x1002c
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING 0x1002c
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 0x1002d
#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST 0x10030
#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL 0x10030
#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE 0x10031
#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA 0x10032
#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR 0x10041
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 0x10042
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 0x10043
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3 0x100b7
#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3 0x100b8
#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3 0x100b9
#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST 0x10100
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST 0x10180
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS 0x10182
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK 0x10183
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY 0x10184
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS 0x10185
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK 0x10186
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL 0x10187
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 0x10188
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 0x10189
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 0x1018a
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 0x1018b
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG4 0x1018f
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 0x1018f
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG5 0x10190
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 0x10190
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG6 0x10191
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 0x10191
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG7 0x10192
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 0x10192
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG8 0x10193
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG9 0x10194
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG9_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG10 0x10195
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG10_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG11 0x10196
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG11_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG12 0x10197
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG12_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG13 0x10198
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG13_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST 0x101c7
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_RTR_DATA1 0x101c8
#define regBIF_CFG_DEV0_EPF0_VF4_RTR_DATA1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_RTR_DATA2 0x101c9
#define regBIF_CFG_DEV0_EPF0_VF4_RTR_DATA2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST 0x101dc
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP 0x101dd
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL 0x101dd
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST 0x101eb
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP 0x101ec
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL 0x101ec
#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID 0x10000
#define regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID 0x10000
#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_COMMAND 0x10001
#define regBIF_CFG_DEV0_EPF0_VF5_COMMAND_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_STATUS 0x10001
#define regBIF_CFG_DEV0_EPF0_VF5_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID 0x10002
#define regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE 0x10002
#define regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS 0x10002
#define regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS 0x10002
#define regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE 0x10003
#define regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_LATENCY 0x10003
#define regBIF_CFG_DEV0_EPF0_VF5_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_HEADER 0x10003
#define regBIF_CFG_DEV0_EPF0_VF5_HEADER_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_BIST 0x10003
#define regBIF_CFG_DEV0_EPF0_VF5_BIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 0x10004
#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 0x10005
#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 0x10006
#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 0x10007
#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 0x10008
#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 0x10009
#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR 0x1000a
#define regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID 0x1000b
#define regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR 0x1000c
#define regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR 0x1000d
#define regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST 0x10019
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP 0x10019
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP 0x1001a
#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL 0x1001b
#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS 0x1001b
#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP 0x1001c
#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL 0x1001d
#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS 0x1001d
#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 0x10022
#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 0x10023
#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 0x10023
#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 0x10024
#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 0x10025
#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 0x10025
#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST 0x10028
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL 0x10028
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO 0x10029
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 0x1002c
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING 0x1002c
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 0x1002d
#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST 0x10030
#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL 0x10030
#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE 0x10031
#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA 0x10032
#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR 0x10041
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 0x10042
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 0x10043
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3 0x100b7
#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3 0x100b8
#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3 0x100b9
#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST 0x10100
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST 0x10180
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS 0x10182
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK 0x10183
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY 0x10184
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS 0x10185
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK 0x10186
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL 0x10187
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 0x10188
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 0x10189
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 0x1018a
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 0x1018b
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG4 0x1018f
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 0x1018f
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG5 0x10190
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 0x10190
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG6 0x10191
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 0x10191
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG7 0x10192
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 0x10192
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG8 0x10193
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG9 0x10194
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG9_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG10 0x10195
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG10_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG11 0x10196
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG11_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG12 0x10197
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG12_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG13 0x10198
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG13_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST 0x101c7
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_RTR_DATA1 0x101c8
#define regBIF_CFG_DEV0_EPF0_VF5_RTR_DATA1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_RTR_DATA2 0x101c9
#define regBIF_CFG_DEV0_EPF0_VF5_RTR_DATA2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST 0x101dc
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP 0x101dd
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL 0x101dd
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST 0x101eb
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP 0x101ec
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL 0x101ec
#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID 0x10000
#define regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID 0x10000
#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_COMMAND 0x10001
#define regBIF_CFG_DEV0_EPF0_VF6_COMMAND_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_STATUS 0x10001
#define regBIF_CFG_DEV0_EPF0_VF6_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID 0x10002
#define regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE 0x10002
#define regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS 0x10002
#define regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS 0x10002
#define regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE 0x10003
#define regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_LATENCY 0x10003
#define regBIF_CFG_DEV0_EPF0_VF6_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_HEADER 0x10003
#define regBIF_CFG_DEV0_EPF0_VF6_HEADER_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_BIST 0x10003
#define regBIF_CFG_DEV0_EPF0_VF6_BIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 0x10004
#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 0x10005
#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 0x10006
#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 0x10007
#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 0x10008
#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 0x10009
#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR 0x1000a
#define regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID 0x1000b
#define regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR 0x1000c
#define regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR 0x1000d
#define regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST 0x10019
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP 0x10019
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP 0x1001a
#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL 0x1001b
#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS 0x1001b
#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP 0x1001c
#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL 0x1001d
#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS 0x1001d
#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 0x10022
#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 0x10023
#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 0x10023
#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 0x10024
#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 0x10025
#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 0x10025
#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST 0x10028
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL 0x10028
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO 0x10029
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 0x1002c
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING 0x1002c
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 0x1002d
#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST 0x10030
#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL 0x10030
#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE 0x10031
#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA 0x10032
#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR 0x10041
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 0x10042
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 0x10043
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3 0x100b7
#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3 0x100b8
#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3 0x100b9
#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST 0x10100
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST 0x10180
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS 0x10182
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK 0x10183
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY 0x10184
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS 0x10185
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK 0x10186
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL 0x10187
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 0x10188
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 0x10189
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 0x1018a
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 0x1018b
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG4 0x1018f
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 0x1018f
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG5 0x10190
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 0x10190
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG6 0x10191
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 0x10191
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG7 0x10192
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 0x10192
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG8 0x10193
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG9 0x10194
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG9_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG10 0x10195
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG10_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG11 0x10196
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG11_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG12 0x10197
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG12_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG13 0x10198
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG13_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST 0x101c7
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_RTR_DATA1 0x101c8
#define regBIF_CFG_DEV0_EPF0_VF6_RTR_DATA1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_RTR_DATA2 0x101c9
#define regBIF_CFG_DEV0_EPF0_VF6_RTR_DATA2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST 0x101dc
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP 0x101dd
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL 0x101dd
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST 0x101eb
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP 0x101ec
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL 0x101ec
#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID 0x10000
#define regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID 0x10000
#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_COMMAND 0x10001
#define regBIF_CFG_DEV0_EPF0_VF7_COMMAND_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_STATUS 0x10001
#define regBIF_CFG_DEV0_EPF0_VF7_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID 0x10002
#define regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE 0x10002
#define regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS 0x10002
#define regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS 0x10002
#define regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE 0x10003
#define regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_LATENCY 0x10003
#define regBIF_CFG_DEV0_EPF0_VF7_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_HEADER 0x10003
#define regBIF_CFG_DEV0_EPF0_VF7_HEADER_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_BIST 0x10003
#define regBIF_CFG_DEV0_EPF0_VF7_BIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 0x10004
#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 0x10005
#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 0x10006
#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 0x10007
#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 0x10008
#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 0x10009
#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR 0x1000a
#define regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID 0x1000b
#define regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR 0x1000c
#define regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR 0x1000d
#define regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY 0x1000f
#define regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST 0x10019
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP 0x10019
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP 0x1001a
#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL 0x1001b
#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS 0x1001b
#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP 0x1001c
#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL 0x1001d
#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS 0x1001d
#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 0x10022
#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 0x10023
#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 0x10023
#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 0x10024
#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 0x10025
#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 0x10025
#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST 0x10028
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL 0x10028
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO 0x10029
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA 0x1002a
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 0x1002b
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 0x1002c
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING 0x1002c
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 0x1002d
#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST 0x10030
#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL 0x10030
#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE 0x10031
#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA 0x10032
#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR 0x10041
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 0x10042
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 0x10043
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3 0x100b7
#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3 0x100b8
#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3 0x100b9
#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST 0x10100
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST 0x10180
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS 0x10182
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK 0x10183
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY 0x10184
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS 0x10185
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK 0x10186
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL 0x10187
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 0x10188
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 0x10189
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 0x1018a
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 0x1018b
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG4 0x1018f
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 0x1018f
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG5 0x10190
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 0x10190
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG6 0x10191
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 0x10191
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG7 0x10192
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 0x10192
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG8 0x10193
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG9 0x10194
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG9_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG10 0x10195
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG10_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG11 0x10196
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG11_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG12 0x10197
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG12_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG13 0x10198
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG13_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST 0x101c7
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_RTR_DATA1 0x101c8
#define regBIF_CFG_DEV0_EPF0_VF7_RTR_DATA1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_RTR_DATA2 0x101c9
#define regBIF_CFG_DEV0_EPF0_VF7_RTR_DATA2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST 0x101dc
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP 0x101dd
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL 0x101dd
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST 0x101eb
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP 0x101ec
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL 0x101ec
#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS 0x8e0b
#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG 0x8e0c
#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13
#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14
#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15
#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16
#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17
#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19
#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a
#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ 0x8e26
#define regBIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE 0x8e27
#define regBIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING 0x8e28
#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32
#define regBIF_BX_DEV0_EPF0_VF0_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56
#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57
#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58
#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59
#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a
#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b
#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c
#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d
#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL 0x8e5e
#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL 0x8e5f
#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX 0x8e60
#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP 0x8e81
#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP 0x8e82
#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_STATUS 0x8e83
#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS 0x8e84
#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_MM_INDEX 0x8000
#define regBIF_BX_DEV0_EPF0_VF0_0_MM_INDEX_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_MM_DATA 0x8001
#define regBIF_BX_DEV0_EPF0_VF0_0_MM_DATA_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_0_MM_INDEX_HI 0x8006
#define regBIF_BX_DEV0_EPF0_VF0_0_MM_INDEX_HI_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS 0x00eb
#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG 0x00ec
#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ 0x0106
#define regBIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE 0x0107
#define regBIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING 0x0108
#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
#define regBIF_BX_DEV0_EPF0_VF0_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW0 0x0136
#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW1 0x0137
#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW2 0x0138
#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW3 0x0139
#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW0 0x013a
#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW1 0x013b
#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW2 0x013c
#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW3 0x013d
#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL 0x013e
#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL 0x013f
#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX 0x0140
#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP 0x0161
#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP 0x0162
#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_STATUS 0x0163
#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS 0x0164
#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF0_1_MM_INDEX 0x0000
#define regBIF_BX_DEV0_EPF0_VF0_1_MM_INDEX_BASE_IDX 0
#define regBIF_BX_DEV0_EPF0_VF0_1_MM_DATA 0x0001
#define regBIF_BX_DEV0_EPF0_VF0_1_MM_DATA_BASE_IDX 0
#define regBIF_BX_DEV0_EPF0_VF0_1_MM_INDEX_HI 0x0006
#define regBIF_BX_DEV0_EPF0_VF0_1_MM_INDEX_HI_BASE_IDX 0
#define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0x0085
#define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0x00c0
#define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0x00c3
#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0x00c4
#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5
#define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0x0400
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0x0401
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0x0402
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0x0403
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0x0404
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0x0405
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0x0406
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0x0407
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0x0408
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0x0409
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0x040a
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0x040b
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO 0x040c
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI 0x040d
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA 0x040e
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL 0x040f
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_LO 0x0410
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_HI 0x0411
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_MSG_DATA 0x0412
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_CONTROL 0x0413
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_LO 0x0414
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_HI 0x0415
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_MSG_DATA 0x0416
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_CONTROL 0x0417
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_LO 0x0418
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_HI 0x0419
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_MSG_DATA 0x041a
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_CONTROL 0x041b
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_LO 0x041c
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_HI 0x041d
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_MSG_DATA 0x041e
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_CONTROL 0x041f
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_LO 0x0420
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_HI 0x0421
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_MSG_DATA 0x0422
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_CONTROL 0x0423
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0x0800
#define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX 3
#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS 0x8e0b
#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG 0x8e0c
#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13
#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14
#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15
#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16
#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17
#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19
#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a
#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ 0x8e26
#define regBIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE 0x8e27
#define regBIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING 0x8e28
#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32
#define regBIF_BX_DEV0_EPF0_VF1_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56
#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57
#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58
#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59
#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a
#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b
#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c
#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d
#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL 0x8e5e
#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL 0x8e5f
#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX 0x8e60
#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP 0x8e81
#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP 0x8e82
#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_STATUS 0x8e83
#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS 0x8e84
#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_MM_INDEX 0x8000
#define regBIF_BX_DEV0_EPF0_VF1_0_MM_INDEX_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_MM_DATA 0x8001
#define regBIF_BX_DEV0_EPF0_VF1_0_MM_DATA_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_0_MM_INDEX_HI 0x8006
#define regBIF_BX_DEV0_EPF0_VF1_0_MM_INDEX_HI_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS 0x00eb
#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG 0x00ec
#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ 0x0106
#define regBIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE 0x0107
#define regBIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING 0x0108
#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
#define regBIF_BX_DEV0_EPF0_VF1_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW0 0x0136
#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW1 0x0137
#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW2 0x0138
#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW3 0x0139
#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW0 0x013a
#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW1 0x013b
#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW2 0x013c
#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW3 0x013d
#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL 0x013e
#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL 0x013f
#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX 0x0140
#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP 0x0161
#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP 0x0162
#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_STATUS 0x0163
#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS 0x0164
#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF1_1_MM_INDEX 0x0000
#define regBIF_BX_DEV0_EPF0_VF1_1_MM_INDEX_BASE_IDX 0
#define regBIF_BX_DEV0_EPF0_VF1_1_MM_DATA 0x0001
#define regBIF_BX_DEV0_EPF0_VF1_1_MM_DATA_BASE_IDX 0
#define regBIF_BX_DEV0_EPF0_VF1_1_MM_INDEX_HI 0x0006
#define regBIF_BX_DEV0_EPF0_VF1_1_MM_INDEX_HI_BASE_IDX 0
#define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0x0085
#define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0x00c0
#define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0x00c3
#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0x00c4
#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0x00c5
#define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0x0400
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0x0401
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0x0402
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0x0403
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0x0404
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0x0405
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0x0406
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0x0407
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0x0408
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0x0409
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0x040a
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0x040b
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO 0x040c
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI 0x040d
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA 0x040e
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL 0x040f
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_LO 0x0410
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_HI 0x0411
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_MSG_DATA 0x0412
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_CONTROL 0x0413
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_LO 0x0414
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_HI 0x0415
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_MSG_DATA 0x0416
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_CONTROL 0x0417
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_LO 0x0418
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_HI 0x0419
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_MSG_DATA 0x041a
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_CONTROL 0x041b
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_LO 0x041c
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_HI 0x041d
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_MSG_DATA 0x041e
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_CONTROL 0x041f
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_LO 0x0420
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_HI 0x0421
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_MSG_DATA 0x0422
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_CONTROL 0x0423
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0x0800
#define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX 3
#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS 0x8e0b
#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG 0x8e0c
#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13
#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14
#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15
#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16
#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17
#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19
#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a
#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ 0x8e26
#define regBIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE 0x8e27
#define regBIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING 0x8e28
#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32
#define regBIF_BX_DEV0_EPF0_VF2_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56
#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57
#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58
#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59
#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a
#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b
#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c
#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d
#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL 0x8e5e
#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL 0x8e5f
#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX 0x8e60
#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP 0x8e81
#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP 0x8e82
#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_STATUS 0x8e83
#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS 0x8e84
#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_MM_INDEX 0x8000
#define regBIF_BX_DEV0_EPF0_VF2_0_MM_INDEX_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_MM_DATA 0x8001
#define regBIF_BX_DEV0_EPF0_VF2_0_MM_DATA_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_0_MM_INDEX_HI 0x8006
#define regBIF_BX_DEV0_EPF0_VF2_0_MM_INDEX_HI_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS 0x00eb
#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG 0x00ec
#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ 0x0106
#define regBIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE 0x0107
#define regBIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING 0x0108
#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
#define regBIF_BX_DEV0_EPF0_VF2_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW0 0x0136
#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW1 0x0137
#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW2 0x0138
#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW3 0x0139
#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW0 0x013a
#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW1 0x013b
#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW2 0x013c
#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW3 0x013d
#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL 0x013e
#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL 0x013f
#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX 0x0140
#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP 0x0161
#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP 0x0162
#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_STATUS 0x0163
#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS 0x0164
#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF2_1_MM_INDEX 0x0000
#define regBIF_BX_DEV0_EPF0_VF2_1_MM_INDEX_BASE_IDX 0
#define regBIF_BX_DEV0_EPF0_VF2_1_MM_DATA 0x0001
#define regBIF_BX_DEV0_EPF0_VF2_1_MM_DATA_BASE_IDX 0
#define regBIF_BX_DEV0_EPF0_VF2_1_MM_INDEX_HI 0x0006
#define regBIF_BX_DEV0_EPF0_VF2_1_MM_INDEX_HI_BASE_IDX 0
#define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0x0085
#define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0x00c0
#define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0x00c3
#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0x00c4
#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0x00c5
#define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0x0400
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0x0401
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0x0402
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0x0403
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0x0404
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0x0405
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0x0406
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0x0407
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0x0408
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0x0409
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0x040a
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0x040b
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO 0x040c
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI 0x040d
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA 0x040e
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL 0x040f
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_LO 0x0410
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_HI 0x0411
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_MSG_DATA 0x0412
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_CONTROL 0x0413
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_LO 0x0414
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_HI 0x0415
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_MSG_DATA 0x0416
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_CONTROL 0x0417
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_LO 0x0418
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_HI 0x0419
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_MSG_DATA 0x041a
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_CONTROL 0x041b
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_LO 0x041c
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_HI 0x041d
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_MSG_DATA 0x041e
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_CONTROL 0x041f
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_LO 0x0420
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_HI 0x0421
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_MSG_DATA 0x0422
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_CONTROL 0x0423
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0x0800
#define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX 3
#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS 0x8e0b
#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG 0x8e0c
#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13
#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14
#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15
#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16
#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17
#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19
#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a
#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ 0x8e26
#define regBIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE 0x8e27
#define regBIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING 0x8e28
#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32
#define regBIF_BX_DEV0_EPF0_VF3_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56
#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57
#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58
#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59
#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a
#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b
#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c
#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d
#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL 0x8e5e
#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL 0x8e5f
#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX 0x8e60
#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP 0x8e81
#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP 0x8e82
#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_STATUS 0x8e83
#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS 0x8e84
#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_MM_INDEX 0x8000
#define regBIF_BX_DEV0_EPF0_VF3_0_MM_INDEX_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_MM_DATA 0x8001
#define regBIF_BX_DEV0_EPF0_VF3_0_MM_DATA_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_0_MM_INDEX_HI 0x8006
#define regBIF_BX_DEV0_EPF0_VF3_0_MM_INDEX_HI_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS 0x00eb
#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG 0x00ec
#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ 0x0106
#define regBIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE 0x0107
#define regBIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING 0x0108
#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
#define regBIF_BX_DEV0_EPF0_VF3_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW0 0x0136
#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW1 0x0137
#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW2 0x0138
#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW3 0x0139
#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW0 0x013a
#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW1 0x013b
#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW2 0x013c
#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW3 0x013d
#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL 0x013e
#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL 0x013f
#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX 0x0140
#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP 0x0161
#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP 0x0162
#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_STATUS 0x0163
#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS 0x0164
#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF3_1_MM_INDEX 0x0000
#define regBIF_BX_DEV0_EPF0_VF3_1_MM_INDEX_BASE_IDX 0
#define regBIF_BX_DEV0_EPF0_VF3_1_MM_DATA 0x0001
#define regBIF_BX_DEV0_EPF0_VF3_1_MM_DATA_BASE_IDX 0
#define regBIF_BX_DEV0_EPF0_VF3_1_MM_INDEX_HI 0x0006
#define regBIF_BX_DEV0_EPF0_VF3_1_MM_INDEX_HI_BASE_IDX 0
#define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0x0085
#define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0x00c0
#define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0x00c3
#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0x00c4
#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0x00c5
#define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0x0400
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0x0401
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0x0402
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0x0403
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0x0404
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0x0405
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0x0406
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0x0407
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0x0408
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0x0409
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0x040a
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0x040b
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO 0x040c
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI 0x040d
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA 0x040e
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL 0x040f
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_LO 0x0410
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_HI 0x0411
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_MSG_DATA 0x0412
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_CONTROL 0x0413
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_LO 0x0414
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_HI 0x0415
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_MSG_DATA 0x0416
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_CONTROL 0x0417
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_LO 0x0418
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_HI 0x0419
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_MSG_DATA 0x041a
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_CONTROL 0x041b
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_LO 0x041c
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_HI 0x041d
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_MSG_DATA 0x041e
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_CONTROL 0x041f
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_LO 0x0420
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_HI 0x0421
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_MSG_DATA 0x0422
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_CONTROL 0x0423
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0x0800
#define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX 3
#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS 0x8e0b
#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG 0x8e0c
#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13
#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14
#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15
#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16
#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17
#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19
#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a
#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ 0x8e26
#define regBIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE 0x8e27
#define regBIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING 0x8e28
#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32
#define regBIF_BX_DEV0_EPF0_VF4_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56
#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57
#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58
#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59
#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a
#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b
#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c
#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d
#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL 0x8e5e
#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL 0x8e5f
#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX 0x8e60
#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP 0x8e81
#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP 0x8e82
#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_STATUS 0x8e83
#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS 0x8e84
#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_MM_INDEX 0x8000
#define regBIF_BX_DEV0_EPF0_VF4_0_MM_INDEX_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_MM_DATA 0x8001
#define regBIF_BX_DEV0_EPF0_VF4_0_MM_DATA_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_0_MM_INDEX_HI 0x8006
#define regBIF_BX_DEV0_EPF0_VF4_0_MM_INDEX_HI_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS 0x00eb
#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG 0x00ec
#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ 0x0106
#define regBIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE 0x0107
#define regBIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING 0x0108
#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
#define regBIF_BX_DEV0_EPF0_VF4_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW0 0x0136
#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW1 0x0137
#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW2 0x0138
#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW3 0x0139
#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW0 0x013a
#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW1 0x013b
#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW2 0x013c
#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW3 0x013d
#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL 0x013e
#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL 0x013f
#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX 0x0140
#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP 0x0161
#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP 0x0162
#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_STATUS 0x0163
#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS 0x0164
#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF4_1_MM_INDEX 0x0000
#define regBIF_BX_DEV0_EPF0_VF4_1_MM_INDEX_BASE_IDX 0
#define regBIF_BX_DEV0_EPF0_VF4_1_MM_DATA 0x0001
#define regBIF_BX_DEV0_EPF0_VF4_1_MM_DATA_BASE_IDX 0
#define regBIF_BX_DEV0_EPF0_VF4_1_MM_INDEX_HI 0x0006
#define regBIF_BX_DEV0_EPF0_VF4_1_MM_INDEX_HI_BASE_IDX 0
#define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0x0085
#define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0x00c0
#define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0x00c3
#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0x00c4
#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0x00c5
#define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0x0400
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0x0401
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0x0402
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0x0403
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0x0404
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0x0405
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0x0406
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0x0407
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0x0408
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0x0409
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0x040a
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0x040b
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO 0x040c
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI 0x040d
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA 0x040e
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL 0x040f
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_LO 0x0410
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_HI 0x0411
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_MSG_DATA 0x0412
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_CONTROL 0x0413
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_LO 0x0414
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_HI 0x0415
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_MSG_DATA 0x0416
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_CONTROL 0x0417
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_LO 0x0418
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_HI 0x0419
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_MSG_DATA 0x041a
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_CONTROL 0x041b
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_LO 0x041c
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_HI 0x041d
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_MSG_DATA 0x041e
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_CONTROL 0x041f
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_LO 0x0420
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_HI 0x0421
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_MSG_DATA 0x0422
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_CONTROL 0x0423
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0x0800
#define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX 3
#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS 0x8e0b
#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG 0x8e0c
#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13
#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14
#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15
#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16
#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17
#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19
#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a
#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ 0x8e26
#define regBIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE 0x8e27
#define regBIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING 0x8e28
#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32
#define regBIF_BX_DEV0_EPF0_VF5_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56
#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57
#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58
#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59
#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a
#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b
#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c
#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d
#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL 0x8e5e
#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL 0x8e5f
#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX 0x8e60
#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP 0x8e81
#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP 0x8e82
#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_STATUS 0x8e83
#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS 0x8e84
#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_MM_INDEX 0x8000
#define regBIF_BX_DEV0_EPF0_VF5_0_MM_INDEX_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_MM_DATA 0x8001
#define regBIF_BX_DEV0_EPF0_VF5_0_MM_DATA_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_0_MM_INDEX_HI 0x8006
#define regBIF_BX_DEV0_EPF0_VF5_0_MM_INDEX_HI_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS 0x00eb
#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG 0x00ec
#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ 0x0106
#define regBIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE 0x0107
#define regBIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING 0x0108
#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
#define regBIF_BX_DEV0_EPF0_VF5_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW0 0x0136
#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW1 0x0137
#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW2 0x0138
#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW3 0x0139
#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW0 0x013a
#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW1 0x013b
#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW2 0x013c
#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW3 0x013d
#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL 0x013e
#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL 0x013f
#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX 0x0140
#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP 0x0161
#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP 0x0162
#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_STATUS 0x0163
#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS 0x0164
#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF5_1_MM_INDEX 0x0000
#define regBIF_BX_DEV0_EPF0_VF5_1_MM_INDEX_BASE_IDX 0
#define regBIF_BX_DEV0_EPF0_VF5_1_MM_DATA 0x0001
#define regBIF_BX_DEV0_EPF0_VF5_1_MM_DATA_BASE_IDX 0
#define regBIF_BX_DEV0_EPF0_VF5_1_MM_INDEX_HI 0x0006
#define regBIF_BX_DEV0_EPF0_VF5_1_MM_INDEX_HI_BASE_IDX 0
#define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0x0085
#define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0x00c0
#define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0x00c3
#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0x00c4
#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0x00c5
#define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0x0400
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0x0401
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0x0402
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0x0403
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0x0404
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0x0405
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0x0406
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0x0407
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0x0408
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0x0409
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0x040a
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0x040b
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO 0x040c
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI 0x040d
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA 0x040e
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL 0x040f
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_LO 0x0410
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_HI 0x0411
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_MSG_DATA 0x0412
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_CONTROL 0x0413
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_LO 0x0414
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_HI 0x0415
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_MSG_DATA 0x0416
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_CONTROL 0x0417
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_LO 0x0418
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_HI 0x0419
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_MSG_DATA 0x041a
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_CONTROL 0x041b
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_LO 0x041c
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_HI 0x041d
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_MSG_DATA 0x041e
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_CONTROL 0x041f
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_LO 0x0420
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_HI 0x0421
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_MSG_DATA 0x0422
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_CONTROL 0x0423
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0x0800
#define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX 3
#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS 0x8e0b
#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG 0x8e0c
#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13
#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14
#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15
#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16
#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17
#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19
#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a
#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ 0x8e26
#define regBIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE 0x8e27
#define regBIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING 0x8e28
#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32
#define regBIF_BX_DEV0_EPF0_VF6_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56
#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57
#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58
#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59
#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a
#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b
#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c
#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d
#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL 0x8e5e
#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL 0x8e5f
#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX 0x8e60
#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP 0x8e81
#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP 0x8e82
#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_STATUS 0x8e83
#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS 0x8e84
#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_MM_INDEX 0x8000
#define regBIF_BX_DEV0_EPF0_VF6_0_MM_INDEX_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_MM_DATA 0x8001
#define regBIF_BX_DEV0_EPF0_VF6_0_MM_DATA_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_0_MM_INDEX_HI 0x8006
#define regBIF_BX_DEV0_EPF0_VF6_0_MM_INDEX_HI_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS 0x00eb
#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG 0x00ec
#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ 0x0106
#define regBIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE 0x0107
#define regBIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING 0x0108
#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
#define regBIF_BX_DEV0_EPF0_VF6_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW0 0x0136
#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW1 0x0137
#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW2 0x0138
#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW3 0x0139
#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW0 0x013a
#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW1 0x013b
#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW2 0x013c
#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW3 0x013d
#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL 0x013e
#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL 0x013f
#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX 0x0140
#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP 0x0161
#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP 0x0162
#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_STATUS 0x0163
#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS 0x0164
#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF6_1_MM_INDEX 0x0000
#define regBIF_BX_DEV0_EPF0_VF6_1_MM_INDEX_BASE_IDX 0
#define regBIF_BX_DEV0_EPF0_VF6_1_MM_DATA 0x0001
#define regBIF_BX_DEV0_EPF0_VF6_1_MM_DATA_BASE_IDX 0
#define regBIF_BX_DEV0_EPF0_VF6_1_MM_INDEX_HI 0x0006
#define regBIF_BX_DEV0_EPF0_VF6_1_MM_INDEX_HI_BASE_IDX 0
#define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0x0085
#define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0x00c0
#define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0x00c3
#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0x00c4
#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0x00c5
#define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0x0400
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0x0401
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0x0402
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0x0403
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0x0404
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0x0405
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0x0406
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0x0407
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0x0408
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0x0409
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0x040a
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0x040b
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO 0x040c
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI 0x040d
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA 0x040e
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL 0x040f
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_LO 0x0410
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_HI 0x0411
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_MSG_DATA 0x0412
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_CONTROL 0x0413
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_LO 0x0414
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_HI 0x0415
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_MSG_DATA 0x0416
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_CONTROL 0x0417
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_LO 0x0418
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_HI 0x0419
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_MSG_DATA 0x041a
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_CONTROL 0x041b
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_LO 0x041c
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_HI 0x041d
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_MSG_DATA 0x041e
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_CONTROL 0x041f
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_LO 0x0420
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_HI 0x0421
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_MSG_DATA 0x0422
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_CONTROL 0x0423
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0x0800
#define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX 3
#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS 0x8e0b
#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG 0x8e0c
#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13
#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14
#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15
#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16
#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17
#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19
#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a
#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ 0x8e26
#define regBIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE 0x8e27
#define regBIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING 0x8e28
#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32
#define regBIF_BX_DEV0_EPF0_VF7_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56
#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57
#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58
#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59
#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a
#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b
#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c
#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d
#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL 0x8e5e
#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL 0x8e5f
#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX 0x8e60
#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP 0x8e81
#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP 0x8e82
#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_STATUS 0x8e83
#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS 0x8e84
#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_MM_INDEX 0x8000
#define regBIF_BX_DEV0_EPF0_VF7_0_MM_INDEX_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_MM_DATA 0x8001
#define regBIF_BX_DEV0_EPF0_VF7_0_MM_DATA_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_0_MM_INDEX_HI 0x8006
#define regBIF_BX_DEV0_EPF0_VF7_0_MM_INDEX_HI_BASE_IDX 5
#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS 0x00eb
#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG 0x00ec
#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9
#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa
#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ 0x0106
#define regBIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE 0x0107
#define regBIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING 0x0108
#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
#define regBIF_BX_DEV0_EPF0_VF7_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW0 0x0136
#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW1 0x0137
#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW2 0x0138
#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW3 0x0139
#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW0 0x013a
#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW1 0x013b
#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW2 0x013c
#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW3 0x013d
#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL 0x013e
#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL 0x013f
#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX 0x0140
#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP 0x0161
#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP 0x0162
#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_STATUS 0x0163
#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS 0x0164
#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS_BASE_IDX 2
#define regBIF_BX_DEV0_EPF0_VF7_1_MM_INDEX 0x0000
#define regBIF_BX_DEV0_EPF0_VF7_1_MM_INDEX_BASE_IDX 0
#define regBIF_BX_DEV0_EPF0_VF7_1_MM_DATA 0x0001
#define regBIF_BX_DEV0_EPF0_VF7_1_MM_DATA_BASE_IDX 0
#define regBIF_BX_DEV0_EPF0_VF7_1_MM_INDEX_HI 0x0006
#define regBIF_BX_DEV0_EPF0_VF7_1_MM_INDEX_HI_BASE_IDX 0
#define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0x0085
#define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0x00c0
#define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0x00c3
#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0x00c4
#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0x00c5
#define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0x0400
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0x0401
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0x0402
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0x0403
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0x0404
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0x0405
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0x0406
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0x0407
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0x0408
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0x0409
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0x040a
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0x040b
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO 0x040c
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI 0x040d
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA 0x040e
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL 0x040f
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_LO 0x0410
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_HI 0x0411
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_MSG_DATA 0x0412
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_CONTROL 0x0413
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_LO 0x0414
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_HI 0x0415
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_MSG_DATA 0x0416
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_CONTROL 0x0417
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_LO 0x0418
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_HI 0x0419
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_MSG_DATA 0x041a
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_CONTROL 0x041b
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_LO 0x041c
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_HI 0x041d
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_MSG_DATA 0x041e
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_CONTROL 0x041f
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_LO 0x0420
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_HI 0x0421
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_MSG_DATA 0x0422
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_CONTROL 0x0423
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_CONTROL_BASE_IDX 3
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0x0800
#define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX 3
#define regBIF_CFG_DEV0_EPF1_VENDOR_ID 0x10400
#define regBIF_CFG_DEV0_EPF1_VENDOR_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_DEVICE_ID 0x10400
#define regBIF_CFG_DEV0_EPF1_DEVICE_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_COMMAND 0x10401
#define regBIF_CFG_DEV0_EPF1_COMMAND_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_STATUS 0x10401
#define regBIF_CFG_DEV0_EPF1_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_REVISION_ID 0x10402
#define regBIF_CFG_DEV0_EPF1_REVISION_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PROG_INTERFACE 0x10402
#define regBIF_CFG_DEV0_EPF1_PROG_INTERFACE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_SUB_CLASS 0x10402
#define regBIF_CFG_DEV0_EPF1_SUB_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_BASE_CLASS 0x10402
#define regBIF_CFG_DEV0_EPF1_BASE_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_CACHE_LINE 0x10403
#define regBIF_CFG_DEV0_EPF1_CACHE_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_LATENCY 0x10403
#define regBIF_CFG_DEV0_EPF1_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_HEADER 0x10403
#define regBIF_CFG_DEV0_EPF1_HEADER_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_BIST 0x10403
#define regBIF_CFG_DEV0_EPF1_BIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_1 0x10404
#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_2 0x10405
#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_3 0x10406
#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_4 0x10407
#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_5 0x10408
#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_6 0x10409
#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR 0x1040a
#define regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID 0x1040b
#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR 0x1040c
#define regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_CAP_PTR 0x1040d
#define regBIF_CFG_DEV0_EPF1_CAP_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE 0x1040f
#define regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN 0x1040f
#define regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_MIN_GRANT 0x1040f
#define regBIF_CFG_DEV0_EPF1_MIN_GRANT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_MAX_LATENCY 0x1040f
#define regBIF_CFG_DEV0_EPF1_MAX_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST 0x10412
#define regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W 0x10413
#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST 0x10414
#define regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PMI_CAP 0x10414
#define regBIF_CFG_DEV0_EPF1_PMI_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL 0x10415
#define regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL_BASE_IDX 5
#define regSBRN 0x10418
#define regSBRN_BASE_IDX 5
#define regFLADJ 0x10418
#define regFLADJ_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST 0x10419
#define regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_CAP 0x10419
#define regBIF_CFG_DEV0_EPF1_PCIE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP 0x1041a
#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL 0x1041b
#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS 0x1041b
#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_LINK_CAP 0x1041c
#define regBIF_CFG_DEV0_EPF1_LINK_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_LINK_CNTL 0x1041d
#define regBIF_CFG_DEV0_EPF1_LINK_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_LINK_STATUS 0x1041d
#define regBIF_CFG_DEV0_EPF1_LINK_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP2 0x10422
#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2 0x10423
#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2 0x10423
#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_LINK_CAP2 0x10424
#define regBIF_CFG_DEV0_EPF1_LINK_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_LINK_CNTL2 0x10425
#define regBIF_CFG_DEV0_EPF1_LINK_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_LINK_STATUS2 0x10425
#define regBIF_CFG_DEV0_EPF1_LINK_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST 0x10428
#define regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL 0x10428
#define regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO 0x10429
#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI 0x1042a
#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA 0x1042a
#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA 0x1042a
#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_MSI_MASK 0x1042b
#define regBIF_CFG_DEV0_EPF1_MSI_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 0x1042b
#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 0x1042b
#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_MSI_MASK_64 0x1042c
#define regBIF_CFG_DEV0_EPF1_MSI_MASK_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_MSI_PENDING 0x1042c
#define regBIF_CFG_DEV0_EPF1_MSI_PENDING_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_MSI_PENDING_64 0x1042d
#define regBIF_CFG_DEV0_EPF1_MSI_PENDING_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST 0x10430
#define regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL 0x10430
#define regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_MSIX_TABLE 0x10431
#define regBIF_CFG_DEV0_EPF1_MSIX_TABLE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_MSIX_PBA 0x10432
#define regBIF_CFG_DEV0_EPF1_MSIX_PBA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10440
#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR 0x10441
#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 0x10442
#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 0x10443
#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST 0x104b6
#define regBIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP3 0x104b7
#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL3 0x104b8
#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS3 0x104b9
#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST 0x10500
#define regBIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST 0x10580
#define regBIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10581
#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS 0x10582
#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK 0x10583
#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY 0x10584
#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS 0x10585
#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK 0x10586
#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL 0x10587
#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 0x10588
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 0x10589
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 0x1058a
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 0x1058b
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG4 0x1058f
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 0x1058f
#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG5 0x10590
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 0x10590
#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG6 0x10591
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 0x10591
#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG7 0x10592
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 0x10592
#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG8 0x10593
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG9 0x10594
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG9_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG10 0x10595
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG10_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG11 0x10596
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG11_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG12 0x10597
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG12_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG13 0x10598
#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG13_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST 0x105b7
#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP 0x105b8
#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL 0x105b8
#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST 0x105c7
#define regBIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_RTR_DATA1 0x105c8
#define regBIF_CFG_DEV0_EPF1_RTR_DATA1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_RTR_DATA2 0x105c9
#define regBIF_CFG_DEV0_EPF1_RTR_DATA2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x105ca
#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT 0x105cb
#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA 0x105cc
#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP 0x105cd
#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST 0x105ce
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP 0x105cf
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR 0x105d0
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS 0x105d1
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL 0x105d1
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x105d2
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x105d2
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x105d2
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x105d2
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x105d3
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x105d3
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x105d3
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x105d3
#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST 0x105dc
#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP 0x105dd
#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL 0x105dd
#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST 0x105de
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP 0x105df
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL 0x105e0
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP 0x105e1
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL 0x105e2
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP 0x105e3
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL 0x105e4
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP 0x105e5
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL 0x105e6
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP 0x105e7
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL 0x105e8
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP 0x105e9
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL 0x105ea
#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST 0x105f1
#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP 0x105f2
#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL 0x105f2
#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST 0x105f3
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP 0x105f4
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL 0x105f5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS 0x105f5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS 0x105f6
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS 0x105f6
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS 0x105f7
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK 0x105f7
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET 0x105f8
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE 0x105f8
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID 0x105f9
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x105fa
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x105fb
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0 0x105fc
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1 0x105fd
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2 0x105fe
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3 0x105ff
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4 0x10600
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5 0x10601
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x10602
#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x10638
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP 0x10639
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL 0x1063a
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP 0x1063b
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL 0x1063c
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP 0x1063d
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL 0x1063e
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP 0x1063f
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL 0x10640
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP 0x10641
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL 0x10642
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP 0x10643
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL 0x10644
#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_VENDOR_ID 0x10400
#define regBIF_CFG_DEV0_EPF1_VF0_VENDOR_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_ID 0x10400
#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_COMMAND 0x10401
#define regBIF_CFG_DEV0_EPF1_VF0_COMMAND_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_STATUS 0x10401
#define regBIF_CFG_DEV0_EPF1_VF0_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_REVISION_ID 0x10402
#define regBIF_CFG_DEV0_EPF1_VF0_REVISION_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PROG_INTERFACE 0x10402
#define regBIF_CFG_DEV0_EPF1_VF0_PROG_INTERFACE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_SUB_CLASS 0x10402
#define regBIF_CFG_DEV0_EPF1_VF0_SUB_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_BASE_CLASS 0x10402
#define regBIF_CFG_DEV0_EPF1_VF0_BASE_CLASS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_CACHE_LINE 0x10403
#define regBIF_CFG_DEV0_EPF1_VF0_CACHE_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_LATENCY 0x10403
#define regBIF_CFG_DEV0_EPF1_VF0_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_HEADER 0x10403
#define regBIF_CFG_DEV0_EPF1_VF0_HEADER_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_BIST 0x10403
#define regBIF_CFG_DEV0_EPF1_VF0_BIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_1 0x10404
#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_2 0x10405
#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_3 0x10406
#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_4 0x10407
#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_5 0x10408
#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_6 0x10409
#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_CARDBUS_CIS_PTR 0x1040a
#define regBIF_CFG_DEV0_EPF1_VF0_CARDBUS_CIS_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID 0x1040b
#define regBIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR 0x1040c
#define regBIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_CAP_PTR 0x1040d
#define regBIF_CFG_DEV0_EPF1_VF0_CAP_PTR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_LINE 0x1040f
#define regBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_LINE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_PIN 0x1040f
#define regBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_PIN_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_MIN_GRANT 0x1040f
#define regBIF_CFG_DEV0_EPF1_VF0_MIN_GRANT_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_MAX_LATENCY 0x1040f
#define regBIF_CFG_DEV0_EPF1_VF0_MAX_LATENCY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST 0x10419
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP 0x10419
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP 0x1041a
#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL 0x1041b
#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS 0x1041b
#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CAP 0x1041c
#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL 0x1041d
#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS 0x1041d
#define regBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2 0x10422
#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2 0x10423
#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS2 0x10423
#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CAP2 0x10424
#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CAP2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2 0x10425
#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2 0x10425
#define regBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST 0x10428
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL 0x10428
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_LO 0x10429
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_LO_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_HI 0x1042a
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_HI_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA 0x1042a
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA 0x1042a
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MASK 0x1042b
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_64 0x1042b
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_64 0x1042b
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MASK_64 0x1042c
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MASK_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING 0x1042c
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_64 0x1042d
#define regBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_64_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST 0x10430
#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL 0x10430
#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE 0x10431
#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_PBA 0x10432
#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_PBA_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10440
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x10441
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC1 0x10442
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC2 0x10443
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST 0x104b6
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3 0x104b7
#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3 0x104b8
#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3 0x104b9
#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST 0x10500
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST 0x10580
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10581
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS 0x10582
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK 0x10583
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY 0x10584
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS 0x10585
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK 0x10586
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL 0x10587
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG0 0x10588
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG1 0x10589
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG2 0x1058a
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG3 0x1058b
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG4 0x1058f
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG4_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG0 0x1058f
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG5 0x10590
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG5_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG1 0x10590
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG6 0x10591
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG6_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG2 0x10591
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG7 0x10592
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG7_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG3 0x10592
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG8 0x10593
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG8_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG9 0x10594
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG9_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG10 0x10595
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG10_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG11 0x10596
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG11_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG12 0x10597
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG12_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG13 0x10598
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG13_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST 0x105c7
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_RTR_DATA1 0x105c8
#define regBIF_CFG_DEV0_EPF1_VF0_RTR_DATA1_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_RTR_DATA2 0x105c9
#define regBIF_CFG_DEV0_EPF1_VF0_RTR_DATA2_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST 0x105dc
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP 0x105dd
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP_BASE_IDX 5
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL 0x105dd
#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL_BASE_IDX 5
#define regRCC_DEV0_1_RCC_VDM_SUPPORT 0xc440
#define regRCC_DEV0_1_RCC_VDM_SUPPORT_BASE_IDX 5
#define regRCC_DEV0_1_RCC_BUS_CNTL 0xc441
#define regRCC_DEV0_1_RCC_BUS_CNTL_BASE_IDX 5
#define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC 0xc442
#define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_BASE_IDX 5
#define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL 0xc443
#define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL_BASE_IDX 5
#define regRCC_DEV0_1_RCC_CMN_LINK_CNTL 0xc444
#define regRCC_DEV0_1_RCC_CMN_LINK_CNTL_BASE_IDX 5
#define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE 0xc445
#define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 5
#define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL 0xc446
#define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_BASE_IDX 5
#define regRCC_DEV0_1_RCC_MH_ARB_CNTL 0xc447
#define regRCC_DEV0_1_RCC_MH_ARB_CNTL_BASE_IDX 5
#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 0xc448
#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 5
#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 0xc449
#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 5
#define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH 0xc44c
#define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH_BASE_IDX 5
#define regRCC_EP_DEV0_1_EP_PCIE_CNTL 0xc44e
#define regRCC_EP_DEV0_1_EP_PCIE_CNTL_BASE_IDX 5
#define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL 0xc44f
#define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_BASE_IDX 5
#define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS 0xc450
#define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_BASE_IDX 5
#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 0xc451
#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_BASE_IDX 5
#define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL 0xc452
#define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_BASE_IDX 5
#define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL 0xc453
#define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_BASE_IDX 5
#define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL 0xc454
#define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_BASE_IDX 5
#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC 0xc455
#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_BASE_IDX 5
#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 0xc456
#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_BASE_IDX 5
#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP 0xc457
#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_BASE_IDX 5
#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0xc458
#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 5
#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL 0xc458
#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_BASE_IDX 5
#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0xc458
#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5
#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0xc459
#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5
#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0xc459
#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5
#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0xc459
#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5
#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0xc459
#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5
#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0xc45a
#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5
#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0xc45a
#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5
#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0xc45a
#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5
#define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL 0xc45c
#define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_BASE_IDX 5
#define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED 0xc45d
#define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED_BASE_IDX 5
#define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL 0xc45f
#define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_BASE_IDX 5
#define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID 0xc460
#define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 5
#define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL 0xc461
#define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_BASE_IDX 5
#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL 0xc462
#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_BASE_IDX 5
#define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL 0xc463
#define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 5
#define regRCC_EP_DEV0_1_EP_PCIE_DEVICE_CNTL3 0xc464
#define regRCC_EP_DEV0_1_EP_PCIE_DEVICE_CNTL3_BASE_IDX 5
#define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED 0xc468
#define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED_BASE_IDX 5
#define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH 0xc469
#define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_BASE_IDX 5
#define regRCC_DWN_DEV0_1_DN_PCIE_CNTL 0xc46b
#define regRCC_DWN_DEV0_1_DN_PCIE_CNTL_BASE_IDX 5
#define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL 0xc46c
#define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_BASE_IDX 5
#define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 0xc46d
#define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_BASE_IDX 5
#define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL 0xc46e
#define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_BASE_IDX 5
#define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL 0xc46f
#define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_BASE_IDX 5
#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 0xc470
#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_BASE_IDX 5
#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC 0xc471
#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_BASE_IDX 5
#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 0xc472
#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_BASE_IDX 5
#define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL 0xc475
#define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_BASE_IDX 5
#define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL 0xc476
#define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL_BASE_IDX 5
#define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL 0xc477
#define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_BASE_IDX 5
#define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2 0xc478
#define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_BASE_IDX 5
#define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC 0xc479
#define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_BASE_IDX 5
#define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP 0xc47a
#define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_BASE_IDX 5
#define regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL 0xd040
#define regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL_BASE_IDX 5
#define regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE 0xd041
#define regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE_BASE_IDX 5
#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0 0xd042
#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0_BASE_IDX 5
#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1 0xd043
#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1_BASE_IDX 5
#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2 0xd044
#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2_BASE_IDX 5
#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3 0xd045
#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3_BASE_IDX 5
#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4 0xd046
#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4_BASE_IDX 5
#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5 0xd047
#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5_BASE_IDX 5
#define regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL 0xd048
#define regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL_BASE_IDX 5
#define regRCC_PFC_AMDGFX_RCC_PFC_MISC_CNTL 0xd049
#define regRCC_PFC_AMDGFX_RCC_PFC_MISC_CNTL_BASE_IDX 5
#define regRCC_PFC_AMDGFX_RCC_NFC 0xd04a
#define regRCC_PFC_AMDGFX_RCC_NFC_BASE_IDX 5
#define regSHADOW_COMMAND 0xc001
#define regSHADOW_COMMAND_BASE_IDX 5
#define regSHADOW_BASE_ADDR_1 0xc004
#define regSHADOW_BASE_ADDR_1_BASE_IDX 5
#define regSHADOW_BASE_ADDR_2 0xc005
#define regSHADOW_BASE_ADDR_2_BASE_IDX 5
#define regSHADOW_SUB_BUS_NUMBER_LATENCY 0xc006
#define regSHADOW_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5
#define regSHADOW_IO_BASE_LIMIT 0xc007
#define regSHADOW_IO_BASE_LIMIT_BASE_IDX 5
#define regSHADOW_MEM_BASE_LIMIT 0xc008
#define regSHADOW_MEM_BASE_LIMIT_BASE_IDX 5
#define regSHADOW_PREF_BASE_LIMIT 0xc009
#define regSHADOW_PREF_BASE_LIMIT_BASE_IDX 5
#define regSHADOW_PREF_BASE_UPPER 0xc00a
#define regSHADOW_PREF_BASE_UPPER_BASE_IDX 5
#define regSHADOW_PREF_LIMIT_UPPER 0xc00b
#define regSHADOW_PREF_LIMIT_UPPER_BASE_IDX 5
#define regSHADOW_IO_BASE_LIMIT_HI 0xc00c
#define regSHADOW_IO_BASE_LIMIT_HI_BASE_IDX 5
#define regSHADOW_IRQ_BRIDGE_CNTL 0xc00f
#define regSHADOW_IRQ_BRIDGE_CNTL_BASE_IDX 5
#define regSUC_INDEX 0xc038
#define regSUC_INDEX_BASE_IDX 5
#define regSUC_DATA 0xc039
#define regSUC_DATA_BASE_IDX 5
#define regSUM_INDEX 0xec38
#define regSUM_INDEX_BASE_IDX 5
#define regSUM_DATA 0xec39
#define regSUM_DATA_BASE_IDX 5
#define regSUM_INDEX_HI 0xec3b
#define regSUM_INDEX_HI_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0 0xc400
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1 0xc401
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2 0xc402
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3 0xc403
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4 0xc404
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5 0xc405
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6 0xc406
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7 0xc407
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8 0xc408
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9 0xc409
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10 0xc40a
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11 0xc40b
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12 0xc40c
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13 0xc40d
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14 0xc40e
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP15 0xc40f
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP15_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP16 0xc410
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP16_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP17 0xc411
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP17_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP18 0xc412
#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP18_BASE_IDX 5
#define regRCC_DEV1_PORT_STRAP0 0xc480
#define regRCC_DEV1_PORT_STRAP0_BASE_IDX 5
#define regRCC_DEV1_PORT_STRAP1 0xc481
#define regRCC_DEV1_PORT_STRAP1_BASE_IDX 5
#define regRCC_DEV1_PORT_STRAP2 0xc482
#define regRCC_DEV1_PORT_STRAP2_BASE_IDX 5
#define regRCC_DEV1_PORT_STRAP3 0xc483
#define regRCC_DEV1_PORT_STRAP3_BASE_IDX 5
#define regRCC_DEV1_PORT_STRAP4 0xc484
#define regRCC_DEV1_PORT_STRAP4_BASE_IDX 5
#define regRCC_DEV1_PORT_STRAP5 0xc485
#define regRCC_DEV1_PORT_STRAP5_BASE_IDX 5
#define regRCC_DEV1_PORT_STRAP6 0xc486
#define regRCC_DEV1_PORT_STRAP6_BASE_IDX 5
#define regRCC_DEV1_PORT_STRAP7 0xc487
#define regRCC_DEV1_PORT_STRAP7_BASE_IDX 5
#define regRCC_DEV1_PORT_STRAP8 0xc488
#define regRCC_DEV1_PORT_STRAP8_BASE_IDX 5
#define regRCC_DEV1_PORT_STRAP9 0xc489
#define regRCC_DEV1_PORT_STRAP9_BASE_IDX 5
#define regRCC_DEV1_PORT_STRAP10 0xc48a
#define regRCC_DEV1_PORT_STRAP10_BASE_IDX 5
#define regRCC_DEV1_PORT_STRAP11 0xc48b
#define regRCC_DEV1_PORT_STRAP11_BASE_IDX 5
#define regRCC_DEV1_PORT_STRAP12 0xc48c
#define regRCC_DEV1_PORT_STRAP12_BASE_IDX 5
#define regRCC_DEV1_PORT_STRAP13 0xc48d
#define regRCC_DEV1_PORT_STRAP13_BASE_IDX 5
#define regRCC_DEV1_PORT_STRAP14 0xc48e
#define regRCC_DEV1_PORT_STRAP14_BASE_IDX 5
#define regRCC_DEV1_PORT_STRAP15 0xc48f
#define regRCC_DEV1_PORT_STRAP15_BASE_IDX 5
#define regRCC_DEV1_PORT_STRAP16 0xc490
#define regRCC_DEV1_PORT_STRAP16_BASE_IDX 5
#define regRCC_DEV2_PORT_STRAP0 0xc500
#define regRCC_DEV2_PORT_STRAP0_BASE_IDX 5
#define regRCC_DEV2_PORT_STRAP1 0xc501
#define regRCC_DEV2_PORT_STRAP1_BASE_IDX 5
#define regRCC_DEV2_PORT_STRAP2 0xc502
#define regRCC_DEV2_PORT_STRAP2_BASE_IDX 5
#define regRCC_DEV2_PORT_STRAP3 0xc503
#define regRCC_DEV2_PORT_STRAP3_BASE_IDX 5
#define regRCC_DEV2_PORT_STRAP4 0xc504
#define regRCC_DEV2_PORT_STRAP4_BASE_IDX 5
#define regRCC_DEV2_PORT_STRAP5 0xc505
#define regRCC_DEV2_PORT_STRAP5_BASE_IDX 5
#define regRCC_DEV2_PORT_STRAP6 0xc506
#define regRCC_DEV2_PORT_STRAP6_BASE_IDX 5
#define regRCC_DEV2_PORT_STRAP7 0xc507
#define regRCC_DEV2_PORT_STRAP7_BASE_IDX 5
#define regRCC_DEV2_PORT_STRAP8 0xc508
#define regRCC_DEV2_PORT_STRAP8_BASE_IDX 5
#define regRCC_DEV2_PORT_STRAP9 0xc509
#define regRCC_DEV2_PORT_STRAP9_BASE_IDX 5
#define regRCC_DEV2_PORT_STRAP10 0xc50a
#define regRCC_DEV2_PORT_STRAP10_BASE_IDX 5
#define regRCC_DEV2_PORT_STRAP11 0xc50b
#define regRCC_DEV2_PORT_STRAP11_BASE_IDX 5
#define regRCC_DEV2_PORT_STRAP12 0xc50c
#define regRCC_DEV2_PORT_STRAP12_BASE_IDX 5
#define regRCC_DEV2_PORT_STRAP13 0xc50d
#define regRCC_DEV2_PORT_STRAP13_BASE_IDX 5
#define regRCC_DEV2_PORT_STRAP14 0xc50e
#define regRCC_DEV2_PORT_STRAP14_BASE_IDX 5
#define regRCC_DEV2_PORT_STRAP15 0xc50f
#define regRCC_DEV2_PORT_STRAP15_BASE_IDX 5
#define regRCC_DEV2_PORT_STRAP16 0xc510
#define regRCC_DEV2_PORT_STRAP16_BASE_IDX 5
#define regRCC_STRAP1_RCC_BIF_STRAP0 0xc600
#define regRCC_STRAP1_RCC_BIF_STRAP0_BASE_IDX 5
#define regRCC_STRAP1_RCC_BIF_STRAP1 0xc601
#define regRCC_STRAP1_RCC_BIF_STRAP1_BASE_IDX 5
#define regRCC_STRAP1_RCC_BIF_STRAP2 0xc602
#define regRCC_STRAP1_RCC_BIF_STRAP2_BASE_IDX 5
#define regRCC_STRAP1_RCC_BIF_STRAP3 0xc603
#define regRCC_STRAP1_RCC_BIF_STRAP3_BASE_IDX 5
#define regRCC_STRAP1_RCC_BIF_STRAP4 0xc604
#define regRCC_STRAP1_RCC_BIF_STRAP4_BASE_IDX 5
#define regRCC_STRAP1_RCC_BIF_STRAP5 0xc605
#define regRCC_STRAP1_RCC_BIF_STRAP5_BASE_IDX 5
#define regRCC_STRAP1_RCC_BIF_STRAP6 0xc606
#define regRCC_STRAP1_RCC_BIF_STRAP6_BASE_IDX 5
#define regRCC_STRAP1_RCC_BIF_STRAP7 0xc607
#define regRCC_STRAP1_RCC_BIF_STRAP7_BASE_IDX 5
#define regRCC_STRAP1_RCC_BIF_STRAP8 0xc608
#define regRCC_STRAP1_RCC_BIF_STRAP8_BASE_IDX 5
#define regRCC_STRAP1_RCC_BIF_STRAP9 0xc609
#define regRCC_STRAP1_RCC_BIF_STRAP9_BASE_IDX 5
#define regRCC_STRAP1_RCC_BIF_STRAP10 0xc60a
#define regRCC_STRAP1_RCC_BIF_STRAP10_BASE_IDX 5
#define regRCC_STRAP1_RCC_BIF_STRAP11 0xc60b
#define regRCC_STRAP1_RCC_BIF_STRAP11_BASE_IDX 5
#define regRCC_STRAP1_RCC_BIF_STRAP12 0xc60c
#define regRCC_STRAP1_RCC_BIF_STRAP12_BASE_IDX 5
#define regRCC_STRAP1_RCC_BIF_STRAP13 0xc60d
#define regRCC_STRAP1_RCC_BIF_STRAP13_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0 0xd000
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1 0xd001
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2 0xd002
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3 0xd003
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4 0xd004
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5 0xd005
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8 0xd008
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9 0xd009
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13 0xd00d
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14 0xd00e
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15 0xd00f
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16 0xd010
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17 0xd011
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18 0xd012
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP19 0xd013
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP19_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP22 0xd016
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP22_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP23 0xd017
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP23_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP24 0xd018
#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP24_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0 0xd080
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP1 0xd081
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP1_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2 0xd082
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3 0xd083
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4 0xd084
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5 0xd085
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6 0xd086
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7 0xd087
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP8 0xd088
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP8_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP9 0xd089
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP9_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP10 0xd08a
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP10_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP11 0xd08b
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP11_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP12 0xd08c
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP12_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP13 0xd08d
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP13_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP14 0xd08e
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP14_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP15 0xd08f
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP15_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP16 0xd090
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP16_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP17 0xd091
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP17_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP18 0xd092
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP18_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP19 0xd093
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP19_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20 0xd094
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21 0xd095
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23 0xd097
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23_BASE_IDX 5
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24 0xd098
#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24_BASE_IDX 5
#define regRCC_DEV0_EPF2_STRAP0 0xd100
#define regRCC_DEV0_EPF2_STRAP0_BASE_IDX 5
#define regRCC_DEV0_EPF2_STRAP2 0xd102
#define regRCC_DEV0_EPF2_STRAP2_BASE_IDX 5
#define regRCC_DEV0_EPF2_STRAP3 0xd103
#define regRCC_DEV0_EPF2_STRAP3_BASE_IDX 5
#define regRCC_DEV0_EPF2_STRAP4 0xd104
#define regRCC_DEV0_EPF2_STRAP4_BASE_IDX 5
#define regRCC_DEV0_EPF2_STRAP5 0xd105
#define regRCC_DEV0_EPF2_STRAP5_BASE_IDX 5
#define regRCC_DEV0_EPF2_STRAP6 0xd106
#define regRCC_DEV0_EPF2_STRAP6_BASE_IDX 5
#define regRCC_DEV0_EPF2_STRAP7 0xd107
#define regRCC_DEV0_EPF2_STRAP7_BASE_IDX 5
#define regRCC_DEV0_EPF2_STRAP9 0xd109
#define regRCC_DEV0_EPF2_STRAP9_BASE_IDX 5
#define regRCC_DEV0_EPF2_STRAP10 0xd10a
#define regRCC_DEV0_EPF2_STRAP10_BASE_IDX 5
#define regRCC_DEV0_EPF2_STRAP11 0xd10b
#define regRCC_DEV0_EPF2_STRAP11_BASE_IDX 5
#define regRCC_DEV0_EPF2_STRAP12 0xd10c
#define regRCC_DEV0_EPF2_STRAP12_BASE_IDX 5
#define regRCC_DEV0_EPF2_STRAP13 0xd10d
#define regRCC_DEV0_EPF2_STRAP13_BASE_IDX 5
#define regRCC_DEV0_EPF2_STRAP14 0xd10e
#define regRCC_DEV0_EPF2_STRAP14_BASE_IDX 5
#define regRCC_DEV0_EPF2_STRAP15 0xd10f
#define regRCC_DEV0_EPF2_STRAP15_BASE_IDX 5
#define regRCC_DEV0_EPF2_STRAP16 0xd110
#define regRCC_DEV0_EPF2_STRAP16_BASE_IDX 5
#define regRCC_DEV0_EPF2_STRAP20 0xd114
#define regRCC_DEV0_EPF2_STRAP20_BASE_IDX 5
#define regRCC_DEV0_EPF3_STRAP0 0xd180
#define regRCC_DEV0_EPF3_STRAP0_BASE_IDX 5
#define regRCC_DEV0_EPF3_STRAP2 0xd182
#define regRCC_DEV0_EPF3_STRAP2_BASE_IDX 5
#define regRCC_DEV0_EPF3_STRAP3 0xd183
#define regRCC_DEV0_EPF3_STRAP3_BASE_IDX 5
#define regRCC_DEV0_EPF3_STRAP4 0xd184
#define regRCC_DEV0_EPF3_STRAP4_BASE_IDX 5
#define regRCC_DEV0_EPF3_STRAP5 0xd185
#define regRCC_DEV0_EPF3_STRAP5_BASE_IDX 5
#define regRCC_DEV0_EPF3_STRAP6 0xd186
#define regRCC_DEV0_EPF3_STRAP6_BASE_IDX 5
#define regRCC_DEV0_EPF3_STRAP7 0xd187
#define regRCC_DEV0_EPF3_STRAP7_BASE_IDX 5
#define regRCC_DEV0_EPF3_STRAP9 0xd189
#define regRCC_DEV0_EPF3_STRAP9_BASE_IDX 5
#define regRCC_DEV0_EPF3_STRAP10 0xd18a
#define regRCC_DEV0_EPF3_STRAP10_BASE_IDX 5
#define regRCC_DEV0_EPF3_STRAP11 0xd18b
#define regRCC_DEV0_EPF3_STRAP11_BASE_IDX 5
#define regRCC_DEV0_EPF3_STRAP12 0xd18c
#define regRCC_DEV0_EPF3_STRAP12_BASE_IDX 5
#define regRCC_DEV0_EPF3_STRAP13 0xd18d
#define regRCC_DEV0_EPF3_STRAP13_BASE_IDX 5
#define regRCC_DEV0_EPF3_STRAP14 0xd18e
#define regRCC_DEV0_EPF3_STRAP14_BASE_IDX 5
#define regRCC_DEV0_EPF3_STRAP15 0xd18f
#define regRCC_DEV0_EPF3_STRAP15_BASE_IDX 5
#define regRCC_DEV0_EPF3_STRAP16 0xd190
#define regRCC_DEV0_EPF3_STRAP16_BASE_IDX 5
#define regRCC_DEV0_EPF3_STRAP20 0xd194
#define regRCC_DEV0_EPF3_STRAP20_BASE_IDX 5
#define regRCC_DEV0_EPF4_STRAP0 0xd200
#define regRCC_DEV0_EPF4_STRAP0_BASE_IDX 5
#define regRCC_DEV0_EPF4_STRAP2 0xd202
#define regRCC_DEV0_EPF4_STRAP2_BASE_IDX 5
#define regRCC_DEV0_EPF4_STRAP3 0xd203
#define regRCC_DEV0_EPF4_STRAP3_BASE_IDX 5
#define regRCC_DEV0_EPF4_STRAP4 0xd204
#define regRCC_DEV0_EPF4_STRAP4_BASE_IDX 5
#define regRCC_DEV0_EPF4_STRAP5 0xd205
#define regRCC_DEV0_EPF4_STRAP5_BASE_IDX 5
#define regRCC_DEV0_EPF4_STRAP6 0xd206
#define regRCC_DEV0_EPF4_STRAP6_BASE_IDX 5
#define regRCC_DEV0_EPF4_STRAP7 0xd207
#define regRCC_DEV0_EPF4_STRAP7_BASE_IDX 5
#define regRCC_DEV0_EPF4_STRAP9 0xd209
#define regRCC_DEV0_EPF4_STRAP9_BASE_IDX 5
#define regRCC_DEV0_EPF4_STRAP13 0xd20d
#define regRCC_DEV0_EPF4_STRAP13_BASE_IDX 5
#define regRCC_DEV0_EPF4_STRAP14 0xd20e
#define regRCC_DEV0_EPF4_STRAP14_BASE_IDX 5
#define regRCC_DEV0_EPF4_STRAP15 0xd20f
#define regRCC_DEV0_EPF4_STRAP15_BASE_IDX 5
#define regRCC_DEV0_EPF4_STRAP16 0xd210
#define regRCC_DEV0_EPF4_STRAP16_BASE_IDX 5
#define regRCC_DEV0_EPF5_STRAP0 0xd280
#define regRCC_DEV0_EPF5_STRAP0_BASE_IDX 5
#define regRCC_DEV0_EPF5_STRAP2 0xd282
#define regRCC_DEV0_EPF5_STRAP2_BASE_IDX 5
#define regRCC_DEV0_EPF5_STRAP3 0xd283
#define regRCC_DEV0_EPF5_STRAP3_BASE_IDX 5
#define regRCC_DEV0_EPF5_STRAP4 0xd284
#define regRCC_DEV0_EPF5_STRAP4_BASE_IDX 5
#define regRCC_DEV0_EPF5_STRAP5 0xd285
#define regRCC_DEV0_EPF5_STRAP5_BASE_IDX 5
#define regRCC_DEV0_EPF5_STRAP6 0xd286
#define regRCC_DEV0_EPF5_STRAP6_BASE_IDX 5
#define regRCC_DEV0_EPF5_STRAP7 0xd287
#define regRCC_DEV0_EPF5_STRAP7_BASE_IDX 5
#define regRCC_DEV0_EPF5_STRAP9 0xd289
#define regRCC_DEV0_EPF5_STRAP9_BASE_IDX 5
#define regRCC_DEV0_EPF5_STRAP13 0xd28d
#define regRCC_DEV0_EPF5_STRAP13_BASE_IDX 5
#define regRCC_DEV0_EPF5_STRAP14 0xd28e
#define regRCC_DEV0_EPF5_STRAP14_BASE_IDX 5
#define regRCC_DEV0_EPF5_STRAP15 0xd28f
#define regRCC_DEV0_EPF5_STRAP15_BASE_IDX 5
#define regRCC_DEV0_EPF5_STRAP16 0xd290
#define regRCC_DEV0_EPF5_STRAP16_BASE_IDX 5
#define regRCC_DEV0_EPF6_STRAP0 0xd300
#define regRCC_DEV0_EPF6_STRAP0_BASE_IDX 5
#define regRCC_DEV0_EPF6_STRAP2 0xd302
#define regRCC_DEV0_EPF6_STRAP2_BASE_IDX 5
#define regRCC_DEV0_EPF6_STRAP3 0xd303
#define regRCC_DEV0_EPF6_STRAP3_BASE_IDX 5
#define regRCC_DEV0_EPF6_STRAP4 0xd304
#define regRCC_DEV0_EPF6_STRAP4_BASE_IDX 5
#define regRCC_DEV0_EPF6_STRAP5 0xd305
#define regRCC_DEV0_EPF6_STRAP5_BASE_IDX 5
#define regRCC_DEV0_EPF6_STRAP6 0xd306
#define regRCC_DEV0_EPF6_STRAP6_BASE_IDX 5
#define regRCC_DEV0_EPF6_STRAP7 0xd307
#define regRCC_DEV0_EPF6_STRAP7_BASE_IDX 5
#define regRCC_DEV0_EPF6_STRAP9 0xd309
#define regRCC_DEV0_EPF6_STRAP9_BASE_IDX 5
#define regRCC_DEV0_EPF6_STRAP13 0xd30d
#define regRCC_DEV0_EPF6_STRAP13_BASE_IDX 5
#define regRCC_DEV0_EPF6_STRAP14 0xd30e
#define regRCC_DEV0_EPF6_STRAP14_BASE_IDX 5
#define regRCC_DEV0_EPF6_STRAP15 0xd30f
#define regRCC_DEV0_EPF6_STRAP15_BASE_IDX 5
#define regRCC_DEV0_EPF6_STRAP16 0xd310
#define regRCC_DEV0_EPF6_STRAP16_BASE_IDX 5
#define regRCC_DEV0_EPF7_STRAP0 0xd380
#define regRCC_DEV0_EPF7_STRAP0_BASE_IDX 5
#define regRCC_DEV0_EPF7_STRAP2 0xd382
#define regRCC_DEV0_EPF7_STRAP2_BASE_IDX 5
#define regRCC_DEV0_EPF7_STRAP3 0xd383
#define regRCC_DEV0_EPF7_STRAP3_BASE_IDX 5
#define regRCC_DEV0_EPF7_STRAP4 0xd384
#define regRCC_DEV0_EPF7_STRAP4_BASE_IDX 5
#define regRCC_DEV0_EPF7_STRAP5 0xd385
#define regRCC_DEV0_EPF7_STRAP5_BASE_IDX 5
#define regRCC_DEV0_EPF7_STRAP6 0xd386
#define regRCC_DEV0_EPF7_STRAP6_BASE_IDX 5
#define regRCC_DEV0_EPF7_STRAP9 0xd389
#define regRCC_DEV0_EPF7_STRAP9_BASE_IDX 5
#define regRCC_DEV0_EPF7_STRAP13 0xd38d
#define regRCC_DEV0_EPF7_STRAP13_BASE_IDX 5
#define regRCC_DEV0_EPF7_STRAP14 0xd38e
#define regRCC_DEV0_EPF7_STRAP14_BASE_IDX 5
#define regRCC_DEV0_EPF7_STRAP15 0xd38f
#define regRCC_DEV0_EPF7_STRAP15_BASE_IDX 5
#define regRCC_DEV0_EPF7_STRAP16 0xd390
#define regRCC_DEV0_EPF7_STRAP16_BASE_IDX 5
#define regRCC_DEV1_EPF0_STRAP0 0xd400
#define regRCC_DEV1_EPF0_STRAP0_BASE_IDX 5
#define regRCC_DEV1_EPF0_STRAP2 0xd402
#define regRCC_DEV1_EPF0_STRAP2_BASE_IDX 5
#define regRCC_DEV1_EPF0_STRAP3 0xd403
#define regRCC_DEV1_EPF0_STRAP3_BASE_IDX 5
#define regRCC_DEV1_EPF0_STRAP4 0xd404
#define regRCC_DEV1_EPF0_STRAP4_BASE_IDX 5
#define regRCC_DEV1_EPF0_STRAP5 0xd405
#define regRCC_DEV1_EPF0_STRAP5_BASE_IDX 5
#define regRCC_DEV1_EPF0_STRAP6 0xd406
#define regRCC_DEV1_EPF0_STRAP6_BASE_IDX 5
#define regRCC_DEV1_EPF0_STRAP9 0xd409
#define regRCC_DEV1_EPF0_STRAP9_BASE_IDX 5
#define regRCC_DEV1_EPF0_STRAP13 0xd40d
#define regRCC_DEV1_EPF0_STRAP13_BASE_IDX 5
#define regRCC_DEV1_EPF0_STRAP14 0xd40e
#define regRCC_DEV1_EPF0_STRAP14_BASE_IDX 5
#define regRCC_DEV1_EPF0_STRAP15 0xd40f
#define regRCC_DEV1_EPF0_STRAP15_BASE_IDX 5
#define regRCC_DEV1_EPF0_STRAP16 0xd410
#define regRCC_DEV1_EPF0_STRAP16_BASE_IDX 5
#define regRCC_DEV1_EPF1_STRAP0 0xd480
#define regRCC_DEV1_EPF1_STRAP0_BASE_IDX 5
#define regRCC_DEV1_EPF1_STRAP1 0xd481
#define regRCC_DEV1_EPF1_STRAP1_BASE_IDX 5
#define regRCC_DEV1_EPF1_STRAP2 0xd482
#define regRCC_DEV1_EPF1_STRAP2_BASE_IDX 5
#define regRCC_DEV1_EPF1_STRAP3 0xd483
#define regRCC_DEV1_EPF1_STRAP3_BASE_IDX 5
#define regRCC_DEV1_EPF1_STRAP4 0xd484
#define regRCC_DEV1_EPF1_STRAP4_BASE_IDX 5
#define regRCC_DEV1_EPF1_STRAP5 0xd485
#define regRCC_DEV1_EPF1_STRAP5_BASE_IDX 5
#define regRCC_DEV1_EPF1_STRAP6 0xd486
#define regRCC_DEV1_EPF1_STRAP6_BASE_IDX 5
#define regRCC_DEV1_EPF1_STRAP7 0xd487
#define regRCC_DEV1_EPF1_STRAP7_BASE_IDX 5
#define regRCC_DEV1_EPF1_STRAP8 0xd488
#define regRCC_DEV1_EPF1_STRAP8_BASE_IDX 5
#define regRCC_DEV1_EPF1_STRAP9 0xd489
#define regRCC_DEV1_EPF1_STRAP9_BASE_IDX 5
#define regRCC_DEV1_EPF1_STRAP13 0xd48d
#define regRCC_DEV1_EPF1_STRAP13_BASE_IDX 5
#define regRCC_DEV1_EPF1_STRAP14 0xd48e
#define regRCC_DEV1_EPF1_STRAP14_BASE_IDX 5
#define regRCC_DEV1_EPF1_STRAP15 0xd48f
#define regRCC_DEV1_EPF1_STRAP15_BASE_IDX 5
#define regRCC_DEV1_EPF1_STRAP16 0xd490
#define regRCC_DEV1_EPF1_STRAP16_BASE_IDX 5
#define regRCC_DEV1_EPF1_STRAP17 0xd491
#define regRCC_DEV1_EPF1_STRAP17_BASE_IDX 5
#define regRCC_DEV1_EPF1_STRAP18 0xd492
#define regRCC_DEV1_EPF1_STRAP18_BASE_IDX 5
#define regRCC_DEV1_EPF1_STRAP19 0xd493
#define regRCC_DEV1_EPF1_STRAP19_BASE_IDX 5
#define regRCC_DEV1_EPF1_STRAP20 0xd494
#define regRCC_DEV1_EPF1_STRAP20_BASE_IDX 5
#define regRCC_DEV1_EPF1_STRAP21 0xd495
#define regRCC_DEV1_EPF1_STRAP21_BASE_IDX 5
#define regRCC_DEV1_EPF2_STRAP0 0xd500
#define regRCC_DEV1_EPF2_STRAP0_BASE_IDX 5
#define regRCC_DEV1_EPF2_STRAP1 0xd501
#define regRCC_DEV1_EPF2_STRAP1_BASE_IDX 5
#define regRCC_DEV1_EPF2_STRAP2 0xd502
#define regRCC_DEV1_EPF2_STRAP2_BASE_IDX 5
#define regRCC_DEV1_EPF2_STRAP3 0xd503
#define regRCC_DEV1_EPF2_STRAP3_BASE_IDX 5
#define regRCC_DEV1_EPF2_STRAP4 0xd504
#define regRCC_DEV1_EPF2_STRAP4_BASE_IDX 5
#define regRCC_DEV1_EPF2_STRAP5 0xd505
#define regRCC_DEV1_EPF2_STRAP5_BASE_IDX 5
#define regRCC_DEV1_EPF2_STRAP6 0xd506
#define regRCC_DEV1_EPF2_STRAP6_BASE_IDX 5
#define regRCC_DEV1_EPF2_STRAP7 0xd507
#define regRCC_DEV1_EPF2_STRAP7_BASE_IDX 5
#define regRCC_DEV1_EPF2_STRAP8 0xd508
#define regRCC_DEV1_EPF2_STRAP8_BASE_IDX 5
#define regRCC_DEV1_EPF2_STRAP9 0xd509
#define regRCC_DEV1_EPF2_STRAP9_BASE_IDX 5
#define regRCC_DEV1_EPF2_STRAP13 0xd50d
#define regRCC_DEV1_EPF2_STRAP13_BASE_IDX 5
#define regRCC_DEV1_EPF2_STRAP14 0xd50e
#define regRCC_DEV1_EPF2_STRAP14_BASE_IDX 5
#define regRCC_DEV1_EPF2_STRAP15 0xd50f
#define regRCC_DEV1_EPF2_STRAP15_BASE_IDX 5
#define regRCC_DEV1_EPF2_STRAP16 0xd510
#define regRCC_DEV1_EPF2_STRAP16_BASE_IDX 5
#define regRCC_DEV1_EPF2_STRAP17 0xd511
#define regRCC_DEV1_EPF2_STRAP17_BASE_IDX 5
#define regRCC_DEV1_EPF2_STRAP18 0xd512
#define regRCC_DEV1_EPF2_STRAP18_BASE_IDX 5
#define regRCC_DEV1_EPF2_STRAP19 0xd513
#define regRCC_DEV1_EPF2_STRAP19_BASE_IDX 5
#define regRCC_DEV1_EPF2_STRAP20 0xd514
#define regRCC_DEV1_EPF2_STRAP20_BASE_IDX 5
#define regRCC_DEV1_EPF2_STRAP21 0xd515
#define regRCC_DEV1_EPF2_STRAP21_BASE_IDX 5
#define regRCC_DEV1_EPF3_STRAP0 0xd580
#define regRCC_DEV1_EPF3_STRAP0_BASE_IDX 5
#define regRCC_DEV1_EPF3_STRAP2 0xd582
#define regRCC_DEV1_EPF3_STRAP2_BASE_IDX 5
#define regRCC_DEV1_EPF3_STRAP3 0xd583
#define regRCC_DEV1_EPF3_STRAP3_BASE_IDX 5
#define regRCC_DEV1_EPF3_STRAP4 0xd584
#define regRCC_DEV1_EPF3_STRAP4_BASE_IDX 5
#define regRCC_DEV1_EPF3_STRAP5 0xd585
#define regRCC_DEV1_EPF3_STRAP5_BASE_IDX 5
#define regRCC_DEV1_EPF3_STRAP6 0xd586
#define regRCC_DEV1_EPF3_STRAP6_BASE_IDX 5
#define regRCC_DEV1_EPF3_STRAP7 0xd587
#define regRCC_DEV1_EPF3_STRAP7_BASE_IDX 5
#define regRCC_DEV1_EPF3_STRAP13 0xd58d
#define regRCC_DEV1_EPF3_STRAP13_BASE_IDX 5
#define regRCC_DEV1_EPF3_STRAP14 0xd58e
#define regRCC_DEV1_EPF3_STRAP14_BASE_IDX 5
#define regRCC_DEV1_EPF3_STRAP15 0xd58f
#define regRCC_DEV1_EPF3_STRAP15_BASE_IDX 5
#define regRCC_DEV1_EPF3_STRAP16 0xd590
#define regRCC_DEV1_EPF3_STRAP16_BASE_IDX 5
#define regRCC_DEV1_EPF4_STRAP6 0xd606
#define regRCC_DEV1_EPF4_STRAP6_BASE_IDX 5
#define regRCC_DEV1_EPF5_STRAP6 0xd686
#define regRCC_DEV1_EPF5_STRAP6_BASE_IDX 5
#define regRCC_DEV1_EPF6_STRAP6 0xd706
#define regRCC_DEV1_EPF6_STRAP6_BASE_IDX 5
#define regRCC_DEV2_EPF0_STRAP0 0xd800
#define regRCC_DEV2_EPF0_STRAP0_BASE_IDX 5
#define regRCC_DEV2_EPF0_STRAP2 0xd802
#define regRCC_DEV2_EPF0_STRAP2_BASE_IDX 5
#define regRCC_DEV2_EPF0_STRAP3 0xd803
#define regRCC_DEV2_EPF0_STRAP3_BASE_IDX 5
#define regRCC_DEV2_EPF0_STRAP4 0xd804
#define regRCC_DEV2_EPF0_STRAP4_BASE_IDX 5
#define regRCC_DEV2_EPF0_STRAP5 0xd805
#define regRCC_DEV2_EPF0_STRAP5_BASE_IDX 5
#define regRCC_DEV2_EPF0_STRAP6 0xd806
#define regRCC_DEV2_EPF0_STRAP6_BASE_IDX 5
#define regRCC_DEV2_EPF0_STRAP7 0xd807
#define regRCC_DEV2_EPF0_STRAP7_BASE_IDX 5
#define regRCC_DEV2_EPF0_STRAP13 0xd80d
#define regRCC_DEV2_EPF0_STRAP13_BASE_IDX 5
#define regRCC_DEV2_EPF0_STRAP14 0xd80e
#define regRCC_DEV2_EPF0_STRAP14_BASE_IDX 5
#define regRCC_DEV2_EPF0_STRAP15 0xd80f
#define regRCC_DEV2_EPF0_STRAP15_BASE_IDX 5
#define regRCC_DEV2_EPF0_STRAP16 0xd810
#define regRCC_DEV2_EPF0_STRAP16_BASE_IDX 5
#define regRCC_DEV2_EPF0_STRAP18 0xd812
#define regRCC_DEV2_EPF0_STRAP18_BASE_IDX 5
#define regRCC_DEV2_EPF0_STRAP25 0xd819
#define regRCC_DEV2_EPF0_STRAP25_BASE_IDX 5
#define regRCC_DEV2_EPF0_STRAP26 0xd81a
#define regRCC_DEV2_EPF0_STRAP26_BASE_IDX 5
#define regRCC_DEV2_EPF1_STRAP0 0xd880
#define regRCC_DEV2_EPF1_STRAP0_BASE_IDX 5
#define regRCC_DEV2_EPF1_STRAP2 0xd882
#define regRCC_DEV2_EPF1_STRAP2_BASE_IDX 5
#define regRCC_DEV2_EPF1_STRAP3 0xd883
#define regRCC_DEV2_EPF1_STRAP3_BASE_IDX 5
#define regRCC_DEV2_EPF1_STRAP4 0xd884
#define regRCC_DEV2_EPF1_STRAP4_BASE_IDX 5
#define regRCC_DEV2_EPF1_STRAP5 0xd885
#define regRCC_DEV2_EPF1_STRAP5_BASE_IDX 5
#define regRCC_DEV2_EPF1_STRAP6 0xd886
#define regRCC_DEV2_EPF1_STRAP6_BASE_IDX 5
#define regRCC_DEV2_EPF1_STRAP7 0xd887
#define regRCC_DEV2_EPF1_STRAP7_BASE_IDX 5
#define regRCC_DEV2_EPF1_STRAP13 0xd88d
#define regRCC_DEV2_EPF1_STRAP13_BASE_IDX 5
#define regRCC_DEV2_EPF1_STRAP14 0xd88e
#define regRCC_DEV2_EPF1_STRAP14_BASE_IDX 5
#define regRCC_DEV2_EPF1_STRAP15 0xd88f
#define regRCC_DEV2_EPF1_STRAP15_BASE_IDX 5
#define regRCC_DEV2_EPF1_STRAP16 0xd890
#define regRCC_DEV2_EPF1_STRAP16_BASE_IDX 5
#define regRCC_DEV2_EPF2_STRAP0 0xd900
#define regRCC_DEV2_EPF2_STRAP0_BASE_IDX 5
#define regRCC_DEV2_EPF2_STRAP2 0xd902
#define regRCC_DEV2_EPF2_STRAP2_BASE_IDX 5
#define regRCC_DEV2_EPF2_STRAP3 0xd903
#define regRCC_DEV2_EPF2_STRAP3_BASE_IDX 5
#define regRCC_DEV2_EPF2_STRAP4 0xd904
#define regRCC_DEV2_EPF2_STRAP4_BASE_IDX 5
#define regRCC_DEV2_EPF2_STRAP5 0xd905
#define regRCC_DEV2_EPF2_STRAP5_BASE_IDX 5
#define regRCC_DEV2_EPF2_STRAP6 0xd906
#define regRCC_DEV2_EPF2_STRAP6_BASE_IDX 5
#define regRCC_DEV2_EPF2_STRAP7 0xd907
#define regRCC_DEV2_EPF2_STRAP7_BASE_IDX 5
#define regRCC_DEV2_EPF2_STRAP13 0xd90d
#define regRCC_DEV2_EPF2_STRAP13_BASE_IDX 5
#define regRCC_DEV2_EPF2_STRAP14 0xd90e
#define regRCC_DEV2_EPF2_STRAP14_BASE_IDX 5
#define regRCC_DEV2_EPF2_STRAP15 0xd90f
#define regRCC_DEV2_EPF2_STRAP15_BASE_IDX 5
#define regRCC_DEV2_EPF2_STRAP16 0xd910
#define regRCC_DEV2_EPF2_STRAP16_BASE_IDX 5
#define regRCC_DEV2_EPF3_STRAP0 0xd980
#define regRCC_DEV2_EPF3_STRAP0_BASE_IDX 5
#define regRCC_DEV2_EPF3_STRAP2 0xd982
#define regRCC_DEV2_EPF3_STRAP2_BASE_IDX 5
#define regRCC_DEV2_EPF3_STRAP3 0xd983
#define regRCC_DEV2_EPF3_STRAP3_BASE_IDX 5
#define regRCC_DEV2_EPF3_STRAP4 0xd984
#define regRCC_DEV2_EPF3_STRAP4_BASE_IDX 5
#define regRCC_DEV2_EPF3_STRAP5 0xd985
#define regRCC_DEV2_EPF3_STRAP5_BASE_IDX 5
#define regRCC_DEV2_EPF3_STRAP6 0xd986
#define regRCC_DEV2_EPF3_STRAP6_BASE_IDX 5
#define regRCC_DEV2_EPF3_STRAP7 0xd987
#define regRCC_DEV2_EPF3_STRAP7_BASE_IDX 5
#define regRCC_DEV2_EPF3_STRAP13 0xd98d
#define regRCC_DEV2_EPF3_STRAP13_BASE_IDX 5
#define regRCC_DEV2_EPF3_STRAP14 0xd98e
#define regRCC_DEV2_EPF3_STRAP14_BASE_IDX 5
#define regRCC_DEV2_EPF3_STRAP15 0xd98f
#define regRCC_DEV2_EPF3_STRAP15_BASE_IDX 5
#define regRCC_DEV2_EPF3_STRAP16 0xd990
#define regRCC_DEV2_EPF3_STRAP16_BASE_IDX 5
#define regRCC_DEV2_EPF4_STRAP0 0xda00
#define regRCC_DEV2_EPF4_STRAP0_BASE_IDX 5
#define regRCC_DEV2_EPF4_STRAP2 0xda02
#define regRCC_DEV2_EPF4_STRAP2_BASE_IDX 5
#define regRCC_DEV2_EPF4_STRAP3 0xda03
#define regRCC_DEV2_EPF4_STRAP3_BASE_IDX 5
#define regRCC_DEV2_EPF4_STRAP4 0xda04
#define regRCC_DEV2_EPF4_STRAP4_BASE_IDX 5
#define regRCC_DEV2_EPF4_STRAP5 0xda05
#define regRCC_DEV2_EPF4_STRAP5_BASE_IDX 5
#define regRCC_DEV2_EPF4_STRAP6 0xda06
#define regRCC_DEV2_EPF4_STRAP6_BASE_IDX 5
#define regRCC_DEV2_EPF4_STRAP7 0xda07
#define regRCC_DEV2_EPF4_STRAP7_BASE_IDX 5
#define regRCC_DEV2_EPF4_STRAP13 0xda0d
#define regRCC_DEV2_EPF4_STRAP13_BASE_IDX 5
#define regRCC_DEV2_EPF4_STRAP14 0xda0e
#define regRCC_DEV2_EPF4_STRAP14_BASE_IDX 5
#define regRCC_DEV2_EPF4_STRAP15 0xda0f
#define regRCC_DEV2_EPF4_STRAP15_BASE_IDX 5
#define regRCC_DEV2_EPF4_STRAP16 0xda10
#define regRCC_DEV2_EPF4_STRAP16_BASE_IDX 5
#define regRCC_DEV2_EPF5_STRAP0 0xda80
#define regRCC_DEV2_EPF5_STRAP0_BASE_IDX 5
#define regRCC_DEV2_EPF5_STRAP2 0xda82
#define regRCC_DEV2_EPF5_STRAP2_BASE_IDX 5
#define regRCC_DEV2_EPF5_STRAP3 0xda83
#define regRCC_DEV2_EPF5_STRAP3_BASE_IDX 5
#define regRCC_DEV2_EPF5_STRAP4 0xda84
#define regRCC_DEV2_EPF5_STRAP4_BASE_IDX 5
#define regRCC_DEV2_EPF5_STRAP5 0xda85
#define regRCC_DEV2_EPF5_STRAP5_BASE_IDX 5
#define regRCC_DEV2_EPF5_STRAP6 0xda86
#define regRCC_DEV2_EPF5_STRAP6_BASE_IDX 5
#define regRCC_DEV2_EPF5_STRAP7 0xda87
#define regRCC_DEV2_EPF5_STRAP7_BASE_IDX 5
#define regRCC_DEV2_EPF5_STRAP13 0xda8d
#define regRCC_DEV2_EPF5_STRAP13_BASE_IDX 5
#define regRCC_DEV2_EPF5_STRAP14 0xda8e
#define regRCC_DEV2_EPF5_STRAP14_BASE_IDX 5
#define regRCC_DEV2_EPF5_STRAP15 0xda8f
#define regRCC_DEV2_EPF5_STRAP15_BASE_IDX 5
#define regRCC_DEV2_EPF5_STRAP16 0xda90
#define regRCC_DEV2_EPF5_STRAP16_BASE_IDX 5
#define regRCC_DEV2_EPF6_STRAP0 0xdb00
#define regRCC_DEV2_EPF6_STRAP0_BASE_IDX 5
#define regRCC_DEV2_EPF6_STRAP2 0xdb02
#define regRCC_DEV2_EPF6_STRAP2_BASE_IDX 5
#define regRCC_DEV2_EPF6_STRAP3 0xdb03
#define regRCC_DEV2_EPF6_STRAP3_BASE_IDX 5
#define regRCC_DEV2_EPF6_STRAP4 0xdb04
#define regRCC_DEV2_EPF6_STRAP4_BASE_IDX 5
#define regRCC_DEV2_EPF6_STRAP5 0xdb05
#define regRCC_DEV2_EPF6_STRAP5_BASE_IDX 5
#define regRCC_DEV2_EPF6_STRAP6 0xdb06
#define regRCC_DEV2_EPF6_STRAP6_BASE_IDX 5
#define regRCC_DEV2_EPF6_STRAP7 0xdb07
#define regRCC_DEV2_EPF6_STRAP7_BASE_IDX 5
#define regRCC_DEV2_EPF6_STRAP13 0xdb0d
#define regRCC_DEV2_EPF6_STRAP13_BASE_IDX 5
#define regRCC_DEV2_EPF6_STRAP14 0xdb0e
#define regRCC_DEV2_EPF6_STRAP14_BASE_IDX 5
#define regRCC_DEV2_EPF6_STRAP15 0xdb0f
#define regRCC_DEV2_EPF6_STRAP15_BASE_IDX 5
#define regRCC_DEV2_EPF6_STRAP16 0xdb10
#define regRCC_DEV2_EPF6_STRAP16_BASE_IDX 5
#define regHARD_RST_CTRL 0xe000
#define regHARD_RST_CTRL_BASE_IDX 5
#define regSELF_SOFT_RST 0xe002
#define regSELF_SOFT_RST_BASE_IDX 5
#define regBIF_GFX_DRV_VPU_RST 0xe003
#define regBIF_GFX_DRV_VPU_RST_BASE_IDX 5
#define regBIF_RST_MISC_CTRL 0xe004
#define regBIF_RST_MISC_CTRL_BASE_IDX 5
#define regBIF_RST_MISC_CTRL2 0xe005
#define regBIF_RST_MISC_CTRL2_BASE_IDX 5
#define regBIF_RST_MISC_CTRL3 0xe006
#define regBIF_RST_MISC_CTRL3_BASE_IDX 5
#define regDEV0_PF0_FLR_RST_CTRL 0xe008
#define regDEV0_PF0_FLR_RST_CTRL_BASE_IDX 5
#define regDEV0_PF1_FLR_RST_CTRL 0xe009
#define regDEV0_PF1_FLR_RST_CTRL_BASE_IDX 5
#define regBIF_INST_RESET_INTR_STS 0xe010
#define regBIF_INST_RESET_INTR_STS_BASE_IDX 5
#define regBIF_PF_FLR_INTR_STS 0xe011
#define regBIF_PF_FLR_INTR_STS_BASE_IDX 5
#define regBIF_D3HOTD0_INTR_STS 0xe012
#define regBIF_D3HOTD0_INTR_STS_BASE_IDX 5
#define regBIF_POWER_INTR_STS 0xe014
#define regBIF_POWER_INTR_STS_BASE_IDX 5
#define regBIF_PF_DSTATE_INTR_STS 0xe015
#define regBIF_PF_DSTATE_INTR_STS_BASE_IDX 5
#define regSELF_SOFT_RST_2 0xe016
#define regSELF_SOFT_RST_2_BASE_IDX 5
#define regSION_SDP_PORT_RST 0xe017
#define regSION_SDP_PORT_RST_BASE_IDX 5
#define regBIF_INST_RESET_INTR_MASK 0xe020
#define regBIF_INST_RESET_INTR_MASK_BASE_IDX 5
#define regBIF_PF_FLR_INTR_MASK 0xe021
#define regBIF_PF_FLR_INTR_MASK_BASE_IDX 5
#define regBIF_D3HOTD0_INTR_MASK 0xe022
#define regBIF_D3HOTD0_INTR_MASK_BASE_IDX 5
#define regBIF_POWER_INTR_MASK 0xe024
#define regBIF_POWER_INTR_MASK_BASE_IDX 5
#define regBIF_PF_DSTATE_INTR_MASK 0xe025
#define regBIF_PF_DSTATE_INTR_MASK_BASE_IDX 5
#define regBIF_DEV0_PF0_VF_FLR_INTR_MASK 0xe028
#define regBIF_DEV0_PF0_VF_FLR_INTR_MASK_BASE_IDX 5
#define regBIF_DEV0_PF1_VF_FLR_INTR_MASK 0xe029
#define regBIF_DEV0_PF1_VF_FLR_INTR_MASK_BASE_IDX 5
#define regBIF_PF_FLR_RST 0xe040
#define regBIF_PF_FLR_RST_BASE_IDX 5
#define regBIF_PF_FLR_PROTECT 0xe042
#define regBIF_PF_FLR_PROTECT_BASE_IDX 5
#define regBIF_PF_FLR_PROTECT3 0xe044
#define regBIF_PF_FLR_PROTECT3_BASE_IDX 5
#define regBIF_DEV0_PF0_DSTATE_VALUE 0xe050
#define regBIF_DEV0_PF0_DSTATE_VALUE_BASE_IDX 5
#define regBIF_DEV0_PF1_DSTATE_VALUE 0xe051
#define regBIF_DEV0_PF1_DSTATE_VALUE_BASE_IDX 5
#define regGFX_RST_CNTL_IND0 0xe05d
#define regGFX_RST_CNTL_IND0_BASE_IDX 5
#define regGFX_RST_CNTL_SOFT_PF 0xe05e
#define regGFX_RST_CNTL_SOFT_PF_BASE_IDX 5
#define regGFX_RST_CNTL_IND1 0xe05f
#define regGFX_RST_CNTL_IND1_BASE_IDX 5
#define regGFX_RST_CNTL_IND2 0xe060
#define regGFX_RST_CNTL_IND2_BASE_IDX 5
#define regGFX_RST_CNTL_IND3 0xe061
#define regGFX_RST_CNTL_IND3_BASE_IDX 5
#define regGFX_RST_CNTL_IND4 0xe062
#define regGFX_RST_CNTL_IND4_BASE_IDX 5
#define regGFX_RST_CNTL_IND5 0xe063
#define regGFX_RST_CNTL_IND5_BASE_IDX 5
#define regGFX_RST_CNTL_IND6 0xe064
#define regGFX_RST_CNTL_IND6_BASE_IDX 5
#define regGFX_RST_CNTL_IND7 0xe065
#define regGFX_RST_CNTL_IND7_BASE_IDX 5
#define regGFX_RST_CNTL_IND8 0xe066
#define regGFX_RST_CNTL_IND8_BASE_IDX 5
#define regDEV0_PF0_D3HOTD0_RST_CTRL 0xe07e
#define regDEV0_PF0_D3HOTD0_RST_CTRL_BASE_IDX 5
#define regDEV0_PF1_D3HOTD0_RST_CTRL 0xe07f
#define regDEV0_PF1_D3HOTD0_RST_CTRL_BASE_IDX 5
#define regBIF_DEV0_PF0_VF_FLR_PROTECT 0xe086
#define regBIF_DEV0_PF0_VF_FLR_PROTECT_BASE_IDX 5
#define regBIF_DEV0_PF1_VF_FLR_PROTECT 0xe087
#define regBIF_DEV0_PF1_VF_FLR_PROTECT_BASE_IDX 5
#define regBIF_SRIOVEN_SET_INTR_STS 0xe088
#define regBIF_SRIOVEN_SET_INTR_STS_BASE_IDX 5
#define regBIF_SRIOVEN_CLR_INTR_STS 0xe089
#define regBIF_SRIOVEN_CLR_INTR_STS_BASE_IDX 5
#define regBIF_SRIOVEN_SET_INTR_MASK 0xe08a
#define regBIF_SRIOVEN_SET_INTR_MASK_BASE_IDX 5
#define regBIF_SRIOVEN_CLR_INTR_MASK 0xe08b
#define regBIF_SRIOVEN_CLR_INTR_MASK_BASE_IDX 5
#define regBIF_PORT0_DSTATE_VALUE 0xe230
#define regBIF_PORT0_DSTATE_VALUE_BASE_IDX 5
#define regBIF_DEV0_PF0_RST_VF_FLR_IDLE 0xe2c4
#define regBIF_DEV0_PF0_RST_VF_FLR_IDLE_BASE_IDX 5
#define regBIF_DEV0_PF1_RST_VF_FLR_IDLE 0xe2c5
#define regBIF_DEV0_PF1_RST_VF_FLR_IDLE_BASE_IDX 5
#define regBIF_DEV0_PF0_VF_FLR_INTR_STS 0xe2c8
#define regBIF_DEV0_PF0_VF_FLR_INTR_STS_BASE_IDX 5
#define regBIF_DEV0_PF1_VF_FLR_INTR_STS 0xe2c9
#define regBIF_DEV0_PF1_VF_FLR_INTR_STS_BASE_IDX 5
#define regBIF_DEV0_PF0_VF_FLR_RST 0xe2cc
#define regBIF_DEV0_PF0_VF_FLR_RST_BASE_IDX 5
#define regBIF_DEV0_PF1_VF_FLR_RST 0xe2cd
#define regBIF_DEV0_PF1_VF_FLR_RST_BASE_IDX 5
#define regDOE_PRV_CTRL0_DEV0F0 0xc806
#define regDOE_PRV_CTRL0_DEV0F0_BASE_IDX 5
#define regDOE_PRV_CMD_DEV0F0 0xc807
#define regDOE_PRV_CMD_DEV0F0_BASE_IDX 5
#define regDOE_PRV_WDATA_DEV0F0 0xc808
#define regDOE_PRV_WDATA_DEV0F0_BASE_IDX 5
#define regDOE_PRV_STS_DEV0F0 0xc809
#define regDOE_PRV_STS_DEV0F0_BASE_IDX 5
#define regDOE_PRV_RDATA_DEV0F0 0xc80a
#define regDOE_PRV_RDATA_DEV0F0_BASE_IDX 5
#define regNBIF_RC_INTR_CNTL 0xc81b
#define regNBIF_RC_INTR_CNTL_BASE_IDX 5
#define regBIF_DEV0_PF0_TDISP_CNTL 0xc8c0
#define regBIF_DEV0_PF0_TDISP_CNTL_BASE_IDX 5
#define regBIF_DEV0_PF1_TDISP_CNTL 0xc8c1
#define regBIF_DEV0_PF1_TDISP_CNTL_BASE_IDX 5
#define regBIF_DEV0_PF0_VF0_TDISP_CNTL 0xc8d0
#define regBIF_DEV0_PF0_VF0_TDISP_CNTL_BASE_IDX 5
#define regBIF_DEV0_PF0_VF1_TDISP_CNTL 0xc8d1
#define regBIF_DEV0_PF0_VF1_TDISP_CNTL_BASE_IDX 5
#define regBIF_DEV0_PF0_VF2_TDISP_CNTL 0xc8d2
#define regBIF_DEV0_PF0_VF2_TDISP_CNTL_BASE_IDX 5
#define regBIF_DEV0_PF0_VF3_TDISP_CNTL 0xc8d3
#define regBIF_DEV0_PF0_VF3_TDISP_CNTL_BASE_IDX 5
#define regBIF_DEV0_PF0_VF4_TDISP_CNTL 0xc8d4
#define regBIF_DEV0_PF0_VF4_TDISP_CNTL_BASE_IDX 5
#define regBIF_DEV0_PF0_VF5_TDISP_CNTL 0xc8d5
#define regBIF_DEV0_PF0_VF5_TDISP_CNTL_BASE_IDX 5
#define regBIF_DEV0_PF0_VF6_TDISP_CNTL 0xc8d6
#define regBIF_DEV0_PF0_VF6_TDISP_CNTL_BASE_IDX 5
#define regBIF_DEV0_PF0_VF7_TDISP_CNTL 0xc8d7
#define regBIF_DEV0_PF0_VF7_TDISP_CNTL_BASE_IDX 5
#define regBIF_DEV0_PF1_VF0_TDISP_CNTL 0xc8d8
#define regBIF_DEV0_PF1_VF0_TDISP_CNTL_BASE_IDX 5
#define regBIF_TDISP_ERROR_DEV0_PF0_INST0 0xc9d0
#define regBIF_TDISP_ERROR_DEV0_PF0_INST0_BASE_IDX 5
#define regBIF_TDISP_ERROR_DEV0_PF1_INST0 0xc9d1
#define regBIF_TDISP_ERROR_DEV0_PF1_INST0_BASE_IDX 5
#define regBIF_TDISP_UNLOCKED_DEV0_PF0_INST0 0xc9d8
#define regBIF_TDISP_UNLOCKED_DEV0_PF0_INST0_BASE_IDX 5
#define regBIF_TDISP_UNLOCKED_DEV0_PF1_INST0 0xc9d9
#define regBIF_TDISP_UNLOCKED_DEV0_PF1_INST0_BASE_IDX 5
#define regBIF_TDISP_MISC_CNTL_DEV0 0xc9e0
#define regBIF_TDISP_MISC_CNTL_DEV0_BASE_IDX 5
#define regBIF_TDISP_MISC_CNTL 0xc9e4
#define regBIF_TDISP_MISC_CNTL_BASE_IDX 5
#define regBIF_RCC_IDE_TDISP_CNTL 0xc9e5
#define regBIF_RCC_IDE_TDISP_CNTL_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_31 0xca00
#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_VF0_31 0xca01
#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_VF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF1_VF0_31 0xca02
#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF1_VF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_31 0xca03
#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_VF0_31 0xca04
#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_VF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF1_VF0_31 0xca05
#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF1_VF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_31 0xca06
#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_VF0_31 0xca07
#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_VF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF1_VF0_31 0xca08
#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF1_VF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_31 0xca09
#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_VF0_31 0xca0a
#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_VF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF1_VF0_31 0xca0b
#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF1_VF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_31 0xca0c
#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_VF0_31 0xca0d
#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_VF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF1_VF0_31 0xca0e
#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF1_VF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_31 0xca0f
#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_VF0_31 0xca10
#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_VF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF1_VF0_31 0xca11
#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF1_VF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_31 0xca12
#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_VF0_31 0xca13
#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_VF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF1_VF0_31 0xca14
#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF1_VF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_31 0xca15
#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_VF0_31 0xca16
#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_VF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF1_VF0_31 0xca17
#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF1_VF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_31 0xca18
#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_VF0_31 0xca19
#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_VF0_31_BASE_IDX 5
#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF1_VF0_31 0xca1a
#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF1_VF0_31_BASE_IDX 5
#define regBIF_SYSTEM_EN 0xca1b
#define regBIF_SYSTEM_EN_BASE_IDX 5
#define regBIF_MASK_SYSTEM_EN 0xca1c
#define regBIF_MASK_SYSTEM_EN_BASE_IDX 5
#define regGPUIOV_SCH0 0xcb40
#define regGPUIOV_SCH0_BASE_IDX 5
#define regGPUIOV_SCH1 0xcb41
#define regGPUIOV_SCH1_BASE_IDX 5
#define regGPUIOV_SCH2 0xcb42
#define regGPUIOV_SCH2_BASE_IDX 5
#define regGPUIOV_SCH3 0xcb43
#define regGPUIOV_SCH3_BASE_IDX 5
#define regGPUIOV_SCH4 0xcb44
#define regGPUIOV_SCH4_BASE_IDX 5
#define regGPUIOV_SCH5 0xcb45
#define regGPUIOV_SCH5_BASE_IDX 5
#define regGPUIOV_SCH6 0xcb46
#define regGPUIOV_SCH6_BASE_IDX 5
#define regGPUIOV_SCH7 0xcb47
#define regGPUIOV_SCH7_BASE_IDX 5
#define regGPUIOV_SCH8 0xcb48
#define regGPUIOV_SCH8_BASE_IDX 5
#define regGPUIOV_SCH9 0xcb49
#define regGPUIOV_SCH9_BASE_IDX 5
#define regGPUIOV_SCH10 0xcb4a
#define regGPUIOV_SCH10_BASE_IDX 5
#define regGPUIOV_SCH11 0xcb4b
#define regGPUIOV_SCH11_BASE_IDX 5
#define regGPUIOV_SCH12 0xcb4c
#define regGPUIOV_SCH12_BASE_IDX 5
#define regGPUIOV_SCH13 0xcb4d
#define regGPUIOV_SCH13_BASE_IDX 5
#define regGPUIOV_SCH14 0xcb4e
#define regGPUIOV_SCH14_BASE_IDX 5
#define regGPUIOV_SCH15 0xcb4f
#define regGPUIOV_SCH15_BASE_IDX 5
#define regGPUIOV_SCH16 0xcb50
#define regGPUIOV_SCH16_BASE_IDX 5
#define regGPUIOV_SCH17 0xcb51
#define regGPUIOV_SCH17_BASE_IDX 5
#define regGPUIOV_SCH18 0xcb52
#define regGPUIOV_SCH18_BASE_IDX 5
#define regGPUIOV_SCH19 0xcb53
#define regGPUIOV_SCH19_BASE_IDX 5
#define regGPUIOV_MMHUB_P2P_CNTL 0xcb54
#define regGPUIOV_MMHUB_P2P_CNTL_BASE_IDX 5
#define regBIF_AER_INTR_CTRL 0xcb55
#define regBIF_AER_INTR_CTRL_BASE_IDX 5
#define regBIF_AER_INTR_STS 0xcb56
#define regBIF_AER_INTR_STS_BASE_IDX 5
#define regBIF_PCIE_MSG_CTRL 0xcb57
#define regBIF_PCIE_MSG_CTRL_BASE_IDX 5
#define regBIF_PCIE_MSG_HEADER_DW0 0xcb58
#define regBIF_PCIE_MSG_HEADER_DW0_BASE_IDX 5
#define regBIF_PCIE_MSG_HEADER_DW1 0xcb59
#define regBIF_PCIE_MSG_HEADER_DW1_BASE_IDX 5
#define regBIF_PCIE_MSG_HEADER_DW2 0xcb5a
#define regBIF_PCIE_MSG_HEADER_DW2_BASE_IDX 5
#define regBIF_PCIE_MSG_HEADER_DW3 0xcb5b
#define regBIF_PCIE_MSG_HEADER_DW3_BASE_IDX 5
#define regBIF_PCIE_MSG_DATA_DW0 0xcb5c
#define regBIF_PCIE_MSG_DATA_DW0_BASE_IDX 5
#define regBIF_PCIE_MSG_DATA_DW1 0xcb5d
#define regBIF_PCIE_MSG_DATA_DW1_BASE_IDX 5
#define regBIF_PCIE_MSG_DATA_DW2 0xcb5e
#define regBIF_PCIE_MSG_DATA_DW2_BASE_IDX 5
#define regBIF_PCIE_MSG_DATA_DW3 0xcb5f
#define regBIF_PCIE_MSG_DATA_DW3_BASE_IDX 5
#define regBIFC_SEC_AER_SMN_CTRL0 0xcb60
#define regBIFC_SEC_AER_SMN_CTRL0_BASE_IDX 5
#define regBIFC_SEC_AER_SMN_CTRL1 0xcb61
#define regBIFC_SEC_AER_SMN_CTRL1_BASE_IDX 5
#define regBIFC_SEC_AER_SMN_CTRL2 0xcb62
#define regBIFC_SEC_AER_SMN_CTRL2_BASE_IDX 5
#define regBIF_PCIE_ERR_CTRL0 0xcb63
#define regBIF_PCIE_ERR_CTRL0_BASE_IDX 5
#define regBIF_PCIE_ERR_CTRL1 0xcb64
#define regBIF_PCIE_ERR_CTRL1_BASE_IDX 5
#define regBIF_PCIE_ERR_CTRL2 0xcb65
#define regBIF_PCIE_ERR_CTRL2_BASE_IDX 5
#define regBIF_AER_UNCORR_ERR_STATUS 0xcb66
#define regBIF_AER_UNCORR_ERR_STATUS_BASE_IDX 5
#define regBIF_AER_UNCORR_ERR_MASK 0xcb67
#define regBIF_AER_UNCORR_ERR_MASK_BASE_IDX 5
#define regBIF_AER_UNCORR_ERR_SEVERITY 0xcb68
#define regBIF_AER_UNCORR_ERR_SEVERITY_BASE_IDX 5
#define regBIF_AER_CORR_ERR_STATUS 0xcb69
#define regBIF_AER_CORR_ERR_STATUS_BASE_IDX 5
#define regBIF_AER_CORR_ERR_MASK 0xcb6a
#define regBIF_AER_CORR_ERR_MASK_BASE_IDX 5
#define regRCC_EP_STICKY_RESTORE_0 0xcb6b
#define regRCC_EP_STICKY_RESTORE_0_BASE_IDX 5
#define regRCC_EP_STICKY_RESTORE_1 0xcb6c
#define regRCC_EP_STICKY_RESTORE_1_BASE_IDX 5
#define regRCC_EP_STICKY_RESTORE_2 0xcb6d
#define regRCC_EP_STICKY_RESTORE_2_BASE_IDX 5
#define regRCC_EP_STICKY_RESTORE_3 0xcb6e
#define regRCC_EP_STICKY_RESTORE_3_BASE_IDX 5
#define regRCC_EP_STICKY_RESTORE_4 0xcb6f
#define regRCC_EP_STICKY_RESTORE_4_BASE_IDX 5
#define regRCC_EP_STICKY_RESTORE_5 0xcb70
#define regRCC_EP_STICKY_RESTORE_5_BASE_IDX 5
#define regRCC_EP_STICKY_RESTORE_6 0xcb71
#define regRCC_EP_STICKY_RESTORE_6_BASE_IDX 5
#define regRCC_EP_STICKY_RESTORE_7 0xcb72
#define regRCC_EP_STICKY_RESTORE_7_BASE_IDX 5
#define regRCC_EP_STICKY_RESTORE_8 0xcb73
#define regRCC_EP_STICKY_RESTORE_8_BASE_IDX 5
#define regRCC_EP_STICKY_RESTORE_9 0xcb74
#define regRCC_EP_STICKY_RESTORE_9_BASE_IDX 5
#define regRCC_EP_STICKY_RESTORE_10 0xcb75
#define regRCC_EP_STICKY_RESTORE_10_BASE_IDX 5
#define regRCC_EP_STICKY_RESTORE_11 0xcb76
#define regRCC_EP_STICKY_RESTORE_11_BASE_IDX 5
#define regRCC_EP_STICKY_RESTORE_12 0xcb77
#define regRCC_EP_STICKY_RESTORE_12_BASE_IDX 5
#define regRCC_EP_STICKY_RESTORE_13 0xcb78
#define regRCC_EP_STICKY_RESTORE_13_BASE_IDX 5
#define regBIF_DEVICE3_STATUS 0xcb79
#define regBIF_DEVICE3_STATUS_BASE_IDX 5
#define regBIFC_SEC_MCTP_SMN_CTRL0 0xcb81
#define regBIFC_SEC_MCTP_SMN_CTRL0_BASE_IDX 5
#define regBIFC_SEC_MCTP_SMN_CTRL1 0xcb82
#define regBIFC_SEC_MCTP_SMN_CTRL1_BASE_IDX 5
#define regNBIF_MCTP_GENERIC_CNTL 0xcc08
#define regNBIF_MCTP_GENERIC_CNTL_BASE_IDX 5
#define regNBIF_MCTP_GENERIC_STATUS 0xcc09
#define regNBIF_MCTP_GENERIC_STATUS_BASE_IDX 5
#define regSDPVW_UPDATE_EN 0xcc22
#define regSDPVW_UPDATE_EN_BASE_IDX 5
#define regREGS_ROM_OFFSET_CTRL 0xcc23
#define regREGS_ROM_OFFSET_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_POISON_DATA_DROP_CTRL 0xcc24
#define regBIFL_SEC_RAS_POISON_DATA_DROP_CTRL_BASE_IDX 5
#define regREGS_INDEX_DATA_PAIR_CTRL 0xcc25
#define regREGS_INDEX_DATA_PAIR_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_RESPONSE_DROP_CTRL 0xcc26
#define regBIFL_SEC_RAS_RESPONSE_DROP_CTRL_BASE_IDX 5
#define regBIFC_SEC_MCA_SMN_CTRL0 0xcc44
#define regBIFC_SEC_MCA_SMN_CTRL0_BASE_IDX 5
#define regBIFC_SEC_MCA_SMN_CTRL1 0xcc45
#define regBIFC_SEC_MCA_SMN_CTRL1_BASE_IDX 5
#define regBIFL_SEC_RAS_POISON_DBUG_CTRL 0xcc46
#define regBIFL_SEC_RAS_POISON_DBUG_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_PARITY_DBUG_CTRL 0xcc47
#define regBIFL_SEC_RAS_PARITY_DBUG_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_NTB_DBUG_CTRL 0xcc48
#define regBIFL_SEC_RAS_NTB_DBUG_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL 0xcc4a
#define regBIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_TIMEOUT_DBUG_CTRL 0xcc4c
#define regBIFL_SEC_RAS_TIMEOUT_DBUG_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF0_RRESP_POISON_CTRL 0xcc5b
#define regBIFL_SEC_RAS_LEAF0_RRESP_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF0_RUSER_POISON_CTRL 0xcc5c
#define regBIFL_SEC_RAS_LEAF0_RUSER_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF1_RRESP_POISON_CTRL 0xcc5d
#define regBIFL_SEC_RAS_LEAF1_RRESP_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF1_RUSER_POISON_CTRL 0xcc5e
#define regBIFL_SEC_RAS_LEAF1_RUSER_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF2_RRESP_POISON_CTRL 0xcc5f
#define regBIFL_SEC_RAS_LEAF2_RRESP_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF2_RUSER_POISON_CTRL 0xcc60
#define regBIFL_SEC_RAS_LEAF2_RUSER_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF3_RRESP_POISON_CTRL 0xcc61
#define regBIFL_SEC_RAS_LEAF3_RRESP_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF3_RUSER_POISON_CTRL 0xcc62
#define regBIFL_SEC_RAS_LEAF3_RUSER_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF4_RRESP_POISON_CTRL 0xcc63
#define regBIFL_SEC_RAS_LEAF4_RRESP_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF4_RUSER_POISON_CTRL 0xcc64
#define regBIFL_SEC_RAS_LEAF4_RUSER_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF5_RRESP_POISON_CTRL 0xcc65
#define regBIFL_SEC_RAS_LEAF5_RRESP_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF5_RUSER_POISON_CTRL 0xcc66
#define regBIFL_SEC_RAS_LEAF5_RUSER_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF6_RRESP_POISON_CTRL 0xcc67
#define regBIFL_SEC_RAS_LEAF6_RRESP_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF6_RUSER_POISON_CTRL 0xcc68
#define regBIFL_SEC_RAS_LEAF6_RUSER_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF7_RRESP_POISON_CTRL 0xcc69
#define regBIFL_SEC_RAS_LEAF7_RRESP_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF7_RUSER_POISON_CTRL 0xcc6a
#define regBIFL_SEC_RAS_LEAF7_RUSER_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF8_RRESP_POISON_CTRL 0xcc6b
#define regBIFL_SEC_RAS_LEAF8_RRESP_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF8_RUSER_POISON_CTRL 0xcc6c
#define regBIFL_SEC_RAS_LEAF8_RUSER_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF9_RRESP_POISON_CTRL 0xcc6d
#define regBIFL_SEC_RAS_LEAF9_RRESP_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF9_RUSER_POISON_CTRL 0xcc6e
#define regBIFL_SEC_RAS_LEAF9_RUSER_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF10_RRESP_POISON_CTRL 0xcc6f
#define regBIFL_SEC_RAS_LEAF10_RRESP_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF10_RUSER_POISON_CTRL 0xcc70
#define regBIFL_SEC_RAS_LEAF10_RUSER_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF11_RRESP_POISON_CTRL 0xcc71
#define regBIFL_SEC_RAS_LEAF11_RRESP_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF11_RUSER_POISON_CTRL 0xcc72
#define regBIFL_SEC_RAS_LEAF11_RUSER_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF12_RRESP_POISON_CTRL 0xcc73
#define regBIFL_SEC_RAS_LEAF12_RRESP_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF12_RUSER_POISON_CTRL 0xcc74
#define regBIFL_SEC_RAS_LEAF12_RUSER_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF13_RRESP_POISON_CTRL 0xcc75
#define regBIFL_SEC_RAS_LEAF13_RRESP_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF13_RUSER_POISON_CTRL 0xcc76
#define regBIFL_SEC_RAS_LEAF13_RUSER_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF14_RRESP_POISON_CTRL 0xcc77
#define regBIFL_SEC_RAS_LEAF14_RRESP_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF14_RUSER_POISON_CTRL 0xcc78
#define regBIFL_SEC_RAS_LEAF14_RUSER_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF15_RRESP_POISON_CTRL 0xcc79
#define regBIFL_SEC_RAS_LEAF15_RRESP_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF15_RUSER_POISON_CTRL 0xcc7a
#define regBIFL_SEC_RAS_LEAF15_RUSER_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF16_RRESP_POISON_CTRL 0xcc7b
#define regBIFL_SEC_RAS_LEAF16_RRESP_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF16_RUSER_POISON_CTRL 0xcc7c
#define regBIFL_SEC_RAS_LEAF16_RUSER_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF17_RRESP_POISON_CTRL 0xcc7d
#define regBIFL_SEC_RAS_LEAF17_RRESP_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF17_RUSER_POISON_CTRL 0xcc7e
#define regBIFL_SEC_RAS_LEAF17_RUSER_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF18_RRESP_POISON_CTRL 0xcc7f
#define regBIFL_SEC_RAS_LEAF18_RRESP_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF18_RUSER_POISON_CTRL 0xcc80
#define regBIFL_SEC_RAS_LEAF18_RUSER_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF19_RRESP_POISON_CTRL 0xcc81
#define regBIFL_SEC_RAS_LEAF19_RRESP_POISON_CTRL_BASE_IDX 5
#define regBIFL_SEC_RAS_LEAF19_RUSER_POISON_CTRL 0xcc82
#define regBIFL_SEC_RAS_LEAF19_RUSER_POISON_CTRL_BASE_IDX 5
#define regNBIF_STRAP_BIOS_CNTL 0xcc89
#define regNBIF_STRAP_BIOS_CNTL_BASE_IDX 5
#define regSMN_MST_NORMAL_SECURITY 0xcdea
#define regSMN_MST_NORMAL_SECURITY_BASE_IDX 5
#define regOVERRIDE_TYPE_FOR_CHAIN_CTRL 0xcdec
#define regOVERRIDE_TYPE_FOR_CHAIN_CTRL_BASE_IDX 5
#define regPROCESSING_HINT_SUPPORT_CNTL 0xcded
#define regPROCESSING_HINT_SUPPORT_CNTL_BASE_IDX 5
#define regDEV0_PF0_VF0_MMIO0_FENCE 0xce40
#define regDEV0_PF0_VF0_MMIO0_FENCE_BASE_IDX 5
#define regDEV0_PF0_VF1_MMIO0_FENCE 0xce41
#define regDEV0_PF0_VF1_MMIO0_FENCE_BASE_IDX 5
#define regDEV0_PF0_VF2_MMIO0_FENCE 0xce42
#define regDEV0_PF0_VF2_MMIO0_FENCE_BASE_IDX 5
#define regDEV0_PF0_VF3_MMIO0_FENCE 0xce43
#define regDEV0_PF0_VF3_MMIO0_FENCE_BASE_IDX 5
#define regDEV0_PF0_VF4_MMIO0_FENCE 0xce44
#define regDEV0_PF0_VF4_MMIO0_FENCE_BASE_IDX 5
#define regDEV0_PF0_VF5_MMIO0_FENCE 0xce45
#define regDEV0_PF0_VF5_MMIO0_FENCE_BASE_IDX 5
#define regDEV0_PF0_VF6_MMIO0_FENCE 0xce46
#define regDEV0_PF0_VF6_MMIO0_FENCE_BASE_IDX 5
#define regDEV0_PF0_VF7_MMIO0_FENCE 0xce47
#define regDEV0_PF0_VF7_MMIO0_FENCE_BASE_IDX 5
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE0_START 0xce48
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE0_START_BASE_IDX 5
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE0_END 0xce49
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE0_END_BASE_IDX 5
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE1_START 0xce4a
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE1_START_BASE_IDX 5
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE1_END 0xce4b
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE1_END_BASE_IDX 5
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE2_START 0xce4c
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE2_START_BASE_IDX 5
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE2_END 0xce4d
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE2_END_BASE_IDX 5
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE3_START 0xce4e
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE3_START_BASE_IDX 5
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE3_END 0xce4f
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE3_END_BASE_IDX 5
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE4_START 0xce50
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE4_START_BASE_IDX 5
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE4_END 0xce51
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE4_END_BASE_IDX 5
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE5_START 0xce52
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE5_START_BASE_IDX 5
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE5_END 0xce53
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE5_END_BASE_IDX 5
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE6_START 0xce54
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE6_START_BASE_IDX 5
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE6_END 0xce55
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE6_END_BASE_IDX 5
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE7_START 0xce56
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE7_START_BASE_IDX 5
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE7_END 0xce57
#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE7_END_BASE_IDX 5
#define regDEV0_PF1_VF0_MMIO0_FENCE 0xce58
#define regDEV0_PF1_VF0_MMIO0_FENCE_BASE_IDX 5
#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE0_START 0xce59
#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE0_START_BASE_IDX 5
#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE0_END 0xce5a
#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE0_END_BASE_IDX 5
#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE1_START 0xce5b
#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE1_START_BASE_IDX 5
#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE1_END 0xce5c
#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE1_END_BASE_IDX 5
#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE2_START 0xce5d
#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE2_START_BASE_IDX 5
#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE2_END 0xce5e
#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE2_END_BASE_IDX 5
#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE3_START 0xce5f
#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE3_START_BASE_IDX 5
#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE3_END 0xce60
#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE3_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_WR 0xce61
#define regDEV0_PF0_PF_MMIO0_FENCE_WR_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RD 0xce62
#define regDEV0_PF0_PF_MMIO0_FENCE_RD_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE0_START 0xce63
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE0_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE0_END 0xce64
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE0_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE1_START 0xce65
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE1_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE1_END 0xce66
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE1_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE2_START 0xce67
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE2_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE2_END 0xce68
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE2_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE3_START 0xce69
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE3_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE3_END 0xce6a
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE3_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE4_START 0xce6b
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE4_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE4_END 0xce6c
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE4_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE5_START 0xce6d
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE5_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE5_END 0xce6e
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE5_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE6_START 0xce6f
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE6_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE6_END 0xce70
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE6_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE7_START 0xce71
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE7_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE7_END 0xce72
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE7_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE8_START 0xce73
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE8_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE8_END 0xce74
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE8_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE9_START 0xce75
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE9_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE9_END 0xce76
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE9_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE10_START 0xce77
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE10_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE10_END 0xce78
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE10_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE11_START 0xce79
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE11_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE11_END 0xce7a
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE11_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE12_START 0xce7b
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE12_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE12_END 0xce7c
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE12_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE13_START 0xce7d
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE13_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE13_END 0xce7e
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE13_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE14_START 0xce7f
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE14_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE14_END 0xce80
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE14_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE15_START 0xce81
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE15_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE15_END 0xce82
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE15_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE16_START 0xce83
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE16_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE16_END 0xce84
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE16_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE17_START 0xce85
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE17_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE17_END 0xce86
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE17_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE18_START 0xce87
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE18_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE18_END 0xce88
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE18_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE19_START 0xce89
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE19_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE19_END 0xce8a
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE19_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE20_START 0xce8b
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE20_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE20_END 0xce8c
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE20_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE21_START 0xce8d
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE21_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE21_END 0xce8e
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE21_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE22_START 0xce8f
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE22_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE22_END 0xce90
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE22_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE23_START 0xce91
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE23_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE23_END 0xce92
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE23_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE24_START 0xce93
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE24_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE24_END 0xce94
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE24_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE25_START 0xce95
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE25_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE25_END 0xce96
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE25_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE26_START 0xce97
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE26_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE26_END 0xce98
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE26_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE27_START 0xce99
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE27_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE27_END 0xce9a
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE27_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE28_START 0xce9b
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE28_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE28_END 0xce9c
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE28_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE29_START 0xce9d
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE29_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE29_END 0xce9e
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE29_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE30_START 0xce9f
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE30_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE30_END 0xcea0
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE30_END_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE31_START 0xcea1
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE31_START_BASE_IDX 5
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE31_END 0xcea2
#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE31_END_BASE_IDX 5
#define regDEV0_PF1_PF_MMIO0_FENCE_WR 0xcea3
#define regDEV0_PF1_PF_MMIO0_FENCE_WR_BASE_IDX 5
#define regDEV0_PF1_PF_MMIO0_FENCE_RD 0xcea4
#define regDEV0_PF1_PF_MMIO0_FENCE_RD_BASE_IDX 5
#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE0_START 0xcea5
#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE0_START_BASE_IDX 5
#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE0_END 0xcea6
#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE0_END_BASE_IDX 5
#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE1_START 0xcea7
#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE1_START_BASE_IDX 5
#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE1_END 0xcea8
#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE1_END_BASE_IDX 5
#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE2_START 0xcea9
#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE2_START_BASE_IDX 5
#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE2_END 0xceaa
#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE2_END_BASE_IDX 5
#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE3_START 0xceab
#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE3_START_BASE_IDX 5
#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE3_END 0xceac
#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE3_END_BASE_IDX 5
#define regMISC_SCRATCH 0xe800
#define regMISC_SCRATCH_BASE_IDX 5
#define regINTR_LINE_POLARITY 0xe801
#define regINTR_LINE_POLARITY_BASE_IDX 5
#define regINTR_LINE_ENABLE 0xe802
#define regINTR_LINE_ENABLE_BASE_IDX 5
#define regOUTSTANDING_VC_ALLOC 0xe803
#define regOUTSTANDING_VC_ALLOC_BASE_IDX 5
#define regBIFC_MISC_CTRL0 0xe804
#define regBIFC_MISC_CTRL0_BASE_IDX 5
#define regBIFC_MISC_CTRL1 0xe805
#define regBIFC_MISC_CTRL1_BASE_IDX 5
#define regBIFC_BME_ERR_LOG_LB 0xe806
#define regBIFC_BME_ERR_LOG_LB_BASE_IDX 5
#define regBIFC_LC_TIMER_CTRL 0xe807
#define regBIFC_LC_TIMER_CTRL_BASE_IDX 5
#define regBIFC_RCCBIH_BME_ERR_LOG0 0xe808
#define regBIFC_RCCBIH_BME_ERR_LOG0_BASE_IDX 5
#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 0xe80a
#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_BASE_IDX 5
#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 0xe80b
#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_BASE_IDX 5
#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 0xe80c
#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_BASE_IDX 5
#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 0xe80d
#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_BASE_IDX 5
#define regBIFC_DMA_ATTR_CNTL2_DEV0 0xe81a
#define regBIFC_DMA_ATTR_CNTL2_DEV0_BASE_IDX 5
#define regBIFC_MISC_CTRL2 0xe822
#define regBIFC_MISC_CTRL2_BASE_IDX 5
#define regBME_DUMMY_CNTL_0 0xe825
#define regBME_DUMMY_CNTL_0_BASE_IDX 5
#define regBIFC_THT_CNTL 0xe827
#define regBIFC_THT_CNTL_BASE_IDX 5
#define regBIFC_HSTARB_CNTL 0xe828
#define regBIFC_HSTARB_CNTL_BASE_IDX 5
#define regBIFC_GSI_CNTL 0xe829
#define regBIFC_GSI_CNTL_BASE_IDX 5
#define regBIFC_PCIEFUNC_CNTL 0xe82a
#define regBIFC_PCIEFUNC_CNTL_BASE_IDX 5
#define regBIFC_PASID_CHECK_DIS 0xe82b
#define regBIFC_PASID_CHECK_DIS_BASE_IDX 5
#define regBIFC_SDP_CNTL_0 0xe82c
#define regBIFC_SDP_CNTL_0_BASE_IDX 5
#define regBIFC_SDP_CNTL_1 0xe82d
#define regBIFC_SDP_CNTL_1_BASE_IDX 5
#define regBIFC_PASID_STS 0xe82e
#define regBIFC_PASID_STS_BASE_IDX 5
#define regBIFC_ATHUB_ACT_CNTL 0xe82f
#define regBIFC_ATHUB_ACT_CNTL_BASE_IDX 5
#define regBIFC_PERF_CNTL_0 0xe830
#define regBIFC_PERF_CNTL_0_BASE_IDX 5
#define regBIF_MISC_BIFC_PERF_CNTL_1 0xe831
#define regBIF_MISC_BIFC_PERF_CNTL_1_BASE_IDX 5
#define regBIFC_PERF_CNT_MMIO_RD_L32BIT 0xe832
#define regBIFC_PERF_CNT_MMIO_RD_L32BIT_BASE_IDX 5
#define regBIFC_PERF_CNT_MMIO_WR_L32BIT 0xe833
#define regBIFC_PERF_CNT_MMIO_WR_L32BIT_BASE_IDX 5
#define regBIF_MISC_BIFC_PERF_CNT_DMA_RD_L32BIT 0xe834
#define regBIF_MISC_BIFC_PERF_CNT_DMA_RD_L32BIT_BASE_IDX 5
#define regBIF_MISC_BIFC_PERF_CNT_DMA_WR_L32BIT 0xe835
#define regBIF_MISC_BIFC_PERF_CNT_DMA_WR_L32BIT_BASE_IDX 5
#define regNBIF_REGIF_ERRSET_CTRL 0xe836
#define regNBIF_REGIF_ERRSET_CTRL_BASE_IDX 5
#define regBIFC_SDP_CNTL_2 0xe837
#define regBIFC_SDP_CNTL_2_BASE_IDX 5
#define regNBIF_PGMST_CTRL 0xe838
#define regNBIF_PGMST_CTRL_BASE_IDX 5
#define regNBIF_PGSLV_CTRL 0xe839
#define regNBIF_PGSLV_CTRL_BASE_IDX 5
#define regNBIF_PG_MISC_CTRL 0xe83a
#define regNBIF_PG_MISC_CTRL_BASE_IDX 5
#define regSMN_MST_EP_CNTL3 0xe83c
#define regSMN_MST_EP_CNTL3_BASE_IDX 5
#define regSMN_MST_EP_CNTL4 0xe83d
#define regSMN_MST_EP_CNTL4_BASE_IDX 5
#define regSMN_MST_CNTL1 0xe83e
#define regSMN_MST_CNTL1_BASE_IDX 5
#define regSMN_MST_EP_CNTL5 0xe83f
#define regSMN_MST_EP_CNTL5_BASE_IDX 5
#define regBIF_SELFRING_BUFFER_VID 0xe840
#define regBIF_SELFRING_BUFFER_VID_BASE_IDX 5
#define regBIF_SELFRING_VECTOR_CNTL 0xe841
#define regBIF_SELFRING_VECTOR_CNTL_BASE_IDX 5
#define regHDP_ERR_STATUS_EXT 0xe842
#define regHDP_ERR_STATUS_EXT_BASE_IDX 5
#define regNBIF_STRAP_WRITE_CTRL 0xe845
#define regNBIF_STRAP_WRITE_CTRL_BASE_IDX 5
#define regNBIF_INTX_DSTATE_MISC_CNTL 0xe846
#define regNBIF_INTX_DSTATE_MISC_CNTL_BASE_IDX 5
#define regNBIF_PENDING_MISC_CNTL 0xe847
#define regNBIF_PENDING_MISC_CNTL_BASE_IDX 5
#define regBIF_GMI_WRR_WEIGHT 0xe848
#define regBIF_GMI_WRR_WEIGHT_BASE_IDX 5
#define regBIF_GMI_WRR_WEIGHT2 0xe849
#define regBIF_GMI_WRR_WEIGHT2_BASE_IDX 5
#define regBIF_GMI_WRR_WEIGHT3 0xe84a
#define regBIF_GMI_WRR_WEIGHT3_BASE_IDX 5
#define regBIF_GMI_WRR_WEIGHT4 0xe84b
#define regBIF_GMI_WRR_WEIGHT4_BASE_IDX 5
#define regNBIF_PWRBRK_REQUEST 0xe84c
#define regNBIF_PWRBRK_REQUEST_BASE_IDX 5
#define regBIF_ATOMIC_ERR_LOG_DEV0_F0 0xe850
#define regBIF_ATOMIC_ERR_LOG_DEV0_F0_BASE_IDX 5
#define regBIF_ATOMIC_ERR_LOG_DEV0_F1 0xe851
#define regBIF_ATOMIC_ERR_LOG_DEV0_F1_BASE_IDX 5
#define regBIF_DMA_MP4_ERR_LOG 0xe870
#define regBIF_DMA_MP4_ERR_LOG_BASE_IDX 5
#define regBIF_PASID_ERR_LOG 0xe871
#define regBIF_PASID_ERR_LOG_BASE_IDX 5
#define regBIF_PASID_ERR_CLR 0xe872
#define regBIF_PASID_ERR_CLR_BASE_IDX 5
#define regNBIF_VWIRE_CTRL 0xe880
#define regNBIF_VWIRE_CTRL_BASE_IDX 5
#define regNBIF_MGCG_CTRL_LCLK 0xe887
#define regNBIF_MGCG_CTRL_LCLK_BASE_IDX 5
#define regNBIF_DS_CTRL_LCLK 0xe888
#define regNBIF_DS_CTRL_LCLK_BASE_IDX 5
#define regSMN_MST_CNTL0 0xe889
#define regSMN_MST_CNTL0_BASE_IDX 5
#define regSMN_MST_EP_CNTL1 0xe88a
#define regSMN_MST_EP_CNTL1_BASE_IDX 5
#define regSMN_MST_EP_CNTL2 0xe88b
#define regSMN_MST_EP_CNTL2_BASE_IDX 5
#define regNBIF_SDP_VWR_VCHG_DIS_CTRL 0xe88c
#define regNBIF_SDP_VWR_VCHG_DIS_CTRL_BASE_IDX 5
#define regNBIF_SDP_VWR_VCHG_RST_CTRL0 0xe88d
#define regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX 5
#define regNBIF_SDP_VWR_VCHG_RST_CTRL1 0xe88e
#define regNBIF_SDP_VWR_VCHG_RST_CTRL1_BASE_IDX 5
#define regNBIF_SDP_VWR_VCHG_TRIG 0xe88f
#define regNBIF_SDP_VWR_VCHG_TRIG_BASE_IDX 5
#define regNBIO_LCLK_DEEPSLEEP_MASK 0xe890
#define regNBIO_LCLK_DEEPSLEEP_MASK_BASE_IDX 5
#define regNBIF_DS_CTRL_USBCLK 0xe891
#define regNBIF_DS_CTRL_USBCLK_BASE_IDX 5
#define regNBIF_SHUB_TODET_CLIENT_MISC3 0xe897
#define regNBIF_SHUB_TODET_CLIENT_MISC3_BASE_IDX 5
#define regNBIF_SHUB_TODET_CTRL 0xe898
#define regNBIF_SHUB_TODET_CTRL_BASE_IDX 5
#define regNBIF_SHUB_TODET_CLIENT_CTRL 0xe899
#define regNBIF_SHUB_TODET_CLIENT_CTRL_BASE_IDX 5
#define regNBIF_SHUB_TODET_CLIENT_STATUS 0xe89a
#define regNBIF_SHUB_TODET_CLIENT_STATUS_BASE_IDX 5
#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL 0xe89b
#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL_BASE_IDX 5
#define regNBIF_SHUB_TODET_CLIENT_CTRL2 0xe89c
#define regNBIF_SHUB_TODET_CLIENT_CTRL2_BASE_IDX 5
#define regNBIF_SHUB_TODET_CLIENT_STATUS2 0xe89d
#define regNBIF_SHUB_TODET_CLIENT_STATUS2_BASE_IDX 5
#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2 0xe89e
#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2_BASE_IDX 5
#define regDMA_SDP_PORT_DEBUG 0xe8a0
#define regDMA_SDP_PORT_DEBUG_BASE_IDX 5
#define regSDP_PORT_MONITOR_CONTROL 0xe8a2
#define regSDP_PORT_MONITOR_CONTROL_BASE_IDX 5
#define regSDP_PORT_MONITOR_ADDRESS0 0xe8a3
#define regSDP_PORT_MONITOR_ADDRESS0_BASE_IDX 5
#define regSDP_PORT_MONITOR_ADDRESS1 0xe8a4
#define regSDP_PORT_MONITOR_ADDRESS1_BASE_IDX 5
#define regSDP_PORT_MONITOR_UNITID 0xe8a5
#define regSDP_PORT_MONITOR_UNITID_BASE_IDX 5
#define regSDP_PORT_MONITOR_INFO0 0xe8a6
#define regSDP_PORT_MONITOR_INFO0_BASE_IDX 5
#define regSDP_PORT_MONITOR_INFO1 0xe8a7
#define regSDP_PORT_MONITOR_INFO1_BASE_IDX 5
#define regSDP_PORT_MONITOR_INFO2 0xe8a8
#define regSDP_PORT_MONITOR_INFO2_BASE_IDX 5
#define regSDP_PORT_MONITOR_INFO3 0xe8a9
#define regSDP_PORT_MONITOR_INFO3_BASE_IDX 5
#define regSDP_PORT_MONITOR_INFO4 0xe8aa
#define regSDP_PORT_MONITOR_INFO4_BASE_IDX 5
#define regBIFC_BME_ERR_LOG_HB 0xe8ab
#define regBIFC_BME_ERR_LOG_HB_BASE_IDX 5
#define regBIFC_GFX_INT_MONITOR_MASK 0xe8ad
#define regBIFC_GFX_INT_MONITOR_MASK_BASE_IDX 5
#define regBIFC_GFX_INT_MONITOR_STS 0xe8ae
#define regBIFC_GFX_INT_MONITOR_STS_BASE_IDX 5
#define regBIFC_GFX_INT_MONITOR_CTRL 0xe8af
#define regBIFC_GFX_INT_MONITOR_CTRL_BASE_IDX 5
#define regNBIF_FLUSH_CTRL 0xe8b1
#define regNBIF_FLUSH_CTRL_BASE_IDX 5
#define regNBIF_GUI_FLUSH_CNTL 0xe8b3
#define regNBIF_GUI_FLUSH_CNTL_BASE_IDX 5
#define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC 0xe8c0
#define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC_BASE_IDX 5
#define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC 0xe8c1
#define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC_BASE_IDX 5
#define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC 0xe8c2
#define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX 5
#define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC 0xe8c3
#define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX 5
#define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC 0xe8c4
#define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC_BASE_IDX 5
#define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC 0xe8c5
#define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC_BASE_IDX 5
#define regDISCON_HYSTERESIS_HEAD_CTRL 0xe8c6
#define regDISCON_HYSTERESIS_HEAD_CTRL_BASE_IDX 5
#define regBIFC_GSI_SDP_REQ_POOLCRED_ALLOC 0xe8c7
#define regBIFC_GSI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX 5
#define regBIFC_GSI_SDP_DAT_POOLCRED_ALLOC 0xe8c8
#define regBIFC_GSI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX 5
#define regBIFC_MCA_SMN_CTRL0 0xe8cb
#define regBIFC_MCA_SMN_CTRL0_BASE_IDX 5
#define regBIFC_MCTP_SMN_CTRL0 0xe8ce
#define regBIFC_MCTP_SMN_CTRL0_BASE_IDX 5
#define regNBIF_REGIF_DEBUG_COUNTER_CTRL 0xe8cf
#define regNBIF_REGIF_DEBUG_COUNTER_CTRL_BASE_IDX 5
#define regBIFC_EARLY_WAKEUP_CNTL 0xe8d2
#define regBIFC_EARLY_WAKEUP_CNTL_BASE_IDX 5
#define regBIFC_PERF_CNT_MMIO_RD_H16BIT 0xe8f0
#define regBIFC_PERF_CNT_MMIO_RD_H16BIT_BASE_IDX 5
#define regBIFC_PERF_CNT_MMIO_WR_H16BIT 0xe8f1
#define regBIFC_PERF_CNT_MMIO_WR_H16BIT_BASE_IDX 5
#define regBIF_MISC_BIFC_PERF_CNT_DMA_RD_H16BIT 0xe8f2
#define regBIF_MISC_BIFC_PERF_CNT_DMA_RD_H16BIT_BASE_IDX 5
#define regBIF_MISC_BIFC_PERF_CNT_DMA_WR_H16BIT 0xe8f3
#define regBIF_MISC_BIFC_PERF_CNT_DMA_WR_H16BIT_BASE_IDX 5
#define regBIF_MISC_NBIF_PERF_COM_COUNT_ENABLE 0xe8f4
#define regBIF_MISC_NBIF_PERF_COM_COUNT_ENABLE_BASE_IDX 5
#define regBIF_MISC_NBIF_SDP_PERF_CNT_FSM 0xe8f5
#define regBIF_MISC_NBIF_SDP_PERF_CNT_FSM_BASE_IDX 5
#define regBIF_MISC_NBIF_SDP_PERF_COUNTER 0xe8f6
#define regBIF_MISC_NBIF_SDP_PERF_COUNTER_BASE_IDX 5
#define regBIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_L32BIT 0xe8f7
#define regBIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_L32BIT_BASE_IDX 5
#define regBIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_L32BIT 0xe8f8
#define regBIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_L32BIT_BASE_IDX 5
#define regBIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_L32BIT 0xe8f9
#define regBIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_L32BIT_BASE_IDX 5
#define regBIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_L32BIT 0xe8fa
#define regBIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_L32BIT_BASE_IDX 5
#define regBIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_H16BIT 0xe8fb
#define regBIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_H16BIT_BASE_IDX 5
#define regBIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_H16BIT 0xe8fc
#define regBIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_H16BIT_BASE_IDX 5
#define regBIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_H16BIT 0xe8fd
#define regBIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_H16BIT_BASE_IDX 5
#define regBIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_H16BIT 0xe8fe
#define regBIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_H16BIT_BASE_IDX 5
#define regBIF_MISC_NBIF_BX_PERF_CNT_FSM 0xe8ff
#define regBIF_MISC_NBIF_BX_PERF_CNT_FSM_BASE_IDX 5
#define regNBIF_TDISP_ENTER_ERR_CNTL 0xe905
#define regNBIF_TDISP_ENTER_ERR_CNTL_BASE_IDX 5
#define regBIF_UNITID_ERR_LOG 0xe906
#define regBIF_UNITID_ERR_LOG_BASE_IDX 5
#define regNBIF_COM_COUNT_VALUE 0xe908
#define regNBIF_COM_COUNT_VALUE_BASE_IDX 5
#define regNBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL 0xe909
#define regNBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL_BASE_IDX 5
#define regNBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL 0xe90a
#define regNBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL_BASE_IDX 5
#define regBIF_AER_CNTL 0xe92c
#define regBIF_AER_CNTL_BASE_IDX 5
#define regNBIF_IDE_INFO_CNTL 0xe92d
#define regNBIF_IDE_INFO_CNTL_BASE_IDX 5
#define regBIFC_EXP_MISC_CTRL0 0xe9c0
#define regBIFC_EXP_MISC_CTRL0_BASE_IDX 5
#define regSECOND_HDP_MEM_FLUSH_CNTL_PF 0xea80
#define regSECOND_HDP_MEM_FLUSH_CNTL_PF_BASE_IDX 5
#define regSECOND_HDP_MEM_FLUSH_CNTL_VF0 0xea81
#define regSECOND_HDP_MEM_FLUSH_CNTL_VF0_BASE_IDX 5
#define regSECOND_HDP_MEM_FLUSH_CNTL_VF1 0xea82
#define regSECOND_HDP_MEM_FLUSH_CNTL_VF1_BASE_IDX 5
#define regSECOND_HDP_MEM_FLUSH_CNTL_VF2 0xea83
#define regSECOND_HDP_MEM_FLUSH_CNTL_VF2_BASE_IDX 5
#define regSECOND_HDP_MEM_FLUSH_CNTL_VF3 0xea84
#define regSECOND_HDP_MEM_FLUSH_CNTL_VF3_BASE_IDX 5
#define regSECOND_HDP_MEM_FLUSH_CNTL_VF4 0xea85
#define regSECOND_HDP_MEM_FLUSH_CNTL_VF4_BASE_IDX 5
#define regSECOND_HDP_MEM_FLUSH_CNTL_VF5 0xea86
#define regSECOND_HDP_MEM_FLUSH_CNTL_VF5_BASE_IDX 5
#define regSECOND_HDP_MEM_FLUSH_CNTL_VF6 0xea87
#define regSECOND_HDP_MEM_FLUSH_CNTL_VF6_BASE_IDX 5
#define regSECOND_HDP_MEM_FLUSH_CNTL_VF7 0xea88
#define regSECOND_HDP_MEM_FLUSH_CNTL_VF7_BASE_IDX 5
#define regSECOND_HDP_REG_FLUSH_CNTL_PF 0xea89
#define regSECOND_HDP_REG_FLUSH_CNTL_PF_BASE_IDX 5
#define regSECOND_HDP_REG_FLUSH_CNTL_VF0 0xea8a
#define regSECOND_HDP_REG_FLUSH_CNTL_VF0_BASE_IDX 5
#define regSECOND_HDP_REG_FLUSH_CNTL_VF1 0xea8b
#define regSECOND_HDP_REG_FLUSH_CNTL_VF1_BASE_IDX 5
#define regSECOND_HDP_REG_FLUSH_CNTL_VF2 0xea8c
#define regSECOND_HDP_REG_FLUSH_CNTL_VF2_BASE_IDX 5
#define regSECOND_HDP_REG_FLUSH_CNTL_VF3 0xea8d
#define regSECOND_HDP_REG_FLUSH_CNTL_VF3_BASE_IDX 5
#define regSECOND_HDP_REG_FLUSH_CNTL_VF4 0xea8e
#define regSECOND_HDP_REG_FLUSH_CNTL_VF4_BASE_IDX 5
#define regSECOND_HDP_REG_FLUSH_CNTL_VF5 0xea8f
#define regSECOND_HDP_REG_FLUSH_CNTL_VF5_BASE_IDX 5
#define regSECOND_HDP_REG_FLUSH_CNTL_VF6 0xea90
#define regSECOND_HDP_REG_FLUSH_CNTL_VF6_BASE_IDX 5
#define regSECOND_HDP_REG_FLUSH_CNTL_VF7 0xea91
#define regSECOND_HDP_REG_FLUSH_CNTL_VF7_BASE_IDX 5
#define regGPU_HDP_FLUSH_GFX_FW 0xf4c0
#define regGPU_HDP_FLUSH_GFX_FW_BASE_IDX 5
#define regNBIF_RRMT_CNTL 0xf500
#define regNBIF_RRMT_CNTL_BASE_IDX 5
#define regRRMT_NBIF_MISC_REG1 0xf501
#define regRRMT_NBIF_MISC_REG1_BASE_IDX 5
#define regRRMT_LUT_INDEX 0xf502
#define regRRMT_LUT_INDEX_BASE_IDX 5
#define regRRMT_LUT_DATA 0xf503
#define regRRMT_LUT_DATA_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0 0xf600
#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1 0xf601
#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2 0xf602
#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3 0xf603
#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0 0xf604
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1 0xf605
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2 0xf606
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3 0xf607
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0 0xf608
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1 0xf609
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2 0xf60a
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3 0xf60b
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0 0xf60c
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1 0xf60d
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2 0xf60e
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3 0xf60f
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0 0xf610
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1 0xf611
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2 0xf612
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3 0xf613
#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0 0xf619
#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1 0xf61a
#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2 0xf61b
#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3 0xf61c
#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0 0xf61d
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1 0xf61e
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2 0xf61f
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3 0xf620
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0 0xf621
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1 0xf622
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2 0xf623
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3 0xf624
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0 0xf625
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1 0xf626
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2 0xf627
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3 0xf628
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0 0xf629
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1 0xf62a
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2 0xf62b
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2_BASE_IDX 5
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3 0xf62c
#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3_BASE_IDX 5
#define regNBIF_TRAP_NP_STATUS 0x4000
#define regNBIF_TRAP_NP_STATUS_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST0 0x4001
#define regNBIF_TRAP_NP_REQUEST0_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST1 0x4002
#define regNBIF_TRAP_NP_REQUEST1_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST2 0x4003
#define regNBIF_TRAP_NP_REQUEST2_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST3 0x4004
#define regNBIF_TRAP_NP_REQUEST3_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST4 0x4005
#define regNBIF_TRAP_NP_REQUEST4_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST5 0x4006
#define regNBIF_TRAP_NP_REQUEST5_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST6 0x4007
#define regNBIF_TRAP_NP_REQUEST6_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATASTRB0 0x4008
#define regNBIF_TRAP_NP_REQUEST_DATASTRB0_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATASTRB1 0x4009
#define regNBIF_TRAP_NP_REQUEST_DATASTRB1_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATASTRB2 0x400a
#define regNBIF_TRAP_NP_REQUEST_DATASTRB2_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATASTRB3 0x400b
#define regNBIF_TRAP_NP_REQUEST_DATASTRB3_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATASTRB4 0x400c
#define regNBIF_TRAP_NP_REQUEST_DATASTRB4_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATASTRB5 0x400d
#define regNBIF_TRAP_NP_REQUEST_DATASTRB5_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATASTRB6 0x400e
#define regNBIF_TRAP_NP_REQUEST_DATASTRB6_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATASTRB7 0x400f
#define regNBIF_TRAP_NP_REQUEST_DATASTRB7_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA0 0x4010
#define regNBIF_TRAP_NP_REQUEST_DATA0_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA1 0x4011
#define regNBIF_TRAP_NP_REQUEST_DATA1_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA2 0x4012
#define regNBIF_TRAP_NP_REQUEST_DATA2_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA3 0x4013
#define regNBIF_TRAP_NP_REQUEST_DATA3_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA4 0x4014
#define regNBIF_TRAP_NP_REQUEST_DATA4_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA5 0x4015
#define regNBIF_TRAP_NP_REQUEST_DATA5_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA6 0x4016
#define regNBIF_TRAP_NP_REQUEST_DATA6_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA7 0x4017
#define regNBIF_TRAP_NP_REQUEST_DATA7_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA8 0x4018
#define regNBIF_TRAP_NP_REQUEST_DATA8_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA9 0x4019
#define regNBIF_TRAP_NP_REQUEST_DATA9_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA10 0x401a
#define regNBIF_TRAP_NP_REQUEST_DATA10_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA11 0x401b
#define regNBIF_TRAP_NP_REQUEST_DATA11_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA12 0x401c
#define regNBIF_TRAP_NP_REQUEST_DATA12_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA13 0x401d
#define regNBIF_TRAP_NP_REQUEST_DATA13_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA14 0x401e
#define regNBIF_TRAP_NP_REQUEST_DATA14_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA15 0x401f
#define regNBIF_TRAP_NP_REQUEST_DATA15_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA16 0x4020
#define regNBIF_TRAP_NP_REQUEST_DATA16_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA17 0x4021
#define regNBIF_TRAP_NP_REQUEST_DATA17_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA18 0x4022
#define regNBIF_TRAP_NP_REQUEST_DATA18_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA19 0x4023
#define regNBIF_TRAP_NP_REQUEST_DATA19_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA20 0x4024
#define regNBIF_TRAP_NP_REQUEST_DATA20_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA21 0x4025
#define regNBIF_TRAP_NP_REQUEST_DATA21_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA22 0x4026
#define regNBIF_TRAP_NP_REQUEST_DATA22_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA23 0x4027
#define regNBIF_TRAP_NP_REQUEST_DATA23_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA24 0x4028
#define regNBIF_TRAP_NP_REQUEST_DATA24_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA25 0x4029
#define regNBIF_TRAP_NP_REQUEST_DATA25_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA26 0x402a
#define regNBIF_TRAP_NP_REQUEST_DATA26_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA27 0x402b
#define regNBIF_TRAP_NP_REQUEST_DATA27_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA28 0x402c
#define regNBIF_TRAP_NP_REQUEST_DATA28_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA29 0x402d
#define regNBIF_TRAP_NP_REQUEST_DATA29_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA30 0x402e
#define regNBIF_TRAP_NP_REQUEST_DATA30_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA31 0x402f
#define regNBIF_TRAP_NP_REQUEST_DATA31_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA32 0x4030
#define regNBIF_TRAP_NP_REQUEST_DATA32_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA33 0x4031
#define regNBIF_TRAP_NP_REQUEST_DATA33_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA34 0x4032
#define regNBIF_TRAP_NP_REQUEST_DATA34_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA35 0x4033
#define regNBIF_TRAP_NP_REQUEST_DATA35_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA36 0x4034
#define regNBIF_TRAP_NP_REQUEST_DATA36_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA37 0x4035
#define regNBIF_TRAP_NP_REQUEST_DATA37_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA38 0x4036
#define regNBIF_TRAP_NP_REQUEST_DATA38_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA39 0x4037
#define regNBIF_TRAP_NP_REQUEST_DATA39_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA40 0x4038
#define regNBIF_TRAP_NP_REQUEST_DATA40_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA41 0x4039
#define regNBIF_TRAP_NP_REQUEST_DATA41_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA42 0x403a
#define regNBIF_TRAP_NP_REQUEST_DATA42_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA43 0x403b
#define regNBIF_TRAP_NP_REQUEST_DATA43_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA44 0x403c
#define regNBIF_TRAP_NP_REQUEST_DATA44_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA45 0x403d
#define regNBIF_TRAP_NP_REQUEST_DATA45_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA46 0x403e
#define regNBIF_TRAP_NP_REQUEST_DATA46_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA47 0x403f
#define regNBIF_TRAP_NP_REQUEST_DATA47_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA48 0x4040
#define regNBIF_TRAP_NP_REQUEST_DATA48_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA49 0x4041
#define regNBIF_TRAP_NP_REQUEST_DATA49_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA50 0x4042
#define regNBIF_TRAP_NP_REQUEST_DATA50_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA51 0x4043
#define regNBIF_TRAP_NP_REQUEST_DATA51_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA52 0x4044
#define regNBIF_TRAP_NP_REQUEST_DATA52_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA53 0x4045
#define regNBIF_TRAP_NP_REQUEST_DATA53_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA54 0x4046
#define regNBIF_TRAP_NP_REQUEST_DATA54_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA55 0x4047
#define regNBIF_TRAP_NP_REQUEST_DATA55_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA56 0x4048
#define regNBIF_TRAP_NP_REQUEST_DATA56_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA57 0x4049
#define regNBIF_TRAP_NP_REQUEST_DATA57_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA58 0x404a
#define regNBIF_TRAP_NP_REQUEST_DATA58_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA59 0x404b
#define regNBIF_TRAP_NP_REQUEST_DATA59_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA60 0x404c
#define regNBIF_TRAP_NP_REQUEST_DATA60_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA61 0x404d
#define regNBIF_TRAP_NP_REQUEST_DATA61_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA62 0x404e
#define regNBIF_TRAP_NP_REQUEST_DATA62_BASE_IDX 5
#define regNBIF_TRAP_NP_REQUEST_DATA63 0x404f
#define regNBIF_TRAP_NP_REQUEST_DATA63_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_CONTROL 0x4050
#define regNBIF_TRAP_NP_RESPONSE_CONTROL_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE0 0x4051
#define regNBIF_TRAP_NP_RESPONSE0_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE1 0x4052
#define regNBIF_TRAP_NP_RESPONSE1_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE2 0x4053
#define regNBIF_TRAP_NP_RESPONSE2_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE3 0x4054
#define regNBIF_TRAP_NP_RESPONSE3_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE4 0x4055
#define regNBIF_TRAP_NP_RESPONSE4_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE5 0x4056
#define regNBIF_TRAP_NP_RESPONSE5_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA0 0x4057
#define regNBIF_TRAP_NP_RESPONSE_DATA0_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA1 0x4058
#define regNBIF_TRAP_NP_RESPONSE_DATA1_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA2 0x4059
#define regNBIF_TRAP_NP_RESPONSE_DATA2_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA3 0x405a
#define regNBIF_TRAP_NP_RESPONSE_DATA3_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA4 0x405b
#define regNBIF_TRAP_NP_RESPONSE_DATA4_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA5 0x405c
#define regNBIF_TRAP_NP_RESPONSE_DATA5_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA6 0x405d
#define regNBIF_TRAP_NP_RESPONSE_DATA6_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA7 0x405e
#define regNBIF_TRAP_NP_RESPONSE_DATA7_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA8 0x405f
#define regNBIF_TRAP_NP_RESPONSE_DATA8_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA9 0x4060
#define regNBIF_TRAP_NP_RESPONSE_DATA9_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA10 0x4061
#define regNBIF_TRAP_NP_RESPONSE_DATA10_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA11 0x4062
#define regNBIF_TRAP_NP_RESPONSE_DATA11_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA12 0x4063
#define regNBIF_TRAP_NP_RESPONSE_DATA12_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA13 0x4064
#define regNBIF_TRAP_NP_RESPONSE_DATA13_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA14 0x4065
#define regNBIF_TRAP_NP_RESPONSE_DATA14_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA15 0x4066
#define regNBIF_TRAP_NP_RESPONSE_DATA15_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA16 0x4067
#define regNBIF_TRAP_NP_RESPONSE_DATA16_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA17 0x4068
#define regNBIF_TRAP_NP_RESPONSE_DATA17_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA18 0x4069
#define regNBIF_TRAP_NP_RESPONSE_DATA18_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA19 0x406a
#define regNBIF_TRAP_NP_RESPONSE_DATA19_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA20 0x406b
#define regNBIF_TRAP_NP_RESPONSE_DATA20_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA21 0x406c
#define regNBIF_TRAP_NP_RESPONSE_DATA21_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA22 0x406d
#define regNBIF_TRAP_NP_RESPONSE_DATA22_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA23 0x406e
#define regNBIF_TRAP_NP_RESPONSE_DATA23_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA24 0x406f
#define regNBIF_TRAP_NP_RESPONSE_DATA24_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA25 0x4070
#define regNBIF_TRAP_NP_RESPONSE_DATA25_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA26 0x4071
#define regNBIF_TRAP_NP_RESPONSE_DATA26_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA27 0x4072
#define regNBIF_TRAP_NP_RESPONSE_DATA27_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA28 0x4073
#define regNBIF_TRAP_NP_RESPONSE_DATA28_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA29 0x4074
#define regNBIF_TRAP_NP_RESPONSE_DATA29_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA30 0x4075
#define regNBIF_TRAP_NP_RESPONSE_DATA30_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA31 0x4076
#define regNBIF_TRAP_NP_RESPONSE_DATA31_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA32 0x4077
#define regNBIF_TRAP_NP_RESPONSE_DATA32_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA33 0x4078
#define regNBIF_TRAP_NP_RESPONSE_DATA33_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA34 0x4079
#define regNBIF_TRAP_NP_RESPONSE_DATA34_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA35 0x407a
#define regNBIF_TRAP_NP_RESPONSE_DATA35_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA36 0x407b
#define regNBIF_TRAP_NP_RESPONSE_DATA36_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA37 0x407c
#define regNBIF_TRAP_NP_RESPONSE_DATA37_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA38 0x407d
#define regNBIF_TRAP_NP_RESPONSE_DATA38_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA39 0x407e
#define regNBIF_TRAP_NP_RESPONSE_DATA39_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA40 0x407f
#define regNBIF_TRAP_NP_RESPONSE_DATA40_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA41 0x4080
#define regNBIF_TRAP_NP_RESPONSE_DATA41_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA42 0x4081
#define regNBIF_TRAP_NP_RESPONSE_DATA42_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA43 0x4082
#define regNBIF_TRAP_NP_RESPONSE_DATA43_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA44 0x4083
#define regNBIF_TRAP_NP_RESPONSE_DATA44_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA45 0x4084
#define regNBIF_TRAP_NP_RESPONSE_DATA45_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA46 0x4085
#define regNBIF_TRAP_NP_RESPONSE_DATA46_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA47 0x4086
#define regNBIF_TRAP_NP_RESPONSE_DATA47_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA48 0x4087
#define regNBIF_TRAP_NP_RESPONSE_DATA48_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA49 0x4088
#define regNBIF_TRAP_NP_RESPONSE_DATA49_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA50 0x4089
#define regNBIF_TRAP_NP_RESPONSE_DATA50_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA51 0x408a
#define regNBIF_TRAP_NP_RESPONSE_DATA51_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA52 0x408b
#define regNBIF_TRAP_NP_RESPONSE_DATA52_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA53 0x408c
#define regNBIF_TRAP_NP_RESPONSE_DATA53_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA54 0x408d
#define regNBIF_TRAP_NP_RESPONSE_DATA54_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA55 0x408e
#define regNBIF_TRAP_NP_RESPONSE_DATA55_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA56 0x408f
#define regNBIF_TRAP_NP_RESPONSE_DATA56_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA57 0x4090
#define regNBIF_TRAP_NP_RESPONSE_DATA57_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA58 0x4091
#define regNBIF_TRAP_NP_RESPONSE_DATA58_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA59 0x4092
#define regNBIF_TRAP_NP_RESPONSE_DATA59_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA60 0x4093
#define regNBIF_TRAP_NP_RESPONSE_DATA60_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA61 0x4094
#define regNBIF_TRAP_NP_RESPONSE_DATA61_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA62 0x4095
#define regNBIF_TRAP_NP_RESPONSE_DATA62_BASE_IDX 5
#define regNBIF_TRAP_NP_RESPONSE_DATA63 0x4096
#define regNBIF_TRAP_NP_RESPONSE_DATA63_BASE_IDX 5
#define regNBIF_TRAP_NP_0_CONTROL0 0x4097
#define regNBIF_TRAP_NP_0_CONTROL0_BASE_IDX 5
#define regNBIF_TRAP_NP_0_ADDRESS_LO 0x4098
#define regNBIF_TRAP_NP_0_ADDRESS_LO_BASE_IDX 5
#define regNBIF_TRAP_NP_0_ADDRESS_HI 0x4099
#define regNBIF_TRAP_NP_0_ADDRESS_HI_BASE_IDX 5
#define regNBIF_TRAP_NP_0_COMMAND 0x409a
#define regNBIF_TRAP_NP_0_COMMAND_BASE_IDX 5
#define regNBIF_TRAP_NP_0_ADDRESS_LO_MASK 0x409b
#define regNBIF_TRAP_NP_0_ADDRESS_LO_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_0_ADDRESS_HI_MASK 0x409c
#define regNBIF_TRAP_NP_0_ADDRESS_HI_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_0_COMMAND_MASK 0x409d
#define regNBIF_TRAP_NP_0_COMMAND_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_1_CONTROL0 0x409e
#define regNBIF_TRAP_NP_1_CONTROL0_BASE_IDX 5
#define regNBIF_TRAP_NP_1_ADDRESS_LO 0x409f
#define regNBIF_TRAP_NP_1_ADDRESS_LO_BASE_IDX 5
#define regNBIF_TRAP_NP_1_ADDRESS_HI 0x40a0
#define regNBIF_TRAP_NP_1_ADDRESS_HI_BASE_IDX 5
#define regNBIF_TRAP_NP_1_COMMAND 0x40a1
#define regNBIF_TRAP_NP_1_COMMAND_BASE_IDX 5
#define regNBIF_TRAP_NP_1_ADDRESS_LO_MASK 0x40a2
#define regNBIF_TRAP_NP_1_ADDRESS_LO_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_1_ADDRESS_HI_MASK 0x40a3
#define regNBIF_TRAP_NP_1_ADDRESS_HI_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_1_COMMAND_MASK 0x40a4
#define regNBIF_TRAP_NP_1_COMMAND_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_2_CONTROL0 0x40a5
#define regNBIF_TRAP_NP_2_CONTROL0_BASE_IDX 5
#define regNBIF_TRAP_NP_2_ADDRESS_LO 0x40a6
#define regNBIF_TRAP_NP_2_ADDRESS_LO_BASE_IDX 5
#define regNBIF_TRAP_NP_2_ADDRESS_HI 0x40a7
#define regNBIF_TRAP_NP_2_ADDRESS_HI_BASE_IDX 5
#define regNBIF_TRAP_NP_2_COMMAND 0x40a8
#define regNBIF_TRAP_NP_2_COMMAND_BASE_IDX 5
#define regNBIF_TRAP_NP_2_ADDRESS_LO_MASK 0x40a9
#define regNBIF_TRAP_NP_2_ADDRESS_LO_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_2_ADDRESS_HI_MASK 0x40aa
#define regNBIF_TRAP_NP_2_ADDRESS_HI_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_2_COMMAND_MASK 0x40ab
#define regNBIF_TRAP_NP_2_COMMAND_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_3_CONTROL0 0x40ac
#define regNBIF_TRAP_NP_3_CONTROL0_BASE_IDX 5
#define regNBIF_TRAP_NP_3_ADDRESS_LO 0x40ad
#define regNBIF_TRAP_NP_3_ADDRESS_LO_BASE_IDX 5
#define regNBIF_TRAP_NP_3_ADDRESS_HI 0x40ae
#define regNBIF_TRAP_NP_3_ADDRESS_HI_BASE_IDX 5
#define regNBIF_TRAP_NP_3_COMMAND 0x40af
#define regNBIF_TRAP_NP_3_COMMAND_BASE_IDX 5
#define regNBIF_TRAP_NP_3_ADDRESS_LO_MASK 0x40b0
#define regNBIF_TRAP_NP_3_ADDRESS_LO_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_3_ADDRESS_HI_MASK 0x40b1
#define regNBIF_TRAP_NP_3_ADDRESS_HI_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_3_COMMAND_MASK 0x40b2
#define regNBIF_TRAP_NP_3_COMMAND_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_4_CONTROL0 0x40b3
#define regNBIF_TRAP_NP_4_CONTROL0_BASE_IDX 5
#define regNBIF_TRAP_NP_4_ADDRESS_LO 0x40b4
#define regNBIF_TRAP_NP_4_ADDRESS_LO_BASE_IDX 5
#define regNBIF_TRAP_NP_4_ADDRESS_HI 0x40b5
#define regNBIF_TRAP_NP_4_ADDRESS_HI_BASE_IDX 5
#define regNBIF_TRAP_NP_4_COMMAND 0x40b6
#define regNBIF_TRAP_NP_4_COMMAND_BASE_IDX 5
#define regNBIF_TRAP_NP_4_ADDRESS_LO_MASK 0x40b7
#define regNBIF_TRAP_NP_4_ADDRESS_LO_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_4_ADDRESS_HI_MASK 0x40b8
#define regNBIF_TRAP_NP_4_ADDRESS_HI_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_4_COMMAND_MASK 0x40b9
#define regNBIF_TRAP_NP_4_COMMAND_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_5_CONTROL0 0x40ba
#define regNBIF_TRAP_NP_5_CONTROL0_BASE_IDX 5
#define regNBIF_TRAP_NP_5_ADDRESS_LO 0x40bb
#define regNBIF_TRAP_NP_5_ADDRESS_LO_BASE_IDX 5
#define regNBIF_TRAP_NP_5_ADDRESS_HI 0x40bc
#define regNBIF_TRAP_NP_5_ADDRESS_HI_BASE_IDX 5
#define regNBIF_TRAP_NP_5_COMMAND 0x40bd
#define regNBIF_TRAP_NP_5_COMMAND_BASE_IDX 5
#define regNBIF_TRAP_NP_5_ADDRESS_LO_MASK 0x40be
#define regNBIF_TRAP_NP_5_ADDRESS_LO_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_5_ADDRESS_HI_MASK 0x40bf
#define regNBIF_TRAP_NP_5_ADDRESS_HI_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_5_COMMAND_MASK 0x40c0
#define regNBIF_TRAP_NP_5_COMMAND_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_6_CONTROL0 0x40c1
#define regNBIF_TRAP_NP_6_CONTROL0_BASE_IDX 5
#define regNBIF_TRAP_NP_6_ADDRESS_LO 0x40c2
#define regNBIF_TRAP_NP_6_ADDRESS_LO_BASE_IDX 5
#define regNBIF_TRAP_NP_6_ADDRESS_HI 0x40c3
#define regNBIF_TRAP_NP_6_ADDRESS_HI_BASE_IDX 5
#define regNBIF_TRAP_NP_6_COMMAND 0x40c4
#define regNBIF_TRAP_NP_6_COMMAND_BASE_IDX 5
#define regNBIF_TRAP_NP_6_ADDRESS_LO_MASK 0x40c5
#define regNBIF_TRAP_NP_6_ADDRESS_LO_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_6_ADDRESS_HI_MASK 0x40c6
#define regNBIF_TRAP_NP_6_ADDRESS_HI_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_6_COMMAND_MASK 0x40c7
#define regNBIF_TRAP_NP_6_COMMAND_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_7_CONTROL0 0x40c8
#define regNBIF_TRAP_NP_7_CONTROL0_BASE_IDX 5
#define regNBIF_TRAP_NP_7_ADDRESS_LO 0x40c9
#define regNBIF_TRAP_NP_7_ADDRESS_LO_BASE_IDX 5
#define regNBIF_TRAP_NP_7_ADDRESS_HI 0x40ca
#define regNBIF_TRAP_NP_7_ADDRESS_HI_BASE_IDX 5
#define regNBIF_TRAP_NP_7_COMMAND 0x40cb
#define regNBIF_TRAP_NP_7_COMMAND_BASE_IDX 5
#define regNBIF_TRAP_NP_7_ADDRESS_LO_MASK 0x40cc
#define regNBIF_TRAP_NP_7_ADDRESS_LO_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_7_ADDRESS_HI_MASK 0x40cd
#define regNBIF_TRAP_NP_7_ADDRESS_HI_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_7_COMMAND_MASK 0x40ce
#define regNBIF_TRAP_NP_7_COMMAND_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_8_CONTROL0 0x40cf
#define regNBIF_TRAP_NP_8_CONTROL0_BASE_IDX 5
#define regNBIF_TRAP_NP_8_ADDRESS_LO 0x40d0
#define regNBIF_TRAP_NP_8_ADDRESS_LO_BASE_IDX 5
#define regNBIF_TRAP_NP_8_ADDRESS_HI 0x40d1
#define regNBIF_TRAP_NP_8_ADDRESS_HI_BASE_IDX 5
#define regNBIF_TRAP_NP_8_COMMAND 0x40d2
#define regNBIF_TRAP_NP_8_COMMAND_BASE_IDX 5
#define regNBIF_TRAP_NP_8_ADDRESS_LO_MASK 0x40d3
#define regNBIF_TRAP_NP_8_ADDRESS_LO_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_8_ADDRESS_HI_MASK 0x40d4
#define regNBIF_TRAP_NP_8_ADDRESS_HI_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_8_COMMAND_MASK 0x40d5
#define regNBIF_TRAP_NP_8_COMMAND_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_9_CONTROL0 0x40d6
#define regNBIF_TRAP_NP_9_CONTROL0_BASE_IDX 5
#define regNBIF_TRAP_NP_9_ADDRESS_LO 0x40d7
#define regNBIF_TRAP_NP_9_ADDRESS_LO_BASE_IDX 5
#define regNBIF_TRAP_NP_9_ADDRESS_HI 0x40d8
#define regNBIF_TRAP_NP_9_ADDRESS_HI_BASE_IDX 5
#define regNBIF_TRAP_NP_9_COMMAND 0x40d9
#define regNBIF_TRAP_NP_9_COMMAND_BASE_IDX 5
#define regNBIF_TRAP_NP_9_ADDRESS_LO_MASK 0x40da
#define regNBIF_TRAP_NP_9_ADDRESS_LO_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_9_ADDRESS_HI_MASK 0x40db
#define regNBIF_TRAP_NP_9_ADDRESS_HI_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_9_COMMAND_MASK 0x40dc
#define regNBIF_TRAP_NP_9_COMMAND_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_10_CONTROL0 0x40dd
#define regNBIF_TRAP_NP_10_CONTROL0_BASE_IDX 5
#define regNBIF_TRAP_NP_10_ADDRESS_LO 0x40de
#define regNBIF_TRAP_NP_10_ADDRESS_LO_BASE_IDX 5
#define regNBIF_TRAP_NP_10_ADDRESS_HI 0x40df
#define regNBIF_TRAP_NP_10_ADDRESS_HI_BASE_IDX 5
#define regNBIF_TRAP_NP_10_COMMAND 0x40e0
#define regNBIF_TRAP_NP_10_COMMAND_BASE_IDX 5
#define regNBIF_TRAP_NP_10_ADDRESS_LO_MASK 0x40e1
#define regNBIF_TRAP_NP_10_ADDRESS_LO_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_10_ADDRESS_HI_MASK 0x40e2
#define regNBIF_TRAP_NP_10_ADDRESS_HI_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_10_COMMAND_MASK 0x40e3
#define regNBIF_TRAP_NP_10_COMMAND_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_11_CONTROL0 0x40e4
#define regNBIF_TRAP_NP_11_CONTROL0_BASE_IDX 5
#define regNBIF_TRAP_NP_11_ADDRESS_LO 0x40e5
#define regNBIF_TRAP_NP_11_ADDRESS_LO_BASE_IDX 5
#define regNBIF_TRAP_NP_11_ADDRESS_HI 0x40e6
#define regNBIF_TRAP_NP_11_ADDRESS_HI_BASE_IDX 5
#define regNBIF_TRAP_NP_11_COMMAND 0x40e7
#define regNBIF_TRAP_NP_11_COMMAND_BASE_IDX 5
#define regNBIF_TRAP_NP_11_ADDRESS_LO_MASK 0x40e8
#define regNBIF_TRAP_NP_11_ADDRESS_LO_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_11_ADDRESS_HI_MASK 0x40e9
#define regNBIF_TRAP_NP_11_ADDRESS_HI_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_11_COMMAND_MASK 0x40ea
#define regNBIF_TRAP_NP_11_COMMAND_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_12_CONTROL0 0x40eb
#define regNBIF_TRAP_NP_12_CONTROL0_BASE_IDX 5
#define regNBIF_TRAP_NP_12_ADDRESS_LO 0x40ec
#define regNBIF_TRAP_NP_12_ADDRESS_LO_BASE_IDX 5
#define regNBIF_TRAP_NP_12_ADDRESS_HI 0x40ed
#define regNBIF_TRAP_NP_12_ADDRESS_HI_BASE_IDX 5
#define regNBIF_TRAP_NP_12_COMMAND 0x40ee
#define regNBIF_TRAP_NP_12_COMMAND_BASE_IDX 5
#define regNBIF_TRAP_NP_12_ADDRESS_LO_MASK 0x40ef
#define regNBIF_TRAP_NP_12_ADDRESS_LO_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_12_ADDRESS_HI_MASK 0x40f0
#define regNBIF_TRAP_NP_12_ADDRESS_HI_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_12_COMMAND_MASK 0x40f1
#define regNBIF_TRAP_NP_12_COMMAND_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_13_CONTROL0 0x40f2
#define regNBIF_TRAP_NP_13_CONTROL0_BASE_IDX 5
#define regNBIF_TRAP_NP_13_ADDRESS_LO 0x40f3
#define regNBIF_TRAP_NP_13_ADDRESS_LO_BASE_IDX 5
#define regNBIF_TRAP_NP_13_ADDRESS_HI 0x40f4
#define regNBIF_TRAP_NP_13_ADDRESS_HI_BASE_IDX 5
#define regNBIF_TRAP_NP_13_COMMAND 0x40f5
#define regNBIF_TRAP_NP_13_COMMAND_BASE_IDX 5
#define regNBIF_TRAP_NP_13_ADDRESS_LO_MASK 0x40f6
#define regNBIF_TRAP_NP_13_ADDRESS_LO_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_13_ADDRESS_HI_MASK 0x40f7
#define regNBIF_TRAP_NP_13_ADDRESS_HI_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_13_COMMAND_MASK 0x40f8
#define regNBIF_TRAP_NP_13_COMMAND_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_14_CONTROL0 0x40f9
#define regNBIF_TRAP_NP_14_CONTROL0_BASE_IDX 5
#define regNBIF_TRAP_NP_14_ADDRESS_LO 0x40fa
#define regNBIF_TRAP_NP_14_ADDRESS_LO_BASE_IDX 5
#define regNBIF_TRAP_NP_14_ADDRESS_HI 0x40fb
#define regNBIF_TRAP_NP_14_ADDRESS_HI_BASE_IDX 5
#define regNBIF_TRAP_NP_14_COMMAND 0x40fc
#define regNBIF_TRAP_NP_14_COMMAND_BASE_IDX 5
#define regNBIF_TRAP_NP_14_ADDRESS_LO_MASK 0x40fd
#define regNBIF_TRAP_NP_14_ADDRESS_LO_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_14_ADDRESS_HI_MASK 0x40fe
#define regNBIF_TRAP_NP_14_ADDRESS_HI_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_14_COMMAND_MASK 0x40ff
#define regNBIF_TRAP_NP_14_COMMAND_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_15_CONTROL0 0x4100
#define regNBIF_TRAP_NP_15_CONTROL0_BASE_IDX 5
#define regNBIF_TRAP_NP_15_ADDRESS_LO 0x4101
#define regNBIF_TRAP_NP_15_ADDRESS_LO_BASE_IDX 5
#define regNBIF_TRAP_NP_15_ADDRESS_HI 0x4102
#define regNBIF_TRAP_NP_15_ADDRESS_HI_BASE_IDX 5
#define regNBIF_TRAP_NP_15_COMMAND 0x4103
#define regNBIF_TRAP_NP_15_COMMAND_BASE_IDX 5
#define regNBIF_TRAP_NP_15_ADDRESS_LO_MASK 0x4104
#define regNBIF_TRAP_NP_15_ADDRESS_LO_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_15_ADDRESS_HI_MASK 0x4105
#define regNBIF_TRAP_NP_15_ADDRESS_HI_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_15_COMMAND_MASK 0x4106
#define regNBIF_TRAP_NP_15_COMMAND_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_S2_CONTROL0 0x4107
#define regNBIF_TRAP_NP_S2_CONTROL0_BASE_IDX 5
#define regNBIF_TRAP_NP_S2_ADDRESS_LO 0x4108
#define regNBIF_TRAP_NP_S2_ADDRESS_LO_BASE_IDX 5
#define regNBIF_TRAP_NP_S2_ADDRESS_HI 0x4109
#define regNBIF_TRAP_NP_S2_ADDRESS_HI_BASE_IDX 5
#define regNBIF_TRAP_NP_S2_COMMAND 0x410a
#define regNBIF_TRAP_NP_S2_COMMAND_BASE_IDX 5
#define regNBIF_TRAP_NP_S2_ADDRESS_LO_MASK 0x410b
#define regNBIF_TRAP_NP_S2_ADDRESS_LO_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_S2_ADDRESS_HI_MASK 0x410c
#define regNBIF_TRAP_NP_S2_ADDRESS_HI_MASK_BASE_IDX 5
#define regNBIF_TRAP_NP_S2_COMMAND_MASK 0x410d
#define regNBIF_TRAP_NP_S2_COMMAND_MASK_BASE_IDX 5
#define regBIFL_RAS_CENTRAL_CNTL 0xe400
#define regBIFL_RAS_CENTRAL_CNTL_BASE_IDX 5
#define regBIFL_RAS_CENTRAL_STATUS 0xe404
#define regBIFL_RAS_CENTRAL_STATUS_BASE_IDX 5
#define regBIFL_RAS_LEAF0_CTRL 0xe408
#define regBIFL_RAS_LEAF0_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF1_CTRL 0xe409
#define regBIFL_RAS_LEAF1_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF2_CTRL 0xe40a
#define regBIFL_RAS_LEAF2_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF3_CTRL 0xe40b
#define regBIFL_RAS_LEAF3_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF4_CTRL 0xe40c
#define regBIFL_RAS_LEAF4_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF5_CTRL 0xe40d
#define regBIFL_RAS_LEAF5_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF6_CTRL 0xe40e
#define regBIFL_RAS_LEAF6_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF7_CTRL 0xe40f
#define regBIFL_RAS_LEAF7_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF8_CTRL 0xe410
#define regBIFL_RAS_LEAF8_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF9_CTRL 0xe411
#define regBIFL_RAS_LEAF9_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF10_CTRL 0xe412
#define regBIFL_RAS_LEAF10_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF11_CTRL 0xe413
#define regBIFL_RAS_LEAF11_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF12_CTRL 0xe414
#define regBIFL_RAS_LEAF12_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF13_CTRL 0xe415
#define regBIFL_RAS_LEAF13_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF14_CTRL 0xe416
#define regBIFL_RAS_LEAF14_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF15_CTRL 0xe417
#define regBIFL_RAS_LEAF15_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF16_CTRL 0xe418
#define regBIFL_RAS_LEAF16_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF17_CTRL 0xe419
#define regBIFL_RAS_LEAF17_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF18_CTRL 0xe41a
#define regBIFL_RAS_LEAF18_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF19_CTRL 0xe41b
#define regBIFL_RAS_LEAF19_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF2_MISC_CTRL 0xe42e
#define regBIFL_RAS_LEAF2_MISC_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF2_MISC_CTRL2 0xe42f
#define regBIFL_RAS_LEAF2_MISC_CTRL2_BASE_IDX 5
#define regBIFL_RAS_LEAF_NTB_CTRL 0xe430
#define regBIFL_RAS_LEAF_NTB_CTRL_BASE_IDX 5
#define regBIFL_RAS_LEAF0_STATUS 0xe431
#define regBIFL_RAS_LEAF0_STATUS_BASE_IDX 5
#define regBIFL_RAS_LEAF1_STATUS 0xe432
#define regBIFL_RAS_LEAF1_STATUS_BASE_IDX 5
#define regBIFL_RAS_LEAF2_STATUS 0xe433
#define regBIFL_RAS_LEAF2_STATUS_BASE_IDX 5
#define regBIFL_RAS_LEAF3_STATUS 0xe434
#define regBIFL_RAS_LEAF3_STATUS_BASE_IDX 5
#define regBIFL_RAS_LEAF4_STATUS 0xe435
#define regBIFL_RAS_LEAF4_STATUS_BASE_IDX 5
#define regBIFL_RAS_LEAF5_STATUS 0xe436
#define regBIFL_RAS_LEAF5_STATUS_BASE_IDX 5
#define regBIFL_RAS_LEAF6_STATUS 0xe437
#define regBIFL_RAS_LEAF6_STATUS_BASE_IDX 5
#define regBIFL_RAS_LEAF7_STATUS 0xe438
#define regBIFL_RAS_LEAF7_STATUS_BASE_IDX 5
#define regBIFL_RAS_LEAF8_STATUS 0xe439
#define regBIFL_RAS_LEAF8_STATUS_BASE_IDX 5
#define regBIFL_RAS_LEAF9_STATUS 0xe43a
#define regBIFL_RAS_LEAF9_STATUS_BASE_IDX 5
#define regBIFL_RAS_LEAF10_STATUS 0xe43b
#define regBIFL_RAS_LEAF10_STATUS_BASE_IDX 5
#define regBIFL_RAS_LEAF11_STATUS 0xe43c
#define regBIFL_RAS_LEAF11_STATUS_BASE_IDX 5
#define regBIFL_RAS_LEAF12_STATUS 0xe43d
#define regBIFL_RAS_LEAF12_STATUS_BASE_IDX 5
#define regBIFL_RAS_LEAF13_STATUS 0xe43e
#define regBIFL_RAS_LEAF13_STATUS_BASE_IDX 5
#define regBIFL_RAS_LEAF14_STATUS 0xe43f
#define regBIFL_RAS_LEAF14_STATUS_BASE_IDX 5
#define regBIFL_RAS_LEAF15_STATUS 0xe440
#define regBIFL_RAS_LEAF15_STATUS_BASE_IDX 5
#define regBIFL_RAS_LEAF16_STATUS 0xe441
#define regBIFL_RAS_LEAF16_STATUS_BASE_IDX 5
#define regBIFL_RAS_LEAF17_STATUS 0xe442
#define regBIFL_RAS_LEAF17_STATUS_BASE_IDX 5
#define regBIFL_RAS_LEAF18_STATUS 0xe443
#define regBIFL_RAS_LEAF18_STATUS_BASE_IDX 5
#define regBIFL_RAS_LEAF19_STATUS 0xe444
#define regBIFL_RAS_LEAF19_STATUS_BASE_IDX 5
#define regBIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP 0xe450
#define regBIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP_BASE_IDX 5
#define regBIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP 0xe451
#define regBIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP_BASE_IDX 5
#define regBIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP 0xe452
#define regBIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP_BASE_IDX 5
#define regBIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP 0xe453
#define regBIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP_BASE_IDX 5
#define regBIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP 0xe458
#define regBIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP_BASE_IDX 5
#define regBIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP 0xe459
#define regBIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP_BASE_IDX 5
#define regBIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP 0xe45a
#define regBIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP_BASE_IDX 5
#define regBIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP 0xe45b
#define regBIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP_BASE_IDX 5
#define regBIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP 0xe460
#define regBIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP_BASE_IDX 5
#define regBIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP 0xe461
#define regBIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP_BASE_IDX 5
#define regBIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP 0xe462
#define regBIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP_BASE_IDX 5
#define regBIFL_DFV_POISON_INJ_LOG_ATHUB_ORIG_SDP 0xe463
#define regBIFL_DFV_POISON_INJ_LOG_ATHUB_ORIG_SDP_BASE_IDX 5
#define regBIFL_IOHUB_RAS_IH_CNTL 0xe7fe
#define regBIFL_IOHUB_RAS_IH_CNTL_BASE_IDX 5
#define regBIFL_RAS_VWR_FROM_IOHUB 0xe7ff
#define regBIFL_RAS_VWR_FROM_IOHUB_BASE_IDX 5
#define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED 0x8d88
#define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED_BASE_IDX 5
#define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH 0x8d89
#define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH_BASE_IDX 5
#define regRCC_DWN_DEV0_2_DN_PCIE_CNTL 0x8d8b
#define regRCC_DWN_DEV0_2_DN_PCIE_CNTL_BASE_IDX 5
#define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL 0x8d8c
#define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL_BASE_IDX 5
#define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 0x8d8d
#define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2_BASE_IDX 5
#define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL 0x8d8e
#define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL_BASE_IDX 5
#define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL 0x8d8f
#define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL_BASE_IDX 5
#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0 0x8d90
#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0_BASE_IDX 5
#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC 0x8d91
#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC_BASE_IDX 5
#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2 0x8d92
#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2_BASE_IDX 5
#define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL 0x8d94
#define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL_BASE_IDX 5
#define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL 0x8d95
#define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL_BASE_IDX 5
#define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL 0x8d96
#define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL_BASE_IDX 5
#define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2 0x8d97
#define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2_BASE_IDX 5
#define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC 0x8d98
#define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC_BASE_IDX 5
#define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP 0x8d99
#define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP_BASE_IDX 5
#define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH 0x8d6b
#define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH_BASE_IDX 5
#define regRCC_EP_DEV0_2_EP_PCIE_CNTL 0x8d6d
#define regRCC_EP_DEV0_2_EP_PCIE_CNTL_BASE_IDX 5
#define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL 0x8d6e
#define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL_BASE_IDX 5
#define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS 0x8d6f
#define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS_BASE_IDX 5
#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 0x8d70
#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2_BASE_IDX 5
#define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL 0x8d71
#define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL_BASE_IDX 5
#define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL 0x8d72
#define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL_BASE_IDX 5
#define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL 0x8d74
#define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL_BASE_IDX 5
#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x8d75
#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5
#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x8d75
#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5
#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x8d75
#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5
#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x8d75
#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5
#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x8d76
#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5
#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x8d76
#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5
#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x8d76
#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5
#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x8d76
#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5
#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC 0x8d77
#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC_BASE_IDX 5
#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2 0x8d78
#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2_BASE_IDX 5
#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP 0x8d7a
#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP_BASE_IDX 5
#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x8d7b
#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 5
#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL 0x8d7b
#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL_BASE_IDX 5
#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x8d7b
#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5
#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x8d7c
#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5
#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x8d7c
#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5
#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x8d7c
#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5
#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x8d7c
#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5
#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x8d7d
#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5
#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x8d7d
#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5
#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x8d7d
#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5
#define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL 0x8d7d
#define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL_BASE_IDX 5
#define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED 0x8d7e
#define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED_BASE_IDX 5
#define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL 0x8d80
#define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL_BASE_IDX 5
#define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID 0x8d81
#define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 5
#define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL 0x8d82
#define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL_BASE_IDX 5
#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL 0x8d83
#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL_BASE_IDX 5
#define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL 0x8d84
#define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 5
#define regRCC_EP_DEV0_2_EP_PCIE_DEVICE_CNTL3 0x8d85
#define regRCC_EP_DEV0_2_EP_PCIE_DEVICE_CNTL3_BASE_IDX 5
#define regRCC_DEV0_1_RCC_ERR_INT_CNTL 0x8da6
#define regRCC_DEV0_1_RCC_ERR_INT_CNTL_BASE_IDX 5
#define regRCC_DEV0_1_RCC_BACO_CNTL_MISC 0x8da7
#define regRCC_DEV0_1_RCC_BACO_CNTL_MISC_BASE_IDX 5
#define regRCC_DEV0_1_RCC_RESET_EN 0x8da8
#define regRCC_DEV0_1_RCC_RESET_EN_BASE_IDX 5
#define regRCC_DEV0_2_RCC_VDM_SUPPORT 0x8da9
#define regRCC_DEV0_2_RCC_VDM_SUPPORT_BASE_IDX 5
#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0 0x8daa
#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 5
#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1 0x8dab
#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 5
#define regRCC_DEV0_1_RCC_GPUIOV_REGION 0x8dac
#define regRCC_DEV0_1_RCC_GPUIOV_REGION_BASE_IDX 5
#define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN 0x8dad
#define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN_BASE_IDX 5
#define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL 0x8dae
#define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 5
#define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x8daf
#define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 5
#define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE 0x8daf
#define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 5
#define regRCC_DEV0_1_RCC_PEER_REG_RANGE0 0x8dde
#define regRCC_DEV0_1_RCC_PEER_REG_RANGE0_BASE_IDX 5
#define regRCC_DEV0_1_RCC_PEER_REG_RANGE1 0x8ddf
#define regRCC_DEV0_1_RCC_PEER_REG_RANGE1_BASE_IDX 5
#define regRCC_DEV0_2_RCC_BUS_CNTL 0x8de1
#define regRCC_DEV0_2_RCC_BUS_CNTL_BASE_IDX 5
#define regRCC_DEV0_1_RCC_CONFIG_CNTL 0x8de2
#define regRCC_DEV0_1_RCC_CONFIG_CNTL_BASE_IDX 5
#define regRCC_DEV0_1_RCC_CONFIG_F0_BASE 0x8de6
#define regRCC_DEV0_1_RCC_CONFIG_F0_BASE_BASE_IDX 5
#define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE 0x8de7
#define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE_BASE_IDX 5
#define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE 0x8de8
#define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 5
#define regRCC_DEV0_1_RCC_XDMA_LO 0x8de9
#define regRCC_DEV0_1_RCC_XDMA_LO_BASE_IDX 5
#define regRCC_DEV0_1_RCC_XDMA_HI 0x8dea
#define regRCC_DEV0_1_RCC_XDMA_HI_BASE_IDX 5
#define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC 0x8deb
#define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC_BASE_IDX 5
#define regRCC_DEV0_1_RCC_BUSNUM_CNTL1 0x8dec
#define regRCC_DEV0_1_RCC_BUSNUM_CNTL1_BASE_IDX 5
#define regRCC_DEV0_1_RCC_BUSNUM_LIST0 0x8ded
#define regRCC_DEV0_1_RCC_BUSNUM_LIST0_BASE_IDX 5
#define regRCC_DEV0_1_RCC_BUSNUM_LIST1 0x8dee
#define regRCC_DEV0_1_RCC_BUSNUM_LIST1_BASE_IDX 5
#define regRCC_DEV0_1_RCC_BUSNUM_CNTL2 0x8def
#define regRCC_DEV0_1_RCC_BUSNUM_CNTL2_BASE_IDX 5
#define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM 0x8df0
#define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 5
#define regRCC_DEV0_1_RCC_HOST_BUSNUM 0x8df1
#define regRCC_DEV0_1_RCC_HOST_BUSNUM_BASE_IDX 5
#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI 0x8df2
#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 5
#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO 0x8df3
#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 5
#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI 0x8df4
#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 5
#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO 0x8df5
#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 5
#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI 0x8df6
#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 5
#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO 0x8df7
#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 5
#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI 0x8df8
#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 5
#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO 0x8df9
#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 5
#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0 0x8dfa
#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0_BASE_IDX 5
#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1 0x8dfb
#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1_BASE_IDX 5
#define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL 0x8dfd
#define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL_BASE_IDX 5
#define regRCC_DEV0_2_RCC_CMN_LINK_CNTL 0x8dfe
#define regRCC_DEV0_2_RCC_CMN_LINK_CNTL_BASE_IDX 5
#define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE 0x8dff
#define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 5
#define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL 0x8e00
#define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL_BASE_IDX 5
#define regRCC_DEV0_2_RCC_MH_ARB_CNTL 0x8e01
#define regRCC_DEV0_2_RCC_MH_ARB_CNTL_BASE_IDX 5
#define regBIF_BX1_SYSHUB_INDEX_OVLP 0x8008
#define regBIF_BX1_SYSHUB_INDEX_OVLP_BASE_IDX 5
#define regBIF_BX1_SYSHUB_DATA_OVLP 0x8009
#define regBIF_BX1_SYSHUB_DATA_OVLP_BASE_IDX 5
#define regBIF_BX1_SYSHUB_INDEX_HI_OVLP 0x800a
#define regBIF_BX1_SYSHUB_INDEX_HI_OVLP_BASE_IDX 5
#define regBIF_BX1_PCIE_INDEX 0x800c
#define regBIF_BX1_PCIE_INDEX_BASE_IDX 5
#define regBIF_BX1_PCIE_DATA 0x800d
#define regBIF_BX1_PCIE_DATA_BASE_IDX 5
#define regBIF_BX1_PCIE_INDEX2 0x800e
#define regBIF_BX1_PCIE_INDEX2_BASE_IDX 5
#define regBIF_BX1_PCIE_DATA2 0x800f
#define regBIF_BX1_PCIE_DATA2_BASE_IDX 5
#define regBIF_BX1_PCIE_INDEX_HI 0x8010
#define regBIF_BX1_PCIE_INDEX_HI_BASE_IDX 5
#define regBIF_BX1_PCIE_INDEX2_HI 0x8011
#define regBIF_BX1_PCIE_INDEX2_HI_BASE_IDX 5
#define regBIF_BX1_SBIOS_SCRATCH_0 0x8048
#define regBIF_BX1_SBIOS_SCRATCH_0_BASE_IDX 5
#define regBIF_BX1_SBIOS_SCRATCH_1 0x8049
#define regBIF_BX1_SBIOS_SCRATCH_1_BASE_IDX 5
#define regBIF_BX1_SBIOS_SCRATCH_2 0x804a
#define regBIF_BX1_SBIOS_SCRATCH_2_BASE_IDX 5
#define regBIF_BX1_SBIOS_SCRATCH_3 0x804b
#define regBIF_BX1_SBIOS_SCRATCH_3_BASE_IDX 5
#define regBIF_BX1_BIOS_SCRATCH_0 0x804c
#define regBIF_BX1_BIOS_SCRATCH_0_BASE_IDX 5
#define regBIF_BX1_BIOS_SCRATCH_1 0x804d
#define regBIF_BX1_BIOS_SCRATCH_1_BASE_IDX 5
#define regBIF_BX1_BIOS_SCRATCH_2 0x804e
#define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX 5
#define regBIF_BX1_BIOS_SCRATCH_3 0x804f
#define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX 5
#define regBIF_BX1_BIOS_SCRATCH_4 0x8050
#define regBIF_BX1_BIOS_SCRATCH_4_BASE_IDX 5
#define regBIF_BX1_BIOS_SCRATCH_5 0x8051
#define regBIF_BX1_BIOS_SCRATCH_5_BASE_IDX 5
#define regBIF_BX1_BIOS_SCRATCH_6 0x8052
#define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX 5
#define regBIF_BX1_BIOS_SCRATCH_7 0x8053
#define regBIF_BX1_BIOS_SCRATCH_7_BASE_IDX 5
#define regBIF_BX1_BIOS_SCRATCH_8 0x8054
#define regBIF_BX1_BIOS_SCRATCH_8_BASE_IDX 5
#define regBIF_BX1_BIOS_SCRATCH_9 0x8055
#define regBIF_BX1_BIOS_SCRATCH_9_BASE_IDX 5
#define regBIF_BX1_BIOS_SCRATCH_10 0x8056
#define regBIF_BX1_BIOS_SCRATCH_10_BASE_IDX 5
#define regBIF_BX1_BIOS_SCRATCH_11 0x8057
#define regBIF_BX1_BIOS_SCRATCH_11_BASE_IDX 5
#define regBIF_BX1_BIOS_SCRATCH_12 0x8058
#define regBIF_BX1_BIOS_SCRATCH_12_BASE_IDX 5
#define regBIF_BX1_BIOS_SCRATCH_13 0x8059
#define regBIF_BX1_BIOS_SCRATCH_13_BASE_IDX 5
#define regBIF_BX1_BIOS_SCRATCH_14 0x805a
#define regBIF_BX1_BIOS_SCRATCH_14_BASE_IDX 5
#define regBIF_BX1_BIOS_SCRATCH_15 0x805b
#define regBIF_BX1_BIOS_SCRATCH_15_BASE_IDX 5
#define regBIF_BX1_BIF_RLC_INTR_CNTL 0x8060
#define regBIF_BX1_BIF_RLC_INTR_CNTL_BASE_IDX 5
#define regBIF_BX1_BIF_VCE_INTR_CNTL 0x8061
#define regBIF_BX1_BIF_VCE_INTR_CNTL_BASE_IDX 5
#define regBIF_BX1_BIF_UVD_INTR_CNTL 0x8062
#define regBIF_BX1_BIF_UVD_INTR_CNTL_BASE_IDX 5
#define regBIF_BX1_BIF_Engine_INTR_CNTL 0x8063
#define regBIF_BX1_BIF_Engine_INTR_CNTL_BASE_IDX 5
#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0 0x8080
#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 5
#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 0x8081
#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 5
#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1 0x8082
#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 5
#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 0x8083
#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 5
#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2 0x8084
#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 5
#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 0x8085
#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 5
#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3 0x8086
#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 5
#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 0x8087
#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 5
#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4 0x8088
#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 5
#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 0x8089
#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 5
#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5 0x808a
#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 5
#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 0x808b
#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 5
#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6 0x808c
#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 5
#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 0x808d
#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 5
#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7 0x808e
#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 5
#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 0x808f
#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 5
#define regBIF_BX1_GFX_MMIOREG_CAM_CNTL 0x8090
#define regBIF_BX1_GFX_MMIOREG_CAM_CNTL_BASE_IDX 5
#define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL 0x8091
#define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 5
#define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL 0x8092
#define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 5
#define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x8093
#define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 5
#define regBIF_BX1_DRIVER_SCRATCH_0 0x8094
#define regBIF_BX1_DRIVER_SCRATCH_0_BASE_IDX 5
#define regBIF_BX1_DRIVER_SCRATCH_1 0x8095
#define regBIF_BX1_DRIVER_SCRATCH_1_BASE_IDX 5
#define regBIF_BX1_DRIVER_SCRATCH_2 0x8096
#define regBIF_BX1_DRIVER_SCRATCH_2_BASE_IDX 5
#define regBIF_BX1_DRIVER_SCRATCH_3 0x8097
#define regBIF_BX1_DRIVER_SCRATCH_3_BASE_IDX 5
#define regBIF_BX1_DRIVER_SCRATCH_4 0x8098
#define regBIF_BX1_DRIVER_SCRATCH_4_BASE_IDX 5
#define regBIF_BX1_DRIVER_SCRATCH_5 0x8099
#define regBIF_BX1_DRIVER_SCRATCH_5_BASE_IDX 5
#define regBIF_BX1_DRIVER_SCRATCH_6 0x809a
#define regBIF_BX1_DRIVER_SCRATCH_6_BASE_IDX 5
#define regBIF_BX1_DRIVER_SCRATCH_7 0x809b
#define regBIF_BX1_DRIVER_SCRATCH_7_BASE_IDX 5
#define regBIF_BX1_DRIVER_SCRATCH_8 0x809c
#define regBIF_BX1_DRIVER_SCRATCH_8_BASE_IDX 5
#define regBIF_BX1_DRIVER_SCRATCH_9 0x809d
#define regBIF_BX1_DRIVER_SCRATCH_9_BASE_IDX 5
#define regBIF_BX1_DRIVER_SCRATCH_10 0x809e
#define regBIF_BX1_DRIVER_SCRATCH_10_BASE_IDX 5
#define regBIF_BX1_DRIVER_SCRATCH_11 0x809f
#define regBIF_BX1_DRIVER_SCRATCH_11_BASE_IDX 5
#define regBIF_BX1_DRIVER_SCRATCH_12 0x80a0
#define regBIF_BX1_DRIVER_SCRATCH_12_BASE_IDX 5
#define regBIF_BX1_DRIVER_SCRATCH_13 0x80a1
#define regBIF_BX1_DRIVER_SCRATCH_13_BASE_IDX 5
#define regBIF_BX1_DRIVER_SCRATCH_14 0x80a2
#define regBIF_BX1_DRIVER_SCRATCH_14_BASE_IDX 5
#define regBIF_BX1_DRIVER_SCRATCH_15 0x80a3
#define regBIF_BX1_DRIVER_SCRATCH_15_BASE_IDX 5
#define regBIF_BX1_FW_SCRATCH_0 0x80a4
#define regBIF_BX1_FW_SCRATCH_0_BASE_IDX 5
#define regBIF_BX1_FW_SCRATCH_1 0x80a5
#define regBIF_BX1_FW_SCRATCH_1_BASE_IDX 5
#define regBIF_BX1_FW_SCRATCH_2 0x80a6
#define regBIF_BX1_FW_SCRATCH_2_BASE_IDX 5
#define regBIF_BX1_FW_SCRATCH_3 0x80a7
#define regBIF_BX1_FW_SCRATCH_3_BASE_IDX 5
#define regBIF_BX1_FW_SCRATCH_4 0x80a8
#define regBIF_BX1_FW_SCRATCH_4_BASE_IDX 5
#define regBIF_BX1_FW_SCRATCH_5 0x80a9
#define regBIF_BX1_FW_SCRATCH_5_BASE_IDX 5
#define regBIF_BX1_FW_SCRATCH_6 0x80aa
#define regBIF_BX1_FW_SCRATCH_6_BASE_IDX 5
#define regBIF_BX1_FW_SCRATCH_7 0x80ab
#define regBIF_BX1_FW_SCRATCH_7_BASE_IDX 5
#define regBIF_BX1_FW_SCRATCH_8 0x80ac
#define regBIF_BX1_FW_SCRATCH_8_BASE_IDX 5
#define regBIF_BX1_FW_SCRATCH_9 0x80ad
#define regBIF_BX1_FW_SCRATCH_9_BASE_IDX 5
#define regBIF_BX1_FW_SCRATCH_10 0x80ae
#define regBIF_BX1_FW_SCRATCH_10_BASE_IDX 5
#define regBIF_BX1_FW_SCRATCH_11 0x80af
#define regBIF_BX1_FW_SCRATCH_11_BASE_IDX 5
#define regBIF_BX1_FW_SCRATCH_12 0x80b0
#define regBIF_BX1_FW_SCRATCH_12_BASE_IDX 5
#define regBIF_BX1_FW_SCRATCH_13 0x80b1
#define regBIF_BX1_FW_SCRATCH_13_BASE_IDX 5
#define regBIF_BX1_FW_SCRATCH_14 0x80b2
#define regBIF_BX1_FW_SCRATCH_14_BASE_IDX 5
#define regBIF_BX1_FW_SCRATCH_15 0x80b3
#define regBIF_BX1_FW_SCRATCH_15_BASE_IDX 5
#define regBIF_BX1_SBIOS_SCRATCH_4 0x80b4
#define regBIF_BX1_SBIOS_SCRATCH_4_BASE_IDX 5
#define regBIF_BX1_SBIOS_SCRATCH_5 0x80b5
#define regBIF_BX1_SBIOS_SCRATCH_5_BASE_IDX 5
#define regBIF_BX1_SBIOS_SCRATCH_6 0x80b6
#define regBIF_BX1_SBIOS_SCRATCH_6_BASE_IDX 5
#define regBIF_BX1_SBIOS_SCRATCH_7 0x80b7
#define regBIF_BX1_SBIOS_SCRATCH_7_BASE_IDX 5
#define regBIF_BX1_SBIOS_SCRATCH_8 0x80b8
#define regBIF_BX1_SBIOS_SCRATCH_8_BASE_IDX 5
#define regBIF_BX1_SBIOS_SCRATCH_9 0x80b9
#define regBIF_BX1_SBIOS_SCRATCH_9_BASE_IDX 5
#define regBIF_BX1_SBIOS_SCRATCH_10 0x80ba
#define regBIF_BX1_SBIOS_SCRATCH_10_BASE_IDX 5
#define regBIF_BX1_SBIOS_SCRATCH_11 0x80bb
#define regBIF_BX1_SBIOS_SCRATCH_11_BASE_IDX 5
#define regBIF_BX1_SBIOS_SCRATCH_12 0x80bc
#define regBIF_BX1_SBIOS_SCRATCH_12_BASE_IDX 5
#define regBIF_BX1_SBIOS_SCRATCH_13 0x80bd
#define regBIF_BX1_SBIOS_SCRATCH_13_BASE_IDX 5
#define regBIF_BX1_SBIOS_SCRATCH_14 0x80be
#define regBIF_BX1_SBIOS_SCRATCH_14_BASE_IDX 5
#define regBIF_BX1_SBIOS_SCRATCH_15 0x80bf
#define regBIF_BX1_SBIOS_SCRATCH_15_BASE_IDX 5
#define regBIF_BX_PF1_MM_INDEX 0x8000
#define regBIF_BX_PF1_MM_INDEX_BASE_IDX 5
#define regBIF_BX_PF1_MM_DATA 0x8001
#define regBIF_BX_PF1_MM_DATA_BASE_IDX 5
#define regBIF_BX_PF1_MM_INDEX_HI 0x8006
#define regBIF_BX_PF1_MM_INDEX_HI_BASE_IDX 5
#define regBIF_BX1_CC_BIF_BX_STRAP0 0x8e02
#define regBIF_BX1_CC_BIF_BX_STRAP0_BASE_IDX 5
#define regBIF_BX1_CC_BIF_BX_PINSTRAP0 0x8e04
#define regBIF_BX1_CC_BIF_BX_PINSTRAP0_BASE_IDX 5
#define regBIF_BX1_BIF_MM_INDACCESS_CNTL 0x8e06
#define regBIF_BX1_BIF_MM_INDACCESS_CNTL_BASE_IDX 5
#define regBIF_BX1_BUS_CNTL 0x8e07
#define regBIF_BX1_BUS_CNTL_BASE_IDX 5
#define regBIF_BX1_BIF_SCRATCH0 0x8e08
#define regBIF_BX1_BIF_SCRATCH0_BASE_IDX 5
#define regBIF_BX1_BIF_SCRATCH1 0x8e09
#define regBIF_BX1_BIF_SCRATCH1_BASE_IDX 5
#define regBIF_BX1_BX_RESET_EN 0x8e0d
#define regBIF_BX1_BX_RESET_EN_BASE_IDX 5
#define regBIF_BX1_MM_CFGREGS_CNTL 0x8e0e
#define regBIF_BX1_MM_CFGREGS_CNTL_BASE_IDX 5
#define regBIF_BX1_BX_RESET_CNTL 0x8e10
#define regBIF_BX1_BX_RESET_CNTL_BASE_IDX 5
#define regBIF_BX1_INTERRUPT_CNTL 0x8e11
#define regBIF_BX1_INTERRUPT_CNTL_BASE_IDX 5
#define regBIF_BX1_INTERRUPT_CNTL2 0x8e12
#define regBIF_BX1_INTERRUPT_CNTL2_BASE_IDX 5
#define regBIF_BX1_CLKREQB_PAD_CNTL 0x8e18
#define regBIF_BX1_CLKREQB_PAD_CNTL_BASE_IDX 5
#define regBIF_BX1_BIF_FEATURES_CONTROL_MISC 0x8e1b
#define regBIF_BX1_BIF_FEATURES_CONTROL_MISC_BASE_IDX 5
#define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC 0x8e1c
#define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 5
#define regBIF_BX1_BIF_DOORBELL_CNTL 0x8e1d
#define regBIF_BX1_BIF_DOORBELL_CNTL_BASE_IDX 5
#define regBIF_BX1_BIF_DOORBELL_INT_CNTL 0x8e1e
#define regBIF_BX1_BIF_DOORBELL_INT_CNTL_BASE_IDX 5
#define regBIF_BX1_BIF_FB_EN 0x8e20
#define regBIF_BX1_BIF_FB_EN_BASE_IDX 5
#define regBIF_BX1_BIF_INTR_CNTL 0x8e21
#define regBIF_BX1_BIF_INTR_CNTL_BASE_IDX 5
#define regBIF_BX1_BIF_MST_TRANS_PENDING_VF 0x8e29
#define regBIF_BX1_BIF_MST_TRANS_PENDING_VF_BASE_IDX 5
#define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF 0x8e2a
#define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 5
#define regBIF_BX1_BACO_CNTL 0x8e2b
#define regBIF_BX1_BACO_CNTL_BASE_IDX 5
#define regBIF_BX1_BIF_BACO_EXIT_TIME0 0x8e2c
#define regBIF_BX1_BIF_BACO_EXIT_TIME0_BASE_IDX 5
#define regBIF_BX1_BIF_BACO_EXIT_TIMER1 0x8e2d
#define regBIF_BX1_BIF_BACO_EXIT_TIMER1_BASE_IDX 5
#define regBIF_BX1_BIF_BACO_EXIT_TIMER2 0x8e2e
#define regBIF_BX1_BIF_BACO_EXIT_TIMER2_BASE_IDX 5
#define regBIF_BX1_BIF_BACO_EXIT_TIMER3 0x8e2f
#define regBIF_BX1_BIF_BACO_EXIT_TIMER3_BASE_IDX 5
#define regBIF_BX1_BIF_BACO_EXIT_TIMER4 0x8e30
#define regBIF_BX1_BIF_BACO_EXIT_TIMER4_BASE_IDX 5
#define regBIF_BX1_MEM_TYPE_CNTL 0x8e31
#define regBIF_BX1_MEM_TYPE_CNTL_BASE_IDX 5
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL 0x8e33
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 5
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_0 0x8e34
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_0_BASE_IDX 5
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_1 0x8e35
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_1_BASE_IDX 5
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_2 0x8e36
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_2_BASE_IDX 5
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_3 0x8e37
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_3_BASE_IDX 5
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_4 0x8e38
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_4_BASE_IDX 5
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_5 0x8e39
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_5_BASE_IDX 5
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_6 0x8e3a
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_6_BASE_IDX 5
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_7 0x8e3b
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_7_BASE_IDX 5
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_8 0x8e3c
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_8_BASE_IDX 5
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_9 0x8e3d
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_9_BASE_IDX 5
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_10 0x8e3e
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_10_BASE_IDX 5
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_11 0x8e3f
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_11_BASE_IDX 5
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_12 0x8e40
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_12_BASE_IDX 5
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_13 0x8e41
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_13_BASE_IDX 5
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_14 0x8e42
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_14_BASE_IDX 5
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_15 0x8e43
#define regBIF_BX1_NBIF_GFX_ADDR_LUT_15_BASE_IDX 5
#define regBIF_BX1_VF_REGWR_EN 0x8e44
#define regBIF_BX1_VF_REGWR_EN_BASE_IDX 5
#define regBIF_BX1_VF_DOORBELL_EN 0x8e45
#define regBIF_BX1_VF_DOORBELL_EN_BASE_IDX 5
#define regBIF_BX1_VF_FB_EN 0x8e46
#define regBIF_BX1_VF_FB_EN_BASE_IDX 5
#define regBIF_BX1_VF_REGWR_STATUS 0x8e47
#define regBIF_BX1_VF_REGWR_STATUS_BASE_IDX 5
#define regBIF_BX1_VF_DOORBELL_STATUS 0x8e48
#define regBIF_BX1_VF_DOORBELL_STATUS_BASE_IDX 5
#define regBIF_BX1_VF_FB_STATUS 0x8e49
#define regBIF_BX1_VF_FB_STATUS_BASE_IDX 5
#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL 0x8e4d
#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 5
#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL 0x8e4e
#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 5
#define regBIF_BX1_BIF_RB_CNTL 0x8e4f
#define regBIF_BX1_BIF_RB_CNTL_BASE_IDX 5
#define regBIF_BX1_BIF_RB_BASE 0x8e50
#define regBIF_BX1_BIF_RB_BASE_BASE_IDX 5
#define regBIF_BX1_BIF_RB_RPTR 0x8e51
#define regBIF_BX1_BIF_RB_RPTR_BASE_IDX 5
#define regBIF_BX1_BIF_RB_WPTR 0x8e52
#define regBIF_BX1_BIF_RB_WPTR_BASE_IDX 5
#define regBIF_BX1_BIF_RB_WPTR_ADDR_HI 0x8e53
#define regBIF_BX1_BIF_RB_WPTR_ADDR_HI_BASE_IDX 5
#define regBIF_BX1_BIF_RB_WPTR_ADDR_LO 0x8e54
#define regBIF_BX1_BIF_RB_WPTR_ADDR_LO_BASE_IDX 5
#define regBIF_BX1_MAILBOX_INDEX 0x8e55
#define regBIF_BX1_MAILBOX_INDEX_BASE_IDX 5
#define regBIF_BX1_BACO_AZ_ENHANCE_CTRL 0x8e61
#define regBIF_BX1_BACO_AZ_ENHANCE_CTRL_BASE_IDX 5
#define regBIF_BX1_BIF_MP1_INTR_CTRL 0x8e62
#define regBIF_BX1_BIF_MP1_INTR_CTRL_BASE_IDX 5
#define regBIF_BX1_BIF_PERSTB_PAD_CNTL 0x8e65
#define regBIF_BX1_BIF_PERSTB_PAD_CNTL_BASE_IDX 5
#define regBIF_BX1_BIF_PX_EN_PAD_CNTL 0x8e66
#define regBIF_BX1_BIF_PX_EN_PAD_CNTL_BASE_IDX 5
#define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL 0x8e67
#define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 5
#define regBIF_BX1_BIF_CLKREQB_PAD_CNTL 0x8e68
#define regBIF_BX1_BIF_CLKREQB_PAD_CNTL_BASE_IDX 5
#define regBIF_BX1_BIF_PWRBRK_PAD_CNTL 0x8e69
#define regBIF_BX1_BIF_PWRBRK_PAD_CNTL_BASE_IDX 5
#define regBIF_BX1_BIF_GPUIOV_SCH_CFG_SIZE 0x8e85
#define regBIF_BX1_BIF_GPUIOV_SCH_CFG_SIZE_BASE_IDX 5
#define regBIF_BX_PF1_BIF_BME_STATUS 0x8e0b
#define regBIF_BX_PF1_BIF_BME_STATUS_BASE_IDX 5
#define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG 0x8e0c
#define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 5
#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13
#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5
#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14
#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5
#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15
#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5
#define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16
#define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5
#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17
#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5
#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19
#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5
#define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a
#define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5
#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ 0x8e26
#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_BASE_IDX 5
#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE 0x8e27
#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_BASE_IDX 5
#define regBIF_BX_PF1_BIF_TRANS_PENDING 0x8e28
#define regBIF_BX_PF1_BIF_TRANS_PENDING_BASE_IDX 5
#define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32
#define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5
#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 0x8e56
#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5
#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 0x8e57
#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5
#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 0x8e58
#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5
#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 0x8e59
#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5
#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 0x8e5a
#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5
#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 0x8e5b
#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5
#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 0x8e5c
#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5
#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 0x8e5d
#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5
#define regBIF_BX_PF1_MAILBOX_CONTROL 0x8e5e
#define regBIF_BX_PF1_MAILBOX_CONTROL_BASE_IDX 5
#define regBIF_BX_PF1_MAILBOX_INT_CNTL 0x8e5f
#define regBIF_BX_PF1_MAILBOX_INT_CNTL_BASE_IDX 5
#define regBIF_BX_PF1_BIF_VMHV_MAILBOX 0x8e60
#define regBIF_BX_PF1_BIF_VMHV_MAILBOX_BASE_IDX 5
#define regBIF_BX_PF1_PARTITION_COMPUTE_CAP 0x8e81
#define regBIF_BX_PF1_PARTITION_COMPUTE_CAP_BASE_IDX 5
#define regBIF_BX_PF1_PARTITION_MEM_CAP 0x8e82
#define regBIF_BX_PF1_PARTITION_MEM_CAP_BASE_IDX 5
#define regBIF_BX_PF1_PARTITION_COMPUTE_STATUS 0x8e83
#define regBIF_BX_PF1_PARTITION_COMPUTE_STATUS_BASE_IDX 5
#define regBIF_BX_PF1_PARTITION_MEM_STATUS 0x8e84
#define regBIF_BX_PF1_PARTITION_MEM_STATUS_BASE_IDX 5
#define regRCC_STRAP2_RCC_BIF_STRAP0 0x8d20
#define regRCC_STRAP2_RCC_BIF_STRAP0_BASE_IDX 5
#define regRCC_STRAP2_RCC_BIF_STRAP1 0x8d21
#define regRCC_STRAP2_RCC_BIF_STRAP1_BASE_IDX 5
#define regRCC_STRAP2_RCC_BIF_STRAP10 0x8d22
#define regRCC_STRAP2_RCC_BIF_STRAP10_BASE_IDX 5
#define regRCC_STRAP2_RCC_BIF_STRAP11 0x8d23
#define regRCC_STRAP2_RCC_BIF_STRAP11_BASE_IDX 5
#define regRCC_STRAP2_RCC_BIF_STRAP12 0x8d24
#define regRCC_STRAP2_RCC_BIF_STRAP12_BASE_IDX 5
#define regRCC_STRAP2_RCC_BIF_STRAP13 0x8d25
#define regRCC_STRAP2_RCC_BIF_STRAP13_BASE_IDX 5
#define regRCC_STRAP2_RCC_BIF_STRAP2 0x8d26
#define regRCC_STRAP2_RCC_BIF_STRAP2_BASE_IDX 5
#define regRCC_STRAP2_RCC_BIF_STRAP3 0x8d27
#define regRCC_STRAP2_RCC_BIF_STRAP3_BASE_IDX 5
#define regRCC_STRAP2_RCC_BIF_STRAP4 0x8d28
#define regRCC_STRAP2_RCC_BIF_STRAP4_BASE_IDX 5
#define regRCC_STRAP2_RCC_BIF_STRAP5 0x8d29
#define regRCC_STRAP2_RCC_BIF_STRAP5_BASE_IDX 5
#define regRCC_STRAP2_RCC_BIF_STRAP6 0x8d2a
#define regRCC_STRAP2_RCC_BIF_STRAP6_BASE_IDX 5
#define regRCC_STRAP2_RCC_BIF_STRAP7 0x8d2b
#define regRCC_STRAP2_RCC_BIF_STRAP7_BASE_IDX 5
#define regRCC_STRAP2_RCC_BIF_STRAP8 0x8d2c
#define regRCC_STRAP2_RCC_BIF_STRAP8_BASE_IDX 5
#define regRCC_STRAP2_RCC_BIF_STRAP9 0x8d2d
#define regRCC_STRAP2_RCC_BIF_STRAP9_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0 0x8d2e
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1 0x8d2f
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10 0x8d30
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11 0x8d31
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12 0x8d32
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13 0x8d33
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14 0x8d34
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP15 0x8d35
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP15_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP16 0x8d36
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP16_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP17 0x8d37
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP17_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP18 0x8d38
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP18_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2 0x8d39
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3 0x8d3a
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4 0x8d3b
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5 0x8d3c
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6 0x8d3d
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7 0x8d3e
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8 0x8d3f
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9 0x8d40
#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0 0x8d41
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1 0x8d42
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13 0x8d43
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14 0x8d44
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15 0x8d45
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16 0x8d46
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17 0x8d47
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18 0x8d48
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP19 0x8d49
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP19_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2 0x8d4a
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP22 0x8d4b
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP22_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP23 0x8d4c
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP23_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP24 0x8d4d
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP24_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3 0x8d4e
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4 0x8d4f
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5 0x8d50
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8 0x8d51
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9 0x8d52
#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0 0x8d53
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP1 0x8d54
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP1_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP10 0x8d55
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP10_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP11 0x8d56
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP11_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP12 0x8d57
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP12_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP13 0x8d58
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP13_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP14 0x8d59
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP14_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP15 0x8d5a
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP15_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP16 0x8d5b
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP16_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP17 0x8d5c
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP17_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP18 0x8d5d
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP18_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP19 0x8d5e
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP19_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2 0x8d5f
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20 0x8d60
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21 0x8d61
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23 0x8d62
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24 0x8d63
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3 0x8d64
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4 0x8d65
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5 0x8d66
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6 0x8d67
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7 0x8d68
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP8 0x8d69
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP8_BASE_IDX 5
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP9 0x8d6a
#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP9_BASE_IDX 5
#define regNBIF_SDP_PERF_COUNTER_2 0x100a
#define regNBIF_SDP_PERF_COUNTER_2_BASE_IDX 5
#define regNBIF_SHUB_TODET_CLIENT_STATUS3 0x10d1
#define regNBIF_SHUB_TODET_CLIENT_STATUS3_BASE_IDX 5
#define regBIF_AER_ERR_LOG_DEV0_F0 0x10d5
#define regBIF_AER_ERR_LOG_DEV0_F0_BASE_IDX 5
#define regBIF_AER_ERR_LOG_DEV0_F0_vf0 0x10d6
#define regBIF_AER_ERR_LOG_DEV0_F0_vf0_BASE_IDX 5
#define regBIF_AER_ERR_LOG_DEV0_F0_vf1 0x10d7
#define regBIF_AER_ERR_LOG_DEV0_F0_vf1_BASE_IDX 5
#define regBIF_AER_ERR_LOG_DEV0_F0_vf2 0x10d8
#define regBIF_AER_ERR_LOG_DEV0_F0_vf2_BASE_IDX 5
#define regBIF_AER_ERR_LOG_DEV0_F0_vf3 0x10d9
#define regBIF_AER_ERR_LOG_DEV0_F0_vf3_BASE_IDX 5
#define regBIF_AER_ERR_LOG_DEV0_F0_vf4 0x10da
#define regBIF_AER_ERR_LOG_DEV0_F0_vf4_BASE_IDX 5
#define regBIF_AER_ERR_LOG_DEV0_F0_vf5 0x10db
#define regBIF_AER_ERR_LOG_DEV0_F0_vf5_BASE_IDX 5
#define regBIF_AER_ERR_LOG_DEV0_F0_vf6 0x10dc
#define regBIF_AER_ERR_LOG_DEV0_F0_vf6_BASE_IDX 5
#define regBIF_AER_ERR_LOG_DEV0_F0_vf7 0x10dd
#define regBIF_AER_ERR_LOG_DEV0_F0_vf7_BASE_IDX 5
#define regNBIF_AON_SVA_DISABLE_SAD 0x189a
#define regNBIF_AON_SVA_DISABLE_SAD_BASE_IDX 5
#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0 0x4f7400
#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1 0x4f7401
#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0 0x4f7402
#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1 0x4f7403
#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0 0x4f7404
#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1 0x4f7405
#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0 0x4f7406
#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1 0x4f7407
#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG0 0x4f7408
#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG1 0x4f7409
#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG0 0x4f740a
#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG1 0x4f740b
#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0 0x4f740c
#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1 0x4f740d
#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0 0x4f740e
#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1 0x4f740f
#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0 0x4f7410
#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1 0x4f7411
#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0 0x4f7412
#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1 0x4f7413
#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0 0x4f7414
#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1 0x4f7415
#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0 0x4f7416
#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1 0x4f7417
#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0 0x4f7418
#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1 0x4f7419
#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0 0x4f741a
#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1 0x4f741b
#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG0 0x4f741c
#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG1 0x4f741d
#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG0 0x4f741e
#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG1 0x4f741f
#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0 0x4f7420
#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1 0x4f7421
#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0 0x4f7422
#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1 0x4f7423
#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0 0x4f7424
#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1 0x4f7425
#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0 0x4f7426
#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1 0x4f7427
#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0 0x4f7428
#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1 0x4f7429
#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0 0x4f742a
#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1 0x4f742b
#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0 0x4f742c
#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1 0x4f742d
#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0 0x4f742e
#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1 0x4f742f
#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG0 0x4f7430
#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG1 0x4f7431
#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG0 0x4f7432
#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG1 0x4f7433
#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0 0x4f7434
#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1 0x4f7435
#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0 0x4f7436
#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1 0x4f7437
#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0 0x4f7438
#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1 0x4f7439
#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0 0x4f743a
#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1 0x4f743b
#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3
#define regGDC_DMA_SION_CNTL_REG0 0x4f743c
#define regGDC_DMA_SION_CNTL_REG0_BASE_IDX 3
#define regGDC_DMA_SION_CNTL_REG1 0x4f743d
#define regGDC_DMA_SION_CNTL_REG1_BASE_IDX 3
#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0 0x4f7600
#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX 3
#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1 0x4f7601
#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX 3
#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0 0x4f7602
#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX 3
#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1 0x4f7603
#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX 3
#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0 0x4f7604
#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX 3
#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1 0x4f7605
#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX 3
#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0 0x4f7606
#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX 3
#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1 0x4f7607
#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX 3
#define regGDC_HST_SION_CL0_Req_BurstTarget_REG0 0x4f7608
#define regGDC_HST_SION_CL0_Req_BurstTarget_REG0_BASE_IDX 3
#define regGDC_HST_SION_CL0_Req_BurstTarget_REG1 0x4f7609
#define regGDC_HST_SION_CL0_Req_BurstTarget_REG1_BASE_IDX 3
#define regGDC_HST_SION_CL0_Req_TimeSlot_REG0 0x4f760a
#define regGDC_HST_SION_CL0_Req_TimeSlot_REG0_BASE_IDX 3
#define regGDC_HST_SION_CL0_Req_TimeSlot_REG1 0x4f760b
#define regGDC_HST_SION_CL0_Req_TimeSlot_REG1_BASE_IDX 3
#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0 0x4f760c
#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX 3
#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1 0x4f760d
#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX 3
#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0 0x4f760e
#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX 3
#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1 0x4f760f
#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX 3
#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0 0x4f7610
#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3
#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1 0x4f7611
#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3
#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0 0x4f7612
#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3
#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1 0x4f7613
#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3
#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0 0x4f7614
#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX 3
#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1 0x4f7615
#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX 3
#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0 0x4f7616
#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX 3
#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1 0x4f7617
#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX 3
#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0 0x4f7618
#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX 3
#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1 0x4f7619
#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX 3
#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0 0x4f761a
#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX 3
#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1 0x4f761b
#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX 3
#define regGDC_HST_SION_CL1_Req_BurstTarget_REG0 0x4f761c
#define regGDC_HST_SION_CL1_Req_BurstTarget_REG0_BASE_IDX 3
#define regGDC_HST_SION_CL1_Req_BurstTarget_REG1 0x4f761d
#define regGDC_HST_SION_CL1_Req_BurstTarget_REG1_BASE_IDX 3
#define regGDC_HST_SION_CL1_Req_TimeSlot_REG0 0x4f761e
#define regGDC_HST_SION_CL1_Req_TimeSlot_REG0_BASE_IDX 3
#define regGDC_HST_SION_CL1_Req_TimeSlot_REG1 0x4f761f
#define regGDC_HST_SION_CL1_Req_TimeSlot_REG1_BASE_IDX 3
#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0 0x4f7620
#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX 3
#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1 0x4f7621
#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX 3
#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0 0x4f7622
#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX 3
#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1 0x4f7623
#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX 3
#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0 0x4f7624
#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3
#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1 0x4f7625
#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3
#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0 0x4f7626
#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3
#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1 0x4f7627
#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3
#define regGDC_HST_SION_CNTL_REG0 0x4f7628
#define regGDC_HST_SION_CNTL_REG0_BASE_IDX 3
#define regGDC_HST_SION_CNTL_REG1 0x4f7629
#define regGDC_HST_SION_CNTL_REG1_BASE_IDX 3
#define regGDC1_NGDC_SDP_PORT_CTRL 0x4f0aa0
#define regGDC1_NGDC_SDP_PORT_CTRL_BASE_IDX 3
#define regGDC1_SHUB_REGS_IF_CTL 0x4f0aa1
#define regGDC1_SHUB_REGS_IF_CTL_BASE_IDX 3
#define regGDC1_NGDC_MGCG_CTRL 0x4f0aa7
#define regGDC1_NGDC_MGCG_CTRL_BASE_IDX 3
#define regGDC1_S2A_MISC_CNTL 0x4f0aa8
#define regGDC1_S2A_MISC_CNTL_BASE_IDX 3
#define regGDC1_NGDC_MCA_SMN_CTRL0 0x4f0aab
#define regGDC1_NGDC_MCA_SMN_CTRL0_BASE_IDX 3
#define regGDC1_NGDC_EARLY_WAKEUP_CTRL 0x4f0aac
#define regGDC1_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX 3
#define regGDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL 0x4f0ab8
#define regGDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL_BASE_IDX 3
#define regGDC1_GDC_DMA_SION_PCTRL 0x4f0ab9
#define regGDC1_GDC_DMA_SION_PCTRL_BASE_IDX 3
#define regGDC1_NGDC_MP4SDP_CNTL 0x4f0abb
#define regGDC1_NGDC_MP4SDP_CNTL_BASE_IDX 3
#define regGDC1_DOORBELL_VCN_TARGET_VF0 0x4f0b13
#define regGDC1_DOORBELL_VCN_TARGET_VF0_BASE_IDX 3
#define regGDC1_DOORBELL_VCN_TARGET_VF1 0x4f0b13
#define regGDC1_DOORBELL_VCN_TARGET_VF1_BASE_IDX 3
#define regGDC1_DOORBELL_VCN_TARGET_VF2 0x4f0b14
#define regGDC1_DOORBELL_VCN_TARGET_VF2_BASE_IDX 3
#define regGDC1_DOORBELL_VCN_TARGET_VF3 0x4f0b14
#define regGDC1_DOORBELL_VCN_TARGET_VF3_BASE_IDX 3
#define regGDC1_DOORBELL_VCN_TARGET_VF4 0x4f0b15
#define regGDC1_DOORBELL_VCN_TARGET_VF4_BASE_IDX 3
#define regGDC1_DOORBELL_VCN_TARGET_VF5 0x4f0b15
#define regGDC1_DOORBELL_VCN_TARGET_VF5_BASE_IDX 3
#define regGDC1_DOORBELL_VCN_TARGET_VF6 0x4f0b16
#define regGDC1_DOORBELL_VCN_TARGET_VF6_BASE_IDX 3
#define regGDC1_DOORBELL_VCN_TARGET_VF7 0x4f0b16
#define regGDC1_DOORBELL_VCN_TARGET_VF7_BASE_IDX 3
#define regGDC1_DOORBELL_ACCESS_EN_PF 0x4f0b17
#define regGDC1_DOORBELL_ACCESS_EN_PF_BASE_IDX 3
#define regGDC1_DOORBELL_ACCESS_EN_VF0 0x4f0b17
#define regGDC1_DOORBELL_ACCESS_EN_VF0_BASE_IDX 3
#define regGDC1_DOORBELL_ACCESS_EN_VF1 0x4f0b18
#define regGDC1_DOORBELL_ACCESS_EN_VF1_BASE_IDX 3
#define regGDC1_DOORBELL_ACCESS_EN_VF2 0x4f0b18
#define regGDC1_DOORBELL_ACCESS_EN_VF2_BASE_IDX 3
#define regGDC1_DOORBELL_ACCESS_EN_VF3 0x4f0b19
#define regGDC1_DOORBELL_ACCESS_EN_VF3_BASE_IDX 3
#define regGDC1_DOORBELL_ACCESS_EN_VF4 0x4f0b19
#define regGDC1_DOORBELL_ACCESS_EN_VF4_BASE_IDX 3
#define regGDC1_DOORBELL_ACCESS_EN_VF5 0x4f0b1a
#define regGDC1_DOORBELL_ACCESS_EN_VF5_BASE_IDX 3
#define regGDC1_DOORBELL_ACCESS_EN_VF6 0x4f0b1a
#define regGDC1_DOORBELL_ACCESS_EN_VF6_BASE_IDX 3
#define regGDC1_DOORBELL_ACCESS_EN_VF7 0x4f0b1b
#define regGDC1_DOORBELL_ACCESS_EN_VF7_BASE_IDX 3
#define regGDC1_NGDC_CNDI_BUS_PORT_CTRL 0x4f0b1c
#define regGDC1_NGDC_CNDI_BUS_PORT_CTRL_BASE_IDX 3
#define regGDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL 0x4f0b1d
#define regGDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL_BASE_IDX 3
#define regGDCSOC_ERR_RSP_CNTL 0x4f5c00
#define regGDCSOC_ERR_RSP_CNTL_BASE_IDX 3
#define regGDCSOC_RAS_CENTRAL_STATUS 0x4f5c10
#define regGDCSOC_RAS_CENTRAL_STATUS_BASE_IDX 3
#define regGDCSOC_RAS_LEAF0_CTRL 0x4f5c20
#define regGDCSOC_RAS_LEAF0_CTRL_BASE_IDX 3
#define regGDCSOC_RAS_LEAF1_CTRL 0x4f5c21
#define regGDCSOC_RAS_LEAF1_CTRL_BASE_IDX 3
#define regGDCSOC_RAS_LEAF2_CTRL 0x4f5c22
#define regGDCSOC_RAS_LEAF2_CTRL_BASE_IDX 3
#define regGDCSOC_RAS_LEAF3_CTRL 0x4f5c23
#define regGDCSOC_RAS_LEAF3_CTRL_BASE_IDX 3
#define regGDCSOC_RAS_LEAF4_CTRL 0x4f5c24
#define regGDCSOC_RAS_LEAF4_CTRL_BASE_IDX 3
#define regGDCSOC_RAS_LEAF5_CTRL 0x4f5c25
#define regGDCSOC_RAS_LEAF5_CTRL_BASE_IDX 3
#define regGDCSOC_RAS_LEAF6_CTRL 0x4f5c26
#define regGDCSOC_RAS_LEAF6_CTRL_BASE_IDX 3
#define regGDCSOC_RAS_LEAF7_CTRL 0x4f5c27
#define regGDCSOC_RAS_LEAF7_CTRL_BASE_IDX 3
#define regGDCSOC_RAS_LEAF8_CTRL 0x4f5c28
#define regGDCSOC_RAS_LEAF8_CTRL_BASE_IDX 3
#define regGDCSOC_RAS_LEAF9_CTRL 0x4f5c29
#define regGDCSOC_RAS_LEAF9_CTRL_BASE_IDX 3
#define regGDCSOC_RAS_LEAF10_CTRL 0x4f5c2a
#define regGDCSOC_RAS_LEAF10_CTRL_BASE_IDX 3
#define regGDCSOC_RAS_LEAF11_CTRL 0x4f5c2b
#define regGDCSOC_RAS_LEAF11_CTRL_BASE_IDX 3
#define regGDCSOC_RAS_LEAF12_CTRL 0x4f5c2c
#define regGDCSOC_RAS_LEAF12_CTRL_BASE_IDX 3
#define regGDCSOC_RAS_LEAF13_CTRL 0x4f5c2d
#define regGDCSOC_RAS_LEAF13_CTRL_BASE_IDX 3
#define regGDCSOC_RAS_LEAF0_STATUS 0x4f5c30
#define regGDCSOC_RAS_LEAF0_STATUS_BASE_IDX 3
#define regGDCSOC_RAS_LEAF1_STATUS 0x4f5c31
#define regGDCSOC_RAS_LEAF1_STATUS_BASE_IDX 3
#define regGDCSOC_RAS_LEAF2_STATUS 0x4f5c32
#define regGDCSOC_RAS_LEAF2_STATUS_BASE_IDX 3
#define regGDCSOC_RAS_LEAF3_STATUS 0x4f5c33
#define regGDCSOC_RAS_LEAF3_STATUS_BASE_IDX 3
#define regGDCSOC_RAS_LEAF4_STATUS 0x4f5c34
#define regGDCSOC_RAS_LEAF4_STATUS_BASE_IDX 3
#define regGDCSOC_RAS_LEAF5_STATUS 0x4f5c35
#define regGDCSOC_RAS_LEAF5_STATUS_BASE_IDX 3
#define regGDCSOC_RAS_LEAF6_STATUS 0x4f5c36
#define regGDCSOC_RAS_LEAF6_STATUS_BASE_IDX 3
#define regGDCSOC_RAS_LEAF7_STATUS 0x4f5c37
#define regGDCSOC_RAS_LEAF7_STATUS_BASE_IDX 3
#define regGDCSOC_RAS_LEAF8_STATUS 0x4f5c38
#define regGDCSOC_RAS_LEAF8_STATUS_BASE_IDX 3
#define regGDCSOC_RAS_LEAF9_STATUS 0x4f5c39
#define regGDCSOC_RAS_LEAF9_STATUS_BASE_IDX 3
#define regGDCSOC_RAS_LEAF10_STATUS 0x4f5c3a
#define regGDCSOC_RAS_LEAF10_STATUS_BASE_IDX 3
#define regGDCSOC_RAS_LEAF11_STATUS 0x4f5c3b
#define regGDCSOC_RAS_LEAF11_STATUS_BASE_IDX 3
#define regGDCSOC_RAS_LEAF12_STATUS 0x4f5c3c
#define regGDCSOC_RAS_LEAF12_STATUS_BASE_IDX 3
#define regGDCSOC_RAS_LEAF13_STATUS 0x4f5c3d
#define regGDCSOC_RAS_LEAF13_STATUS_BASE_IDX 3
#define regGDC_SEC_MCA_SMN_CTRL0 0x4f7001
#define regGDC_SEC_MCA_SMN_CTRL0_BASE_IDX 3
#define regGDC_SEC_MCA_SMN_CTRL1 0x4f7002
#define regGDC_SEC_MCA_SMN_CTRL1_BASE_IDX 3
#define regXCD_DOORBELL_FENCE 0x4f7003
#define regXCD_DOORBELL_FENCE_BASE_IDX 3
#define regSHUB_PWRBRK_DEGLITCH 0x4f7004
#define regSHUB_PWRBRK_DEGLITCH_BASE_IDX 3
#define regSHUB_DIE_CTRL 0x4f7005
#define regSHUB_DIE_CTRL_BASE_IDX 3
#define regGDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL 0x4f700a
#define regGDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL_BASE_IDX 3
#define regXCD_DOORBELL_FENCE_1 0x4f700b
#define regXCD_DOORBELL_FENCE_1_BASE_IDX 3
#define regNGDC_CNDI_DOORBELL_REQUSER_0 0x4f700c
#define regNGDC_CNDI_DOORBELL_REQUSER_0_BASE_IDX 3
#define regNGDC_CNDI_DOORBELL_REQUSER_1 0x4f700d
#define regNGDC_CNDI_DOORBELL_REQUSER_1_BASE_IDX 3
#define regNGDC_CNDI_DOORBELL_REQUSER_2 0x4f700e
#define regNGDC_CNDI_DOORBELL_REQUSER_2_BASE_IDX 3
#define regNGDC_CNDI_DOORBELL_REQUSER_3 0x4f700f
#define regNGDC_CNDI_DOORBELL_REQUSER_3_BASE_IDX 3
#define regNGDC_CNDI_DOORBELL_REQUSER_4 0x4f7010
#define regNGDC_CNDI_DOORBELL_REQUSER_4_BASE_IDX 3
#define regNGDC_CNDI_DOORBELL_REQUSER_5 0x4f7011
#define regNGDC_CNDI_DOORBELL_REQUSER_5_BASE_IDX 3
#define regNGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0 0x4f7012
#define regNGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0_BASE_IDX 3
#define regNGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1 0x4f7013
#define regNGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1_BASE_IDX 3
#define regSHUB_PF_FLR_RST 0x4f7800
#define regSHUB_PF_FLR_RST_BASE_IDX 3
#define regSHUB_GFX_DRV_VPU_RST 0x4f7801
#define regSHUB_GFX_DRV_VPU_RST_BASE_IDX 3
#define regSHUB_LINK_RESET 0x4f7802
#define regSHUB_LINK_RESET_BASE_IDX 3
#define regSHUB_HST_NIC400_SW_CTRL_RESET 0x4f7803
#define regSHUB_HST_NIC400_SW_CTRL_RESET_BASE_IDX 3
#define regSHUB_DEV0_PF0_VF_FLR_RST 0x4f7808
#define regSHUB_DEV0_PF0_VF_FLR_RST_BASE_IDX 3
#define regSHUB_DEV0_PF1_VF_FLR_RST 0x4f7809
#define regSHUB_DEV0_PF1_VF_FLR_RST_BASE_IDX 3
#define regSHUB_HARD_RST_CTRL 0x4f7810
#define regSHUB_HARD_RST_CTRL_BASE_IDX 3
#define regSHUB_SOFT_RST_CTRL 0x4f7811
#define regSHUB_SOFT_RST_CTRL_BASE_IDX 3
#define regSHUB_SDP_PORT_RST 0x4f7812
#define regSHUB_SDP_PORT_RST_BASE_IDX 3
#define regSHUB_RST_MISC_TRL 0x4f7813
#define regSHUB_RST_MISC_TRL_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL 0x4f0aeb
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1 0x4f0aec
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL 0x4f0aed
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1 0x4f0aee
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL 0x4f0aef
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1 0x4f0af0
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL 0x4f0af1
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1 0x4f0af2
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL 0x4f0af3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1 0x4f0af4
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL 0x4f0af5
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1 0x4f0af6
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL 0x4f0af7
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1 0x4f0af8
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL 0x4f0af9
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1 0x4f0afa
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL 0x4f0afb
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1 0x4f0afc
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL 0x4f0afd
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1 0x4f0afe
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL 0x4f0aff
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1 0x4f0b00
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL 0x4f0b01
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1 0x4f0b02
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL 0x4f0b03
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1 0x4f0b04
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL 0x4f0b05
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1 0x4f0b06
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL 0x4f0b07
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1 0x4f0b08
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL 0x4f0b09
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1 0x4f0b0a
#define regGDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1_BASE_IDX 3
#define regGDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG 0x4f0b0b
#define regGDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX 3
#define regGDC_S2A1_NBIF_GFX_DOORBELL_STATUS 0x4f0b0c
#define regGDC_S2A1_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 3
#define regGDC_DMA_SION_CRED_RST 0x4f3401
#define regGDC_DMA_SION_CRED_RST_BASE_IDX 3
#define regGDC_HST_SION_PER_SDP_PORT_RST 0x4f3402
#define regGDC_HST_SION_PER_SDP_PORT_RST_BASE_IDX 3
#define regGDC_HST_SION_PER_SDP_CNTL_REG1 0x4f3403
#define regGDC_HST_SION_PER_SDP_CNTL_REG1_BASE_IDX 3
#define regGDC_HST_AXI_STALL_FOR_FLUSH 0x4f3404
#define regGDC_HST_AXI_STALL_FOR_FLUSH_BASE_IDX 3
#define regSYSHUB_SDP_DEBUG_COUNTER_CTRL 0x4f3405
#define regSYSHUB_SDP_DEBUG_COUNTER_CTRL_BASE_IDX 3
#define regNBIF_PWRBRK_IN_PAD_CNTL 0x4f3801
#define regNBIF_PWRBRK_IN_PAD_CNTL_BASE_IDX 3
#define regNBIF_PWRBRK_OUT_PAD_CNTL 0x4f3802
#define regNBIF_PWRBRK_OUT_PAD_CNTL_BASE_IDX 3
#define regSHUB_OOB_CRUSH_DUMP_CTRL 0x4f3803
#define regSHUB_OOB_CRUSH_DUMP_CTRL_BASE_IDX 3
#define regSHUB_MP_ERREVENT_MASK_CTRL 0x4f3804
#define regSHUB_MP_ERREVENT_MASK_CTRL_BASE_IDX 3
#define regSHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL 0x4f3805
#define regSHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL_BASE_IDX 3
#define regSHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL 0x4f3806
#define regSHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V3_AXI 0x4f2883
#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V3_AXI_BASE_IDX 3
#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V3_AXI 0x4f2884
#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V3_AXI_BASE_IDX 3
#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V3_AXI 0x4f2885
#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V3_AXI_BASE_IDX 3
#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0B_AXI 0x4f2886
#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0B_AXI_BASE_IDX 3
#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B_AXI 0x4f2887
#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B_AXI_BASE_IDX 3
#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B_AXI 0x4f2888
#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B_AXI_BASE_IDX 3
#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V4_AXI 0x4f2889
#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V4_AXI_BASE_IDX 3
#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4_AXI 0x4f288a
#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4_AXI_BASE_IDX 3
#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4_AXI 0x4f288b
#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4_AXI_BASE_IDX 3
#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V4B_AXI 0x4f288c
#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V4B_AXI_BASE_IDX 3
#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4B_AXI 0x4f288d
#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4B_AXI_BASE_IDX 3
#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4B_AXI 0x4f288e
#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4B_AXI_BASE_IDX 3
#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V7_AXI 0x4f288f
#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V7_AXI_BASE_IDX 3
#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V7_AXI 0x4f2890
#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V7_AXI_BASE_IDX 3
#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V7_AXI 0x4f2891
#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V7_AXI_BASE_IDX 3
#define regGDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP 0x4f2898
#define regGDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP_BASE_IDX 3
#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP 0x4f2899
#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP_BASE_IDX 3
#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_SHUB_CNDI_ORIG_SDP 0x4f289a
#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_SHUB_CNDI_ORIG_SDP_BASE_IDX 3
#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0B1_AXI 0x4f28a7
#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0B1_AXI_BASE_IDX 3
#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B1_AXI 0x4f28a8
#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B1_AXI_BASE_IDX 3
#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B1_AXI 0x4f28a9
#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B1_AXI_BASE_IDX 3
#define regGDCSOC_SEC_RAS_POISON_DBUG_CTRL 0x4f2c00
#define regGDCSOC_SEC_RAS_POISON_DBUG_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_PARITY_DBUG_CTRL 0x4f2c01
#define regGDCSOC_SEC_RAS_PARITY_DBUG_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL 0x4f2c02
#define regGDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL 0x4f2c03
#define regGDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL 0x4f2c04
#define regGDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_RESPONSE_DROP_CTRL 0x4f2c05
#define regGDCSOC_SEC_RAS_RESPONSE_DROP_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF0_RRESP_POISON_CTRL 0x4f2c06
#define regGDCSOC_SEC_RAS_LEAF0_RRESP_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF0_RUSER_POISON_CTRL 0x4f2c07
#define regGDCSOC_SEC_RAS_LEAF0_RUSER_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF1_RRESP_POISON_CTRL 0x4f2c08
#define regGDCSOC_SEC_RAS_LEAF1_RRESP_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF1_RUSER_POISON_CTRL 0x4f2c09
#define regGDCSOC_SEC_RAS_LEAF1_RUSER_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF2_RRESP_POISON_CTRL 0x4f2c0a
#define regGDCSOC_SEC_RAS_LEAF2_RRESP_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF2_RUSER_POISON_CTRL 0x4f2c0b
#define regGDCSOC_SEC_RAS_LEAF2_RUSER_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF3_RRESP_POISON_CTRL 0x4f2c0c
#define regGDCSOC_SEC_RAS_LEAF3_RRESP_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF3_RUSER_POISON_CTRL 0x4f2c0d
#define regGDCSOC_SEC_RAS_LEAF3_RUSER_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF4_RRESP_POISON_CTRL 0x4f2c0e
#define regGDCSOC_SEC_RAS_LEAF4_RRESP_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF4_RUSER_POISON_CTRL 0x4f2c0f
#define regGDCSOC_SEC_RAS_LEAF4_RUSER_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF5_RRESP_POISON_CTRL 0x4f2c10
#define regGDCSOC_SEC_RAS_LEAF5_RRESP_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF5_RUSER_POISON_CTRL 0x4f2c11
#define regGDCSOC_SEC_RAS_LEAF5_RUSER_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF6_RRESP_POISON_CTRL 0x4f2c12
#define regGDCSOC_SEC_RAS_LEAF6_RRESP_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF6_RUSER_POISON_CTRL 0x4f2c13
#define regGDCSOC_SEC_RAS_LEAF6_RUSER_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF7_RRESP_POISON_CTRL 0x4f2c14
#define regGDCSOC_SEC_RAS_LEAF7_RRESP_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF7_RUSER_POISON_CTRL 0x4f2c15
#define regGDCSOC_SEC_RAS_LEAF7_RUSER_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF8_RRESP_POISON_CTRL 0x4f2c16
#define regGDCSOC_SEC_RAS_LEAF8_RRESP_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF8_RUSER_POISON_CTRL 0x4f2c17
#define regGDCSOC_SEC_RAS_LEAF8_RUSER_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF9_RRESP_POISON_CTRL 0x4f2c18
#define regGDCSOC_SEC_RAS_LEAF9_RRESP_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF9_RUSER_POISON_CTRL 0x4f2c19
#define regGDCSOC_SEC_RAS_LEAF9_RUSER_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF10_RRESP_POISON_CTRL 0x4f2c1a
#define regGDCSOC_SEC_RAS_LEAF10_RRESP_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF10_RUSER_POISON_CTRL 0x4f2c1b
#define regGDCSOC_SEC_RAS_LEAF10_RUSER_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF11_RRESP_POISON_CTRL 0x4f2c1c
#define regGDCSOC_SEC_RAS_LEAF11_RRESP_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF11_RUSER_POISON_CTRL 0x4f2c1d
#define regGDCSOC_SEC_RAS_LEAF11_RUSER_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF12_RRESP_POISON_CTRL 0x4f2c1e
#define regGDCSOC_SEC_RAS_LEAF12_RRESP_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF12_RUSER_POISON_CTRL 0x4f2c1f
#define regGDCSOC_SEC_RAS_LEAF12_RUSER_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF13_RRESP_POISON_CTRL 0x4f2c20
#define regGDCSOC_SEC_RAS_LEAF13_RRESP_POISON_CTRL_BASE_IDX 3
#define regGDCSOC_SEC_RAS_LEAF13_RUSER_POISON_CTRL 0x4f2c21
#define regGDCSOC_SEC_RAS_LEAF13_RUSER_POISON_CTRL_BASE_IDX 3
#define regA2S_CNTL_SW0 0x4f0c40
#define regA2S_CNTL_SW0_BASE_IDX 3
#define regA2S_CNTL_SW1 0x4f0c41
#define regA2S_CNTL_SW1_BASE_IDX 3
#define regA2S_CNTL_SW2 0x4f0c42
#define regA2S_CNTL_SW2_BASE_IDX 3
#define regA2S_CNTL_SW3 0x4f0c43
#define regA2S_CNTL_SW3_BASE_IDX 3
#define regA2S_CNTL_SW4 0x4f0c44
#define regA2S_CNTL_SW4_BASE_IDX 3
#define regA2S_CNTL_SW5 0x4f0c45
#define regA2S_CNTL_SW5_BASE_IDX 3
#define regA2S_CNTL_2_SW0 0x4f0c50
#define regA2S_CNTL_2_SW0_BASE_IDX 3
#define regA2S_CNTL_2_SW1 0x4f0c51
#define regA2S_CNTL_2_SW1_BASE_IDX 3
#define regA2S_CNTL_2_SW2 0x4f0c52
#define regA2S_CNTL_2_SW2_BASE_IDX 3
#define regA2S_CNTL_2_SW3 0x4f0c53
#define regA2S_CNTL_2_SW3_BASE_IDX 3
#define regA2S_CNTL_2_SW4 0x4f0c54
#define regA2S_CNTL_2_SW4_BASE_IDX 3
#define regA2S_CNTL_2_SW5 0x4f0c55
#define regA2S_CNTL_2_SW5_BASE_IDX 3
#define regA2S_WRSIZEFULL_SUPPORT_DISABLE 0x4f0c5c
#define regA2S_WRSIZEFULL_SUPPORT_DISABLE_BASE_IDX 3
#define regROUTING_TABLE_CNTL 0x4f0c60
#define regROUTING_TABLE_CNTL_BASE_IDX 3
#define regROUTING_TABLE_DATA0 0x4f0c61
#define regROUTING_TABLE_DATA0_BASE_IDX 3
#define regA2S_ARB_CONTROL_FOR_VC0 0x4f0c68
#define regA2S_ARB_CONTROL_FOR_VC0_BASE_IDX 3
#define regA2S_ARB_CONTROL_FOR_VC1 0x4f0c69
#define regA2S_ARB_CONTROL_FOR_VC1_BASE_IDX 3
#define regA2S_ARB_CONTROL_FOR_VC2 0x4f0c6a
#define regA2S_ARB_CONTROL_FOR_VC2_BASE_IDX 3
#define regA2S_ARB_CONTROL_FOR_VC3 0x4f0c6b
#define regA2S_ARB_CONTROL_FOR_VC3_BASE_IDX 3
#define regA2S_ARB_CONTROL_FOR_VC4 0x4f0c6c
#define regA2S_ARB_CONTROL_FOR_VC4_BASE_IDX 3
#define regA2S_ARB_CONTROL_FOR_VC5 0x4f0c6d
#define regA2S_ARB_CONTROL_FOR_VC5_BASE_IDX 3
#define regA2S_ARB_CONTROL_FOR_VC6 0x4f0c6e
#define regA2S_ARB_CONTROL_FOR_VC6_BASE_IDX 3
#define regA2S_ARB_CONTROL_FOR_VC7 0x4f0c6f
#define regA2S_ARB_CONTROL_FOR_VC7_BASE_IDX 3
#define regA2S_RW_ARB_CNTL 0x4f0c70
#define regA2S_RW_ARB_CNTL_BASE_IDX 3
#define regA2S_REQ_RSP_TAG_CNTL 0x4f0c71
#define regA2S_REQ_RSP_TAG_CNTL_BASE_IDX 3
#define regA2S_MISC_CNTL 0x4f0c72
#define regA2S_MISC_CNTL_BASE_IDX 3
#define regA2S_TAG_ALLOC_0 0x4f0c74
#define regA2S_TAG_ALLOC_0_BASE_IDX 3
#define regA2S_TAG_ALLOC_1 0x4f0c75
#define regA2S_TAG_ALLOC_1_BASE_IDX 3
#define regA2S_TAG_ALLOC_2 0x4f0c76
#define regA2S_TAG_ALLOC_2_BASE_IDX 3
#define regA2S_TAG_ALLOC_3 0x4f0c77
#define regA2S_TAG_ALLOC_3_BASE_IDX 3
#define regSHUB_A2S_TAG_ALLOC_FOR_CHAIN_0 0x4f0c78
#define regSHUB_A2S_TAG_ALLOC_FOR_CHAIN_0_BASE_IDX 3
#define regSHUB_A2S_TAG_ALLOC_FOR_CHAIN_1 0x4f0c79
#define regSHUB_A2S_TAG_ALLOC_FOR_CHAIN_1_BASE_IDX 3
#define regGDC_SDP_PORT_CTRL 0x4f0c7c
#define regGDC_SDP_PORT_CTRL_BASE_IDX 3
#define regGDC_A2S_SDP_REQ_POOLCRED_ALLOC 0x4f0c7d
#define regGDC_A2S_SDP_REQ_POOLCRED_ALLOC_BASE_IDX 3
#define regGDC_A2S_SDP_DAT_POOLCRED_ALLOC 0x4f0c7e
#define regGDC_A2S_SDP_DAT_POOLCRED_ALLOC_BASE_IDX 3
#define regSHUB_PERF_COMMON_COUNTER 0x4f0c80
#define regSHUB_PERF_COMMON_COUNTER_BASE_IDX 3
#define regSHUB_A2S_PERF_CNT_FSM 0x4f0c81
#define regSHUB_A2S_PERF_CNT_FSM_BASE_IDX 3
#define regSHUB_A2S_PERF_CNT_RSP_UNITID 0x4f0c83
#define regSHUB_A2S_PERF_CNT_RSP_UNITID_BASE_IDX 3
#define regSHUB_A2S_PERF_CNT_0_CTRL 0x4f0c84
#define regSHUB_A2S_PERF_CNT_0_CTRL_BASE_IDX 3
#define regSHUB_A2S_PERF_CNT_1_CTRL 0x4f0c85
#define regSHUB_A2S_PERF_CNT_1_CTRL_BASE_IDX 3
#define regSHUB_A2S_PERF_CNT_2_CTRL 0x4f0c86
#define regSHUB_A2S_PERF_CNT_2_CTRL_BASE_IDX 3
#define regSHUB_A2S_PERF_CNT_3_CTRL 0x4f0c87
#define regSHUB_A2S_PERF_CNT_3_CTRL_BASE_IDX 3
#define regSHUB_A2S_PERF_CNT_0_VALUE_L32BIT 0x4f0c88
#define regSHUB_A2S_PERF_CNT_0_VALUE_L32BIT_BASE_IDX 3
#define regSHUB_A2S_PERF_CNT_0_VALUE_H16BIT 0x4f0c89
#define regSHUB_A2S_PERF_CNT_0_VALUE_H16BIT_BASE_IDX 3
#define regSHUB_A2S_PERF_CNT_1_VALUE_L32BIT 0x4f0c8a
#define regSHUB_A2S_PERF_CNT_1_VALUE_L32BIT_BASE_IDX 3
#define regSHUB_A2S_PERF_CNT_1_VALUE_H16BIT 0x4f0c8b
#define regSHUB_A2S_PERF_CNT_1_VALUE_H16BIT_BASE_IDX 3
#define regSHUB_A2S_PERF_CNT_2_VALUE_L32BIT 0x4f0c8c
#define regSHUB_A2S_PERF_CNT_2_VALUE_L32BIT_BASE_IDX 3
#define regSHUB_A2S_PERF_CNT_2_VALUE_H16BIT 0x4f0c8d
#define regSHUB_A2S_PERF_CNT_2_VALUE_H16BIT_BASE_IDX 3
#define regSHUB_A2S_PERF_CNT_3_VALUE_L32BIT 0x4f0c8e
#define regSHUB_A2S_PERF_CNT_3_VALUE_L32BIT_BASE_IDX 3
#define regSHUB_A2S_PERF_CNT_3_VALUE_H16BIT 0x4f0c8f
#define regSHUB_A2S_PERF_CNT_3_VALUE_H16BIT_BASE_IDX 3
#define regSHUB_TO_ALL_PERF_COUNTER 0x4f0c90
#define regSHUB_TO_ALL_PERF_COUNTER_BASE_IDX 3
#define regGDC_PERF_COUNTER_RESET 0x4f0c91
#define regGDC_PERF_COUNTER_RESET_BASE_IDX 3
#define regSHUB_COM_COUNT_VALUE 0x4f0c92
#define regSHUB_COM_COUNT_VALUE_BASE_IDX 3
#define regA2S_QUEUE_FIFO_ARB_CNTL 0x4f0c93
#define regA2S_QUEUE_FIFO_ARB_CNTL_BASE_IDX 3
#define regWR_A2S_RSP_WRR_CNTL 0x4f0c94
#define regWR_A2S_RSP_WRR_CNTL_BASE_IDX 3
#define regRD_A2S_RSP_WRR_CNTL 0x4f0c95
#define regRD_A2S_RSP_WRR_CNTL_BASE_IDX 3
#define regSYSHUB_DS_CTRL_SOCCLK 0x4f3c00
#define regSYSHUB_DS_CTRL_SOCCLK_BASE_IDX 3
#define regSYSHUB_DS_CTRL2_SOCCLK 0x4f3c01
#define regSYSHUB_DS_CTRL2_SOCCLK_BASE_IDX 3
#define regSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x4f3c02
#define regSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_BASE_IDX 3
#define regSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x4f3c03
#define regSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_BASE_IDX 3
#define regSYSHUB_MGCG_CTRL_SOCCLK 0x4f3c08
#define regSYSHUB_MGCG_CTRL_SOCCLK_BASE_IDX 3
#define regSYSHUB_SCRATCH_SOCCLK 0x4f3c0a
#define regSYSHUB_SCRATCH_SOCCLK_BASE_IDX 3
#define regSYSHUB_HANG_CNTL_SOCCLK 0x4f3c0c
#define regSYSHUB_HANG_CNTL_SOCCLK_BASE_IDX 3
#define regSYSHUB_SELECT_SOCCLK 0x4f3c0d
#define regSYSHUB_SELECT_SOCCLK_BASE_IDX 3
#define regSYSHUB_DS_AW_READY_SOCCLK 0x4f3c11
#define regSYSHUB_DS_AW_READY_SOCCLK_BASE_IDX 3
#define regSYSHUB_DS_AR_READY_SOCCLK 0x4f3c12
#define regSYSHUB_DS_AR_READY_SOCCLK_BASE_IDX 3
#define regSYSHUB_DS_W_READY_SOCCLK 0x4f3c13
#define regSYSHUB_DS_W_READY_SOCCLK_BASE_IDX 3
#define regSYSHUB_DS_R_READY_SOCCLK 0x4f3c14
#define regSYSHUB_DS_R_READY_SOCCLK_BASE_IDX 3
#define regSYSHUB_DS_B_READY_SOCCLK 0x4f3c15
#define regSYSHUB_DS_B_READY_SOCCLK_BASE_IDX 3
#define regSYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK 0x4f3c16
#define regSYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK_BASE_IDX 3
#define regDMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x4f3e00
#define regDMA_CLK0_SW0_SYSHUB_QOS_CNTL_BASE_IDX 3
#define regDMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x4f3e01
#define regDMA_CLK0_SW1_SYSHUB_QOS_CNTL_BASE_IDX 3
#define regDMA_CLK0_SW0_CL0_CNTL 0x4f3e40
#define regDMA_CLK0_SW0_CL0_CNTL_BASE_IDX 3
#define regDMA_CLK0_SW0_CL1_CNTL 0x4f3e41
#define regDMA_CLK0_SW0_CL1_CNTL_BASE_IDX 3
#define regDMA_CLK0_SW1_CL0_CNTL 0x4f3e60
#define regDMA_CLK0_SW1_CL0_CNTL_BASE_IDX 3
#define regDMA_CLK0_SW1_CL1_CNTL 0x4f3e61
#define regDMA_CLK0_SW1_CL1_CNTL_BASE_IDX 3
#define regDMA_CLK0_SW2_CL0_CNTL 0x4f3e80
#define regDMA_CLK0_SW2_CL0_CNTL_BASE_IDX 3
#define regDMA_CLK0_SW3_CL0_CNTL 0x4f3ea0
#define regDMA_CLK0_SW3_CL0_CNTL_BASE_IDX 3
#define regDMA_CLK0_SW4_CL0_CNTL 0x4f3ec0
#define regDMA_CLK0_SW4_CL0_CNTL_BASE_IDX 3
#define regDMA_CLK0_SW5_CL0_CNTL 0x4f3ee0
#define regDMA_CLK0_SW5_CL0_CNTL_BASE_IDX 3
#define regNIC400_0_AMIB_0_FN_MOD_BM_ISS 0x4f7c02
#define regNIC400_0_AMIB_0_FN_MOD_BM_ISS_BASE_IDX 3
#define regNIC400_0_AMIB_0_FN_MOD 0x4f7c42
#define regNIC400_0_AMIB_0_FN_MOD_BASE_IDX 3
#define regNIC400_0_ASIB_0_FN_MOD 0x4f8842
#define regNIC400_0_ASIB_0_FN_MOD_BASE_IDX 3
#define regNIC400_0_ASIB_0_QOS_CNTL 0x4f8843
#define regNIC400_0_ASIB_0_QOS_CNTL_BASE_IDX 3
#define regNIC400_0_ASIB_0_MAX_OT 0x4f8844
#define regNIC400_0_ASIB_0_MAX_OT_BASE_IDX 3
#define regNIC400_0_ASIB_0_MAX_COMB_OT 0x4f8845
#define regNIC400_0_ASIB_0_MAX_COMB_OT_BASE_IDX 3
#define regNIC400_0_ASIB_0_AW_P 0x4f8846
#define regNIC400_0_ASIB_0_AW_P_BASE_IDX 3
#define regNIC400_0_ASIB_0_AW_B 0x4f8847
#define regNIC400_0_ASIB_0_AW_B_BASE_IDX 3
#define regNIC400_0_ASIB_0_AW_R 0x4f8848
#define regNIC400_0_ASIB_0_AW_R_BASE_IDX 3
#define regNIC400_0_ASIB_0_AR_P 0x4f8849
#define regNIC400_0_ASIB_0_AR_P_BASE_IDX 3
#define regNIC400_0_ASIB_0_AR_B 0x4f884a
#define regNIC400_0_ASIB_0_AR_B_BASE_IDX 3
#define regNIC400_0_ASIB_0_AR_R 0x4f884b
#define regNIC400_0_ASIB_0_AR_R_BASE_IDX 3
#define regNIC400_0_ASIB_0_TARGET_FC 0x4f884c
#define regNIC400_0_ASIB_0_TARGET_FC_BASE_IDX 3
#define regNIC400_0_ASIB_0_KI_FC 0x4f884d
#define regNIC400_0_ASIB_0_KI_FC_BASE_IDX 3
#define regNIC400_0_ASIB_0_QOS_RANGE 0x4f884e
#define regNIC400_0_ASIB_0_QOS_RANGE_BASE_IDX 3
#define regNIC400_0_ASIB_1_FN_MOD 0x4f8c42
#define regNIC400_0_ASIB_1_FN_MOD_BASE_IDX 3
#define regNIC400_0_ASIB_1_QOS_CNTL 0x4f8c43
#define regNIC400_0_ASIB_1_QOS_CNTL_BASE_IDX 3
#define regNIC400_0_ASIB_1_MAX_OT 0x4f8c44
#define regNIC400_0_ASIB_1_MAX_OT_BASE_IDX 3
#define regNIC400_0_ASIB_1_MAX_COMB_OT 0x4f8c45
#define regNIC400_0_ASIB_1_MAX_COMB_OT_BASE_IDX 3
#define regNIC400_0_ASIB_1_AW_P 0x4f8c46
#define regNIC400_0_ASIB_1_AW_P_BASE_IDX 3
#define regNIC400_0_ASIB_1_AW_B 0x4f8c47
#define regNIC400_0_ASIB_1_AW_B_BASE_IDX 3
#define regNIC400_0_ASIB_1_AW_R 0x4f8c48
#define regNIC400_0_ASIB_1_AW_R_BASE_IDX 3
#define regNIC400_0_ASIB_1_AR_P 0x4f8c49
#define regNIC400_0_ASIB_1_AR_P_BASE_IDX 3
#define regNIC400_0_ASIB_1_AR_B 0x4f8c4a
#define regNIC400_0_ASIB_1_AR_B_BASE_IDX 3
#define regNIC400_0_ASIB_1_AR_R 0x4f8c4b
#define regNIC400_0_ASIB_1_AR_R_BASE_IDX 3
#define regNIC400_0_ASIB_1_TARGET_FC 0x4f8c4c
#define regNIC400_0_ASIB_1_TARGET_FC_BASE_IDX 3
#define regNIC400_0_ASIB_1_KI_FC 0x4f8c4d
#define regNIC400_0_ASIB_1_KI_FC_BASE_IDX 3
#define regNIC400_0_ASIB_1_QOS_RANGE 0x4f8c4e
#define regNIC400_0_ASIB_1_QOS_RANGE_BASE_IDX 3
#define regNIC400_0_IB_0_FN_MOD 0x4fb842
#define regNIC400_0_IB_0_FN_MOD_BASE_IDX 3
#define regNIC400_1_AMIB_0_FN_MOD_BM_ISS 0x4fbc02
#define regNIC400_1_AMIB_0_FN_MOD_BM_ISS_BASE_IDX 3
#define regNIC400_1_AMIB_0_FN_MOD 0x4fbc42
#define regNIC400_1_AMIB_0_FN_MOD_BASE_IDX 3
#define regNIC400_1_ASIB_0_FN_MOD 0x4fc842
#define regNIC400_1_ASIB_0_FN_MOD_BASE_IDX 3
#define regNIC400_1_ASIB_0_QOS_CNTL 0x4fc843
#define regNIC400_1_ASIB_0_QOS_CNTL_BASE_IDX 3
#define regNIC400_1_ASIB_0_MAX_OT 0x4fc844
#define regNIC400_1_ASIB_0_MAX_OT_BASE_IDX 3
#define regNIC400_1_ASIB_0_MAX_COMB_OT 0x4fc845
#define regNIC400_1_ASIB_0_MAX_COMB_OT_BASE_IDX 3
#define regNIC400_1_ASIB_0_AW_P 0x4fc846
#define regNIC400_1_ASIB_0_AW_P_BASE_IDX 3
#define regNIC400_1_ASIB_0_AW_B 0x4fc847
#define regNIC400_1_ASIB_0_AW_B_BASE_IDX 3
#define regNIC400_1_ASIB_0_AW_R 0x4fc848
#define regNIC400_1_ASIB_0_AW_R_BASE_IDX 3
#define regNIC400_1_ASIB_0_AR_P 0x4fc849
#define regNIC400_1_ASIB_0_AR_P_BASE_IDX 3
#define regNIC400_1_ASIB_0_AR_B 0x4fc84a
#define regNIC400_1_ASIB_0_AR_B_BASE_IDX 3
#define regNIC400_1_ASIB_0_AR_R 0x4fc84b
#define regNIC400_1_ASIB_0_AR_R_BASE_IDX 3
#define regNIC400_1_ASIB_0_TARGET_FC 0x4fc84c
#define regNIC400_1_ASIB_0_TARGET_FC_BASE_IDX 3
#define regNIC400_1_ASIB_0_KI_FC 0x4fc84d
#define regNIC400_1_ASIB_0_KI_FC_BASE_IDX 3
#define regNIC400_1_ASIB_0_QOS_RANGE 0x4fc84e
#define regNIC400_1_ASIB_0_QOS_RANGE_BASE_IDX 3
#define regNIC400_1_ASIB_1_FN_MOD 0x4fcc42
#define regNIC400_1_ASIB_1_FN_MOD_BASE_IDX 3
#define regNIC400_1_ASIB_1_QOS_CNTL 0x4fcc43
#define regNIC400_1_ASIB_1_QOS_CNTL_BASE_IDX 3
#define regNIC400_1_ASIB_1_MAX_OT 0x4fcc44
#define regNIC400_1_ASIB_1_MAX_OT_BASE_IDX 3
#define regNIC400_1_ASIB_1_MAX_COMB_OT 0x4fcc45
#define regNIC400_1_ASIB_1_MAX_COMB_OT_BASE_IDX 3
#define regNIC400_1_ASIB_1_AW_P 0x4fcc46
#define regNIC400_1_ASIB_1_AW_P_BASE_IDX 3
#define regNIC400_1_ASIB_1_AW_B 0x4fcc47
#define regNIC400_1_ASIB_1_AW_B_BASE_IDX 3
#define regNIC400_1_ASIB_1_AW_R 0x4fcc48
#define regNIC400_1_ASIB_1_AW_R_BASE_IDX 3
#define regNIC400_1_ASIB_1_AR_P 0x4fcc49
#define regNIC400_1_ASIB_1_AR_P_BASE_IDX 3
#define regNIC400_1_ASIB_1_AR_B 0x4fcc4a
#define regNIC400_1_ASIB_1_AR_B_BASE_IDX 3
#define regNIC400_1_ASIB_1_AR_R 0x4fcc4b
#define regNIC400_1_ASIB_1_AR_R_BASE_IDX 3
#define regNIC400_1_ASIB_1_TARGET_FC 0x4fcc4c
#define regNIC400_1_ASIB_1_TARGET_FC_BASE_IDX 3
#define regNIC400_1_ASIB_1_KI_FC 0x4fcc4d
#define regNIC400_1_ASIB_1_KI_FC_BASE_IDX 3
#define regNIC400_1_ASIB_1_QOS_RANGE 0x4fcc4e
#define regNIC400_1_ASIB_1_QOS_RANGE_BASE_IDX 3
#define regNIC400_1_IB_0_FN_MOD 0x4ff842
#define regNIC400_1_IB_0_FN_MOD_BASE_IDX 3
#define regSYSHUB_INDEX 0x0008
#define regSYSHUB_INDEX_BASE_IDX 0
#define regSYSHUB_DATA 0x0009
#define regSYSHUB_DATA_BASE_IDX 0
#define cfgBIF_CFG_DEV0_RC_VENDOR_ID 0x0000
#define cfgBIF_CFG_DEV0_RC_DEVICE_ID 0x0002
#define cfgBIF_CFG_DEV0_RC_COMMAND 0x0004
#define cfgBIF_CFG_DEV0_RC_STATUS 0x0006
#define cfgBIF_CFG_DEV0_RC_REVISION_ID 0x0008
#define cfgBIF_CFG_DEV0_RC_PROG_INTERFACE 0x0009
#define cfgBIF_CFG_DEV0_RC_SUB_CLASS 0x000a
#define cfgBIF_CFG_DEV0_RC_BASE_CLASS 0x000b
#define cfgBIF_CFG_DEV0_RC_CACHE_LINE 0x000c
#define cfgBIF_CFG_DEV0_RC_LATENCY 0x000d
#define cfgBIF_CFG_DEV0_RC_HEADER 0x000e
#define cfgBIF_CFG_DEV0_RC_BIST 0x000f
#define cfgBIF_CFG_DEV0_RC_BASE_ADDR_1 0x0010
#define cfgBIF_CFG_DEV0_RC_BASE_ADDR_2 0x0014
#define cfgSUB_BUS_NUMBER_LATENCY 0x0018
#define cfgIO_BASE_LIMIT 0x001c
#define cfgSECONDARY_STATUS 0x001e
#define cfgMEM_BASE_LIMIT 0x0020
#define cfgPREF_BASE_LIMIT 0x0024
#define cfgPREF_BASE_UPPER 0x0028
#define cfgPREF_LIMIT_UPPER 0x002c
#define cfgIO_BASE_LIMIT_HI 0x0030
#define cfgBIF_CFG_DEV0_RC_CAP_PTR 0x0034
#define cfgBIF_CFG_DEV0_RC_ROM_BASE_ADDR 0x0038
#define cfgBIF_CFG_DEV0_RC_INTERRUPT_LINE 0x003c
#define cfgBIF_CFG_DEV0_RC_INTERRUPT_PIN 0x003d
#define cfgIRQ_BRIDGE_CNTL 0x003e
#define cfgEXT_BRIDGE_CNTL 0x0040
#define cfgBIF_CFG_DEV0_RC_PMI_CAP_LIST 0x0050
#define cfgBIF_CFG_DEV0_RC_PMI_CAP 0x0052
#define cfgBIF_CFG_DEV0_RC_PMI_STATUS_CNTL 0x0054
#define cfgBIF_CFG_DEV0_RC_PCIE_CAP_LIST 0x0058
#define cfgBIF_CFG_DEV0_RC_PCIE_CAP 0x005a
#define cfgBIF_CFG_DEV0_RC_DEVICE_CAP 0x005c
#define cfgBIF_CFG_DEV0_RC_DEVICE_CNTL 0x0060
#define cfgBIF_CFG_DEV0_RC_DEVICE_STATUS 0x0062
#define cfgBIF_CFG_DEV0_RC_LINK_CAP 0x0064
#define cfgBIF_CFG_DEV0_RC_LINK_CNTL 0x0068
#define cfgBIF_CFG_DEV0_RC_LINK_STATUS 0x006a
#define cfgSLOT_CAP 0x006c
#define cfgSLOT_CNTL 0x0070
#define cfgSLOT_STATUS 0x0072
#define cfgROOT_CNTL 0x0074
#define cfgROOT_CAP 0x0076
#define cfgROOT_STATUS 0x0078
#define cfgBIF_CFG_DEV0_RC_DEVICE_CAP2 0x007c
#define cfgBIF_CFG_DEV0_RC_DEVICE_CNTL2 0x0080
#define cfgBIF_CFG_DEV0_RC_DEVICE_STATUS2 0x0082
#define cfgBIF_CFG_DEV0_RC_LINK_CAP2 0x0084
#define cfgBIF_CFG_DEV0_RC_LINK_CNTL2 0x0088
#define cfgBIF_CFG_DEV0_RC_LINK_STATUS2 0x008a
#define cfgSLOT_CAP2 0x008c
#define cfgSLOT_CNTL2 0x0090
#define cfgSLOT_STATUS2 0x0092
#define cfgBIF_CFG_DEV0_RC_MSI_CAP_LIST 0x00a0
#define cfgBIF_CFG_DEV0_RC_MSI_MSG_CNTL 0x00a2
#define cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO 0x00a4
#define cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI 0x00a8
#define cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA 0x00a8
#define cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA 0x00aa
#define cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA_64 0x00ac
#define cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64 0x00ae
#define cfgSSID_CAP_LIST 0x00c0
#define cfgSSID_CAP 0x00c4
#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR 0x0104
#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1 0x0108
#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2 0x010c
#define cfgBIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST 0x0110
#define cfgBIF_CFG_DEV0_RC_PCIE_LINK_CNTL3 0x0114
#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS 0x0118
#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL 0x011c
#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL 0x011e
#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL 0x0120
#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL 0x0122
#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL 0x0124
#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL 0x0126
#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL 0x0128
#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL 0x012a
#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL 0x012c
#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL 0x012e
#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL 0x0130
#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL 0x0132
#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL 0x0134
#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL 0x0136
#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL 0x0138
#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL 0x013a
#define cfgBIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST 0x01b8
#define cfgBIF_CFG_DEV0_RC_LINK_CAP_16GT 0x01bc
#define cfgBIF_CFG_DEV0_RC_LINK_CNTL_16GT 0x01c0
#define cfgBIF_CFG_DEV0_RC_LINK_STATUS_16GT 0x01c4
#define cfgBIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x01c8
#define cfgBIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT 0x01cc
#define cfgBIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT 0x01d0
#define cfgBIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT 0x01d8
#define cfgBIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT 0x01d9
#define cfgBIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT 0x01da
#define cfgBIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT 0x01db
#define cfgBIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT 0x01dc
#define cfgBIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT 0x01dd
#define cfgBIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT 0x01de
#define cfgBIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT 0x01df
#define cfgBIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT 0x01e0
#define cfgBIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT 0x01e1
#define cfgBIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT 0x01e2
#define cfgBIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT 0x01e3
#define cfgBIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT 0x01e4
#define cfgBIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT 0x01e5
#define cfgBIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT 0x01e6
#define cfgBIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT 0x01e7
#define cfgBIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST 0x01f8
#define cfgBIF_CFG_DEV0_RC_LINK_CAP_32GT 0x01fc
#define cfgBIF_CFG_DEV0_RC_LINK_CNTL_32GT 0x0200
#define cfgBIF_CFG_DEV0_RC_LINK_STATUS_32GT 0x0204
#define cfgBIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1 0x0208
#define cfgBIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA2 0x020c
#define cfgBIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1 0x0210
#define cfgBIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA2 0x0214
#define cfgBIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_32GT 0x0218
#define cfgBIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_32GT 0x0219
#define cfgBIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_32GT 0x021a
#define cfgBIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_32GT 0x021b
#define cfgBIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_32GT 0x021c
#define cfgBIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_32GT 0x021d
#define cfgBIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_32GT 0x021e
#define cfgBIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_32GT 0x021f
#define cfgBIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_32GT 0x0220
#define cfgBIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_32GT 0x0221
#define cfgBIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_32GT 0x0222
#define cfgBIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_32GT 0x0223
#define cfgBIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_32GT 0x0224
#define cfgBIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_32GT 0x0225
#define cfgBIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_32GT 0x0226
#define cfgBIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_32GT 0x0227
#define cfgBIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST 0x0238
#define cfgBIF_CFG_DEV0_RC_AP_CAP 0x023c
#define cfgBIF_CFG_DEV0_RC_AP_CNTL 0x0240
#define cfgBIF_CFG_DEV0_RC_AP_DATA1 0x0244
#define cfgBIF_CFG_DEV0_RC_AP_DATA2 0x0248
#define cfgBIF_CFG_DEV0_RC_AP_SEL_EN_MASK 0x024c
#define cfgBIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST 0x0250
#define cfgBIF_CFG_DEV0_RC_MARGINING_PORT_CAP 0x0254
#define cfgBIF_CFG_DEV0_RC_MARGINING_PORT_STATUS 0x0256
#define cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL 0x0258
#define cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS 0x025a
#define cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL 0x025c
#define cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS 0x025e
#define cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL 0x0260
#define cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS 0x0262
#define cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL 0x0264
#define cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS 0x0266
#define cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL 0x0268
#define cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS 0x026a
#define cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL 0x026c
#define cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS 0x026e
#define cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL 0x0270
#define cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS 0x0272
#define cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL 0x0274
#define cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS 0x0276
#define cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL 0x0278
#define cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS 0x027a
#define cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL 0x027c
#define cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS 0x027e
#define cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL 0x0280
#define cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS 0x0282
#define cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL 0x0284
#define cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS 0x0286
#define cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL 0x0288
#define cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS 0x028a
#define cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL 0x028c
#define cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS 0x028e
#define cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL 0x0290
#define cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS 0x0292
#define cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL 0x0294
#define cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS 0x0296
#define cfgBIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST 0x0400
#define cfgBIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST 0x0404
#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1 0x0408
#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2 0x040c
#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL 0x0410
#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS 0x0412
#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP 0x0414
#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL 0x0418
#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS 0x041e
#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP 0x0420
#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL 0x0424
#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS 0x042a
#define cfgBIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST 0x0430
#define cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP 0x0434
#define cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS 0x0438
#define cfgBIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST 0x0600
#define cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604
#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS 0x0608
#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK 0x060c
#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY 0x0610
#define cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS 0x0614
#define cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK 0x0618
#define cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL 0x061c
#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG0 0x0620
#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG1 0x0624
#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG2 0x0628
#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG3 0x062c
#define cfgPCIE_ROOT_ERR_CMD 0x0630
#define cfgPCIE_ROOT_ERR_STATUS 0x0634
#define cfgPCIE_ERR_SRC_ID 0x0638
#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG4 0x063c
#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0 0x063c
#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG5 0x0640
#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1 0x0640
#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG6 0x0644
#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2 0x0644
#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG7 0x0648
#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3 0x0648
#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG8 0x064c
#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG9 0x0650
#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG10 0x0654
#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG11 0x0658
#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG12 0x065c
#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG13 0x0660
#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0664
#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1 0x0668
#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2 0x066c
#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST 0x06dc
#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_CAP 0x06e0
#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_CNTL 0x06e2
#define cfgBIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST 0x071c
#define cfgBIF_CFG_DEV0_RC_RTR_DATA1 0x0720
#define cfgBIF_CFG_DEV0_RC_RTR_DATA2 0x0724
#define cfgBIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST 0x0e00
#define cfgBIF_CFG_DEV0_RC_IDE_CAP 0x0e04
#define cfgBIF_CFG_DEV0_RC_IDE_CNTL 0x0e08
#define cfgBIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL 0x0e0c
#define cfgBIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_STATUS 0x0e10
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CAP 0x0e14
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL 0x0e18
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_STATUS 0x0e1c
#define cfgBIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG1 0x0e20
#define cfgBIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2 0x0e24
#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1 0x0e28
#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG2 0x0e2c
#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG3 0x0e30
#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1 0x0e34
#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG2 0x0e38
#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG3 0x0e3c
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CAP 0x0e40
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL 0x0e44
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_STATUS 0x0e48
#define cfgBIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG1 0x0e4c
#define cfgBIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2 0x0e50
#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1 0x0e54
#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG2 0x0e58
#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG3 0x0e5c
#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1 0x0e60
#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG2 0x0e64
#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG3 0x0e68
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CAP 0x0e6c
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL 0x0e70
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_STATUS 0x0e74
#define cfgBIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG1 0x0e78
#define cfgBIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2 0x0e7c
#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1 0x0e80
#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG2 0x0e84
#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG3 0x0e88
#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1 0x0e8c
#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG2 0x0e90
#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG3 0x0e94
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CAP 0x0e98
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL 0x0e9c
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_STATUS 0x0ea0
#define cfgBIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG1 0x0ea4
#define cfgBIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2 0x0ea8
#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1 0x0eac
#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG2 0x0eb0
#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG3 0x0eb4
#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1 0x0eb8
#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG2 0x0ebc
#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG3 0x0ec0
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CAP 0x0ec4
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL 0x0ec8
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_STATUS 0x0ecc
#define cfgBIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG1 0x0ed0
#define cfgBIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2 0x0ed4
#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1 0x0ed8
#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG2 0x0edc
#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG3 0x0ee0
#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1 0x0ee4
#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG2 0x0ee8
#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG3 0x0eec
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CAP 0x0ef0
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL 0x0ef4
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_STATUS 0x0ef8
#define cfgBIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG1 0x0efc
#define cfgBIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2 0x0f00
#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1 0x0f04
#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG2 0x0f08
#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG3 0x0f0c
#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1 0x0f10
#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG2 0x0f14
#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG3 0x0f18
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CAP 0x0f1c
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL 0x0f20
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_STATUS 0x0f24
#define cfgBIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG1 0x0f28
#define cfgBIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2 0x0f2c
#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1 0x0f30
#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG2 0x0f34
#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG3 0x0f38
#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1 0x0f3c
#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG2 0x0f40
#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG3 0x0f44
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CAP 0x0f48
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL 0x0f4c
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_STATUS 0x0f50
#define cfgBIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG1 0x0f54
#define cfgBIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2 0x0f58
#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1 0x0f5c
#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG2 0x0f60
#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG3 0x0f64
#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1 0x0f68
#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG2 0x0f6c
#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG3 0x0f70
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CAP 0x0f74
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL 0x0f78
#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_STATUS 0x0f7c
#define cfgBIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG1 0x0f80
#define cfgBIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2 0x0f84
#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1 0x0f88
#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG2 0x0f8c
#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG3 0x0f90
#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1 0x0f94
#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG2 0x0f98
#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG3 0x0f9c
#define cfgBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID 0x0000
#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID 0x0002
#define cfgBIF_CFG_DEV0_EPF0_VF0_COMMAND 0x0004
#define cfgBIF_CFG_DEV0_EPF0_VF0_STATUS 0x0006
#define cfgBIF_CFG_DEV0_EPF0_VF0_REVISION_ID 0x0008
#define cfgBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE 0x0009
#define cfgBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS 0x000a
#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS 0x000b
#define cfgBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE 0x000c
#define cfgBIF_CFG_DEV0_EPF0_VF0_LATENCY 0x000d
#define cfgBIF_CFG_DEV0_EPF0_VF0_HEADER 0x000e
#define cfgBIF_CFG_DEV0_EPF0_VF0_BIST 0x000f
#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 0x0010
#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 0x0014
#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 0x0018
#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 0x001c
#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 0x0020
#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 0x0024
#define cfgBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR 0x0028
#define cfgBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID 0x002c
#define cfgBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR 0x0030
#define cfgBIF_CFG_DEV0_EPF0_VF0_CAP_PTR 0x0034
#define cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE 0x003c
#define cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN 0x003d
#define cfgBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT 0x003e
#define cfgBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY 0x003f
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST 0x0064
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP 0x0066
#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP 0x0068
#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL 0x006c
#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS 0x006e
#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP 0x0070
#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL 0x0074
#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS 0x0076
#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 0x0088
#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 0x008c
#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 0x008e
#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 0x0090
#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 0x0094
#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 0x0096
#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST 0x00a0
#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL 0x00a2
#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO 0x00a4
#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI 0x00a8
#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA 0x00a8
#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA 0x00aa
#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK 0x00ac
#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 0x00ac
#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 0x00ae
#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 0x00b0
#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING 0x00b0
#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 0x00b4
#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST 0x00c0
#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL 0x00c2
#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE 0x00c4
#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA 0x00c8
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 0x0108
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 0x010c
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8
#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3 0x02dc
#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3 0x02e0
#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3 0x02e4
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST 0x0400
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST 0x0600
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS 0x0608
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK 0x060c
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY 0x0610
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS 0x0614
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK 0x0618
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL 0x061c
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 0x0620
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 0x0624
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 0x0628
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 0x062c
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG4 0x063c
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 0x063c
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG5 0x0640
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 0x0640
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG6 0x0644
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 0x0644
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG7 0x0648
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 0x0648
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG8 0x064c
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG9 0x0650
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG10 0x0654
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG11 0x0658
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG12 0x065c
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG13 0x0660
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST 0x071c
#define cfgBIF_CFG_DEV0_EPF0_VF0_RTR_DATA1 0x0720
#define cfgBIF_CFG_DEV0_EPF0_VF0_RTR_DATA2 0x0724
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST 0x0770
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP 0x0774
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL 0x0776
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST 0x07ac
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP 0x07b0
#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL 0x07b2
#define cfgBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID 0x0000
#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID 0x0002
#define cfgBIF_CFG_DEV0_EPF0_VF1_COMMAND 0x0004
#define cfgBIF_CFG_DEV0_EPF0_VF1_STATUS 0x0006
#define cfgBIF_CFG_DEV0_EPF0_VF1_REVISION_ID 0x0008
#define cfgBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE 0x0009
#define cfgBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS 0x000a
#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS 0x000b
#define cfgBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE 0x000c
#define cfgBIF_CFG_DEV0_EPF0_VF1_LATENCY 0x000d
#define cfgBIF_CFG_DEV0_EPF0_VF1_HEADER 0x000e
#define cfgBIF_CFG_DEV0_EPF0_VF1_BIST 0x000f
#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 0x0010
#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 0x0014
#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 0x0018
#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 0x001c
#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 0x0020
#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 0x0024
#define cfgBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR 0x0028
#define cfgBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID 0x002c
#define cfgBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR 0x0030
#define cfgBIF_CFG_DEV0_EPF0_VF1_CAP_PTR 0x0034
#define cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE 0x003c
#define cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN 0x003d
#define cfgBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT 0x003e
#define cfgBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY 0x003f
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST 0x0064
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP 0x0066
#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP 0x0068
#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL 0x006c
#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS 0x006e
#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP 0x0070
#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL 0x0074
#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS 0x0076
#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 0x0088
#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 0x008c
#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 0x008e
#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 0x0090
#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 0x0094
#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 0x0096
#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST 0x00a0
#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL 0x00a2
#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO 0x00a4
#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI 0x00a8
#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA 0x00a8
#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA 0x00aa
#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK 0x00ac
#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 0x00ac
#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 0x00ae
#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 0x00b0
#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING 0x00b0
#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 0x00b4
#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST 0x00c0
#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL 0x00c2
#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE 0x00c4
#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA 0x00c8
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR 0x0104
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 0x0108
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 0x010c
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8
#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3 0x02dc
#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3 0x02e0
#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3 0x02e4
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST 0x0400
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST 0x0600
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS 0x0608
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK 0x060c
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY 0x0610
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS 0x0614
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK 0x0618
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL 0x061c
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 0x0620
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 0x0624
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 0x0628
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 0x062c
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG4 0x063c
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 0x063c
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG5 0x0640
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 0x0640
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG6 0x0644
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 0x0644
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG7 0x0648
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 0x0648
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG8 0x064c
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG9 0x0650
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG10 0x0654
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG11 0x0658
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG12 0x065c
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG13 0x0660
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST 0x071c
#define cfgBIF_CFG_DEV0_EPF0_VF1_RTR_DATA1 0x0720
#define cfgBIF_CFG_DEV0_EPF0_VF1_RTR_DATA2 0x0724
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST 0x0770
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP 0x0774
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL 0x0776
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST 0x07ac
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP 0x07b0
#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL 0x07b2
#define cfgBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID 0x0000
#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID 0x0002
#define cfgBIF_CFG_DEV0_EPF0_VF2_COMMAND 0x0004
#define cfgBIF_CFG_DEV0_EPF0_VF2_STATUS 0x0006
#define cfgBIF_CFG_DEV0_EPF0_VF2_REVISION_ID 0x0008
#define cfgBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE 0x0009
#define cfgBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS 0x000a
#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS 0x000b
#define cfgBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE 0x000c
#define cfgBIF_CFG_DEV0_EPF0_VF2_LATENCY 0x000d
#define cfgBIF_CFG_DEV0_EPF0_VF2_HEADER 0x000e
#define cfgBIF_CFG_DEV0_EPF0_VF2_BIST 0x000f
#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 0x0010
#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 0x0014
#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 0x0018
#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 0x001c
#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 0x0020
#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 0x0024
#define cfgBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR 0x0028
#define cfgBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID 0x002c
#define cfgBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR 0x0030
#define cfgBIF_CFG_DEV0_EPF0_VF2_CAP_PTR 0x0034
#define cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE 0x003c
#define cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN 0x003d
#define cfgBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT 0x003e
#define cfgBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY 0x003f
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST 0x0064
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP 0x0066
#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP 0x0068
#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL 0x006c
#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS 0x006e
#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP 0x0070
#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL 0x0074
#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS 0x0076
#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 0x0088
#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 0x008c
#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 0x008e
#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 0x0090
#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 0x0094
#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 0x0096
#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST 0x00a0
#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL 0x00a2
#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO 0x00a4
#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI 0x00a8
#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA 0x00a8
#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA 0x00aa
#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK 0x00ac
#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 0x00ac
#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 0x00ae
#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 0x00b0
#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING 0x00b0
#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 0x00b4
#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST 0x00c0
#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL 0x00c2
#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE 0x00c4
#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA 0x00c8
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR 0x0104
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 0x0108
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 0x010c
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8
#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3 0x02dc
#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3 0x02e0
#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3 0x02e4
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST 0x0400
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST 0x0600
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS 0x0608
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK 0x060c
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY 0x0610
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS 0x0614
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK 0x0618
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL 0x061c
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 0x0620
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 0x0624
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 0x0628
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 0x062c
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG4 0x063c
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 0x063c
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG5 0x0640
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 0x0640
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG6 0x0644
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 0x0644
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG7 0x0648
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 0x0648
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG8 0x064c
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG9 0x0650
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG10 0x0654
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG11 0x0658
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG12 0x065c
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG13 0x0660
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST 0x071c
#define cfgBIF_CFG_DEV0_EPF0_VF2_RTR_DATA1 0x0720
#define cfgBIF_CFG_DEV0_EPF0_VF2_RTR_DATA2 0x0724
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST 0x0770
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP 0x0774
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL 0x0776
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST 0x07ac
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP 0x07b0
#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL 0x07b2
#define cfgBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID 0x0000
#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID 0x0002
#define cfgBIF_CFG_DEV0_EPF0_VF3_COMMAND 0x0004
#define cfgBIF_CFG_DEV0_EPF0_VF3_STATUS 0x0006
#define cfgBIF_CFG_DEV0_EPF0_VF3_REVISION_ID 0x0008
#define cfgBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE 0x0009
#define cfgBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS 0x000a
#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS 0x000b
#define cfgBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE 0x000c
#define cfgBIF_CFG_DEV0_EPF0_VF3_LATENCY 0x000d
#define cfgBIF_CFG_DEV0_EPF0_VF3_HEADER 0x000e
#define cfgBIF_CFG_DEV0_EPF0_VF3_BIST 0x000f
#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 0x0010
#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 0x0014
#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 0x0018
#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 0x001c
#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 0x0020
#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 0x0024
#define cfgBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR 0x0028
#define cfgBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID 0x002c
#define cfgBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR 0x0030
#define cfgBIF_CFG_DEV0_EPF0_VF3_CAP_PTR 0x0034
#define cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE 0x003c
#define cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN 0x003d
#define cfgBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT 0x003e
#define cfgBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY 0x003f
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST 0x0064
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP 0x0066
#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP 0x0068
#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL 0x006c
#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS 0x006e
#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP 0x0070
#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL 0x0074
#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS 0x0076
#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 0x0088
#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 0x008c
#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 0x008e
#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 0x0090
#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 0x0094
#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 0x0096
#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST 0x00a0
#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL 0x00a2
#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO 0x00a4
#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI 0x00a8
#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA 0x00a8
#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA 0x00aa
#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK 0x00ac
#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 0x00ac
#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 0x00ae
#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 0x00b0
#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING 0x00b0
#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 0x00b4
#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST 0x00c0
#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL 0x00c2
#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE 0x00c4
#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA 0x00c8
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR 0x0104
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 0x0108
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 0x010c
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8
#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3 0x02dc
#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3 0x02e0
#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3 0x02e4
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST 0x0400
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST 0x0600
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS 0x0608
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK 0x060c
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY 0x0610
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS 0x0614
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK 0x0618
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL 0x061c
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 0x0620
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 0x0624
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 0x0628
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 0x062c
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG4 0x063c
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 0x063c
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG5 0x0640
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 0x0640
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG6 0x0644
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 0x0644
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG7 0x0648
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 0x0648
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG8 0x064c
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG9 0x0650
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG10 0x0654
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG11 0x0658
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG12 0x065c
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG13 0x0660
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST 0x071c
#define cfgBIF_CFG_DEV0_EPF0_VF3_RTR_DATA1 0x0720
#define cfgBIF_CFG_DEV0_EPF0_VF3_RTR_DATA2 0x0724
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST 0x0770
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP 0x0774
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL 0x0776
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST 0x07ac
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP 0x07b0
#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL 0x07b2
#define cfgBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID 0x0000
#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID 0x0002
#define cfgBIF_CFG_DEV0_EPF0_VF4_COMMAND 0x0004
#define cfgBIF_CFG_DEV0_EPF0_VF4_STATUS 0x0006
#define cfgBIF_CFG_DEV0_EPF0_VF4_REVISION_ID 0x0008
#define cfgBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE 0x0009
#define cfgBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS 0x000a
#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS 0x000b
#define cfgBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE 0x000c
#define cfgBIF_CFG_DEV0_EPF0_VF4_LATENCY 0x000d
#define cfgBIF_CFG_DEV0_EPF0_VF4_HEADER 0x000e
#define cfgBIF_CFG_DEV0_EPF0_VF4_BIST 0x000f
#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 0x0010
#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 0x0014
#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 0x0018
#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 0x001c
#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 0x0020
#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 0x0024
#define cfgBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR 0x0028
#define cfgBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID 0x002c
#define cfgBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR 0x0030
#define cfgBIF_CFG_DEV0_EPF0_VF4_CAP_PTR 0x0034
#define cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE 0x003c
#define cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN 0x003d
#define cfgBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT 0x003e
#define cfgBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY 0x003f
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST 0x0064
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP 0x0066
#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP 0x0068
#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL 0x006c
#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS 0x006e
#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP 0x0070
#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL 0x0074
#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS 0x0076
#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 0x0088
#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 0x008c
#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 0x008e
#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 0x0090
#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 0x0094
#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 0x0096
#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST 0x00a0
#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL 0x00a2
#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO 0x00a4
#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI 0x00a8
#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA 0x00a8
#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA 0x00aa
#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK 0x00ac
#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 0x00ac
#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 0x00ae
#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 0x00b0
#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING 0x00b0
#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 0x00b4
#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST 0x00c0
#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL 0x00c2
#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE 0x00c4
#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA 0x00c8
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR 0x0104
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 0x0108
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 0x010c
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8
#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3 0x02dc
#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3 0x02e0
#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3 0x02e4
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST 0x0400
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST 0x0600
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS 0x0608
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK 0x060c
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY 0x0610
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS 0x0614
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK 0x0618
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL 0x061c
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 0x0620
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 0x0624
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 0x0628
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 0x062c
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG4 0x063c
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 0x063c
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG5 0x0640
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 0x0640
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG6 0x0644
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 0x0644
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG7 0x0648
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 0x0648
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG8 0x064c
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG9 0x0650
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG10 0x0654
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG11 0x0658
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG12 0x065c
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG13 0x0660
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST 0x071c
#define cfgBIF_CFG_DEV0_EPF0_VF4_RTR_DATA1 0x0720
#define cfgBIF_CFG_DEV0_EPF0_VF4_RTR_DATA2 0x0724
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST 0x0770
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP 0x0774
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL 0x0776
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST 0x07ac
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP 0x07b0
#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL 0x07b2
#define cfgBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID 0x0000
#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID 0x0002
#define cfgBIF_CFG_DEV0_EPF0_VF5_COMMAND 0x0004
#define cfgBIF_CFG_DEV0_EPF0_VF5_STATUS 0x0006
#define cfgBIF_CFG_DEV0_EPF0_VF5_REVISION_ID 0x0008
#define cfgBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE 0x0009
#define cfgBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS 0x000a
#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS 0x000b
#define cfgBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE 0x000c
#define cfgBIF_CFG_DEV0_EPF0_VF5_LATENCY 0x000d
#define cfgBIF_CFG_DEV0_EPF0_VF5_HEADER 0x000e
#define cfgBIF_CFG_DEV0_EPF0_VF5_BIST 0x000f
#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 0x0010
#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 0x0014
#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 0x0018
#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 0x001c
#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 0x0020
#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 0x0024
#define cfgBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR 0x0028
#define cfgBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID 0x002c
#define cfgBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR 0x0030
#define cfgBIF_CFG_DEV0_EPF0_VF5_CAP_PTR 0x0034
#define cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE 0x003c
#define cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN 0x003d
#define cfgBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT 0x003e
#define cfgBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY 0x003f
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST 0x0064
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP 0x0066
#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP 0x0068
#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL 0x006c
#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS 0x006e
#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP 0x0070
#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL 0x0074
#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS 0x0076
#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 0x0088
#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 0x008c
#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 0x008e
#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 0x0090
#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 0x0094
#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 0x0096
#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST 0x00a0
#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL 0x00a2
#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO 0x00a4
#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI 0x00a8
#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA 0x00a8
#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA 0x00aa
#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK 0x00ac
#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 0x00ac
#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 0x00ae
#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 0x00b0
#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING 0x00b0
#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 0x00b4
#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST 0x00c0
#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL 0x00c2
#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE 0x00c4
#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA 0x00c8
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR 0x0104
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 0x0108
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 0x010c
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8
#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3 0x02dc
#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3 0x02e0
#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3 0x02e4
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST 0x0400
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST 0x0600
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS 0x0608
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK 0x060c
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY 0x0610
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS 0x0614
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK 0x0618
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL 0x061c
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 0x0620
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 0x0624
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 0x0628
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 0x062c
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG4 0x063c
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 0x063c
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG5 0x0640
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 0x0640
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG6 0x0644
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 0x0644
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG7 0x0648
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 0x0648
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG8 0x064c
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG9 0x0650
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG10 0x0654
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG11 0x0658
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG12 0x065c
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG13 0x0660
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST 0x071c
#define cfgBIF_CFG_DEV0_EPF0_VF5_RTR_DATA1 0x0720
#define cfgBIF_CFG_DEV0_EPF0_VF5_RTR_DATA2 0x0724
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST 0x0770
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP 0x0774
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL 0x0776
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST 0x07ac
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP 0x07b0
#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL 0x07b2
#define cfgBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID 0x0000
#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID 0x0002
#define cfgBIF_CFG_DEV0_EPF0_VF6_COMMAND 0x0004
#define cfgBIF_CFG_DEV0_EPF0_VF6_STATUS 0x0006
#define cfgBIF_CFG_DEV0_EPF0_VF6_REVISION_ID 0x0008
#define cfgBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE 0x0009
#define cfgBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS 0x000a
#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS 0x000b
#define cfgBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE 0x000c
#define cfgBIF_CFG_DEV0_EPF0_VF6_LATENCY 0x000d
#define cfgBIF_CFG_DEV0_EPF0_VF6_HEADER 0x000e
#define cfgBIF_CFG_DEV0_EPF0_VF6_BIST 0x000f
#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 0x0010
#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 0x0014
#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 0x0018
#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 0x001c
#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 0x0020
#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 0x0024
#define cfgBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR 0x0028
#define cfgBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID 0x002c
#define cfgBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR 0x0030
#define cfgBIF_CFG_DEV0_EPF0_VF6_CAP_PTR 0x0034
#define cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE 0x003c
#define cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN 0x003d
#define cfgBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT 0x003e
#define cfgBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY 0x003f
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST 0x0064
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP 0x0066
#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP 0x0068
#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL 0x006c
#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS 0x006e
#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP 0x0070
#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL 0x0074
#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS 0x0076
#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 0x0088
#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 0x008c
#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 0x008e
#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 0x0090
#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 0x0094
#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 0x0096
#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST 0x00a0
#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL 0x00a2
#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO 0x00a4
#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI 0x00a8
#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA 0x00a8
#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA 0x00aa
#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK 0x00ac
#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 0x00ac
#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 0x00ae
#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 0x00b0
#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING 0x00b0
#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 0x00b4
#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST 0x00c0
#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL 0x00c2
#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE 0x00c4
#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA 0x00c8
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR 0x0104
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 0x0108
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 0x010c
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8
#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3 0x02dc
#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3 0x02e0
#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3 0x02e4
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST 0x0400
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST 0x0600
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS 0x0608
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK 0x060c
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY 0x0610
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS 0x0614
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK 0x0618
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL 0x061c
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 0x0620
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 0x0624
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 0x0628
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 0x062c
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG4 0x063c
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 0x063c
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG5 0x0640
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 0x0640
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG6 0x0644
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 0x0644
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG7 0x0648
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 0x0648
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG8 0x064c
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG9 0x0650
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG10 0x0654
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG11 0x0658
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG12 0x065c
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG13 0x0660
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST 0x071c
#define cfgBIF_CFG_DEV0_EPF0_VF6_RTR_DATA1 0x0720
#define cfgBIF_CFG_DEV0_EPF0_VF6_RTR_DATA2 0x0724
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST 0x0770
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP 0x0774
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL 0x0776
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST 0x07ac
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP 0x07b0
#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL 0x07b2
#define cfgBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID 0x0000
#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID 0x0002
#define cfgBIF_CFG_DEV0_EPF0_VF7_COMMAND 0x0004
#define cfgBIF_CFG_DEV0_EPF0_VF7_STATUS 0x0006
#define cfgBIF_CFG_DEV0_EPF0_VF7_REVISION_ID 0x0008
#define cfgBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE 0x0009
#define cfgBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS 0x000a
#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS 0x000b
#define cfgBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE 0x000c
#define cfgBIF_CFG_DEV0_EPF0_VF7_LATENCY 0x000d
#define cfgBIF_CFG_DEV0_EPF0_VF7_HEADER 0x000e
#define cfgBIF_CFG_DEV0_EPF0_VF7_BIST 0x000f
#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 0x0010
#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 0x0014
#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 0x0018
#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 0x001c
#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 0x0020
#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 0x0024
#define cfgBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR 0x0028
#define cfgBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID 0x002c
#define cfgBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR 0x0030
#define cfgBIF_CFG_DEV0_EPF0_VF7_CAP_PTR 0x0034
#define cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE 0x003c
#define cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN 0x003d
#define cfgBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT 0x003e
#define cfgBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY 0x003f
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST 0x0064
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP 0x0066
#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP 0x0068
#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL 0x006c
#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS 0x006e
#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP 0x0070
#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL 0x0074
#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS 0x0076
#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 0x0088
#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 0x008c
#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 0x008e
#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 0x0090
#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 0x0094
#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 0x0096
#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST 0x00a0
#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL 0x00a2
#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO 0x00a4
#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI 0x00a8
#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA 0x00a8
#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA 0x00aa
#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK 0x00ac
#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 0x00ac
#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 0x00ae
#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 0x00b0
#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING 0x00b0
#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 0x00b4
#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST 0x00c0
#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL 0x00c2
#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE 0x00c4
#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA 0x00c8
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR 0x0104
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 0x0108
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 0x010c
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8
#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3 0x02dc
#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3 0x02e0
#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3 0x02e4
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST 0x0400
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST 0x0600
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS 0x0608
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK 0x060c
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY 0x0610
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS 0x0614
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK 0x0618
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL 0x061c
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 0x0620
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 0x0624
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 0x0628
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 0x062c
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG4 0x063c
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 0x063c
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG5 0x0640
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 0x0640
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG6 0x0644
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 0x0644
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG7 0x0648
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 0x0648
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG8 0x064c
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG9 0x0650
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG10 0x0654
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG11 0x0658
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG12 0x065c
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG13 0x0660
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST 0x071c
#define cfgBIF_CFG_DEV0_EPF0_VF7_RTR_DATA1 0x0720
#define cfgBIF_CFG_DEV0_EPF0_VF7_RTR_DATA2 0x0724
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST 0x0770
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP 0x0774
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL 0x0776
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST 0x07ac
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP 0x07b0
#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL 0x07b2
#define cfgBIF_CFG_DEV0_EPF1_VF0_VENDOR_ID 0x0000
#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_ID 0x0002
#define cfgBIF_CFG_DEV0_EPF1_VF0_COMMAND 0x0004
#define cfgBIF_CFG_DEV0_EPF1_VF0_STATUS 0x0006
#define cfgBIF_CFG_DEV0_EPF1_VF0_REVISION_ID 0x0008
#define cfgBIF_CFG_DEV0_EPF1_VF0_PROG_INTERFACE 0x0009
#define cfgBIF_CFG_DEV0_EPF1_VF0_SUB_CLASS 0x000a
#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_CLASS 0x000b
#define cfgBIF_CFG_DEV0_EPF1_VF0_CACHE_LINE 0x000c
#define cfgBIF_CFG_DEV0_EPF1_VF0_LATENCY 0x000d
#define cfgBIF_CFG_DEV0_EPF1_VF0_HEADER 0x000e
#define cfgBIF_CFG_DEV0_EPF1_VF0_BIST 0x000f
#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_1 0x0010
#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_2 0x0014
#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_3 0x0018
#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_4 0x001c
#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_5 0x0020
#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_6 0x0024
#define cfgBIF_CFG_DEV0_EPF1_VF0_CARDBUS_CIS_PTR 0x0028
#define cfgBIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID 0x002c
#define cfgBIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR 0x0030
#define cfgBIF_CFG_DEV0_EPF1_VF0_CAP_PTR 0x0034
#define cfgBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_LINE 0x003c
#define cfgBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_PIN 0x003d
#define cfgBIF_CFG_DEV0_EPF1_VF0_MIN_GRANT 0x003e
#define cfgBIF_CFG_DEV0_EPF1_VF0_MAX_LATENCY 0x003f
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST 0x0064
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP 0x0066
#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP 0x0068
#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL 0x006c
#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS 0x006e
#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_CAP 0x0070
#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL 0x0074
#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS 0x0076
#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2 0x0088
#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2 0x008c
#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS2 0x008e
#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_CAP2 0x0090
#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2 0x0094
#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2 0x0096
#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST 0x00a0
#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL 0x00a2
#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_LO 0x00a4
#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_HI 0x00a8
#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA 0x00a8
#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA 0x00aa
#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MASK 0x00ac
#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_64 0x00ac
#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_64 0x00ae
#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MASK_64 0x00b0
#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING 0x00b0
#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_64 0x00b4
#define cfgBIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST 0x00c0
#define cfgBIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL 0x00c2
#define cfgBIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE 0x00c4
#define cfgBIF_CFG_DEV0_EPF1_VF0_MSIX_PBA 0x00c8
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC1 0x0108
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC2 0x010c
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8
#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3 0x02dc
#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3 0x02e0
#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3 0x02e4
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST 0x0400
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST 0x0600
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS 0x0608
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK 0x060c
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY 0x0610
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS 0x0614
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK 0x0618
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL 0x061c
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG0 0x0620
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG1 0x0624
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG2 0x0628
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG3 0x062c
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG4 0x063c
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG0 0x063c
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG5 0x0640
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG1 0x0640
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG6 0x0644
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG2 0x0644
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG7 0x0648
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG3 0x0648
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG8 0x064c
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG9 0x0650
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG10 0x0654
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG11 0x0658
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG12 0x065c
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG13 0x0660
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST 0x071c
#define cfgBIF_CFG_DEV0_EPF1_VF0_RTR_DATA1 0x0720
#define cfgBIF_CFG_DEV0_EPF1_VF0_RTR_DATA2 0x0724
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST 0x0770
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP 0x0774
#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL 0x0776
#endif
