/*
 * Copyright 2025 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef _mmhub_4_2_0_OFFSET_HEADER
#define _mmhub_4_2_0_OFFSET_HEADER



// addressBlock: mmhub_dagb_dagbdec
// base address: 0x60000
#define regDAGB0_CNTL_MISC2                                                                             0x00a7
#define regDAGB0_CNTL_MISC2_BASE_IDX                                                                    1
#define regDAGB1_CNTL_MISC2                                                                             0x01a7
#define regDAGB1_CNTL_MISC2_BASE_IDX                                                                    1


// addressBlock: mmhub_mm_cane_mmcanedec
// base address: 0x60c20
#define regMM_CANE_ICG_CTRL                                                                             0x0313
#define regMM_CANE_ICG_CTRL_BASE_IDX                                                                    1


// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec
// base address: 0x66000
#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB                                                     0x0000
#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX                                            2
#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB                                                     0x0001
#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX                                            2
#define regMMUTCL2_CGTT_CLK_CTRL                                                                        0x0002
#define regMMUTCL2_CGTT_CLK_CTRL_BASE_IDX                                                               2
#define regMMMC_SHARED_ACTIVE_FCN_ID                                                                    0x0003
#define regMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX                                                           2
#define regMMUTCL2_CGTT_BUSY_CTRL                                                                       0x0004
#define regMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX                                                              2
#define regMMUTCL2_GROUP_RET_FAULT_STATUS                                                               0x0005
#define regMMUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX                                                      2


// addressBlock: mmhub_mmutcl2_mmvml2pfdec
// base address: 0x66090
#define regMMVM_L2_CNTL                                                                                 0x0024
#define regMMVM_L2_CNTL_BASE_IDX                                                                        2
#define regMMVM_L2_CNTL2                                                                                0x0025
#define regMMVM_L2_CNTL2_BASE_IDX                                                                       2
#define regMMVM_L2_CNTL3                                                                                0x0026
#define regMMVM_L2_CNTL3_BASE_IDX                                                                       2
#define regMMVM_L2_STATUS                                                                               0x0027
#define regMMVM_L2_STATUS_BASE_IDX                                                                      2
#define regMMVM_DUMMY_PAGE_FAULT_CNTL                                                                   0x0028
#define regMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX                                                          2
#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32                                                              0x0029
#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX                                                     2
#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32                                                              0x002a
#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX                                                     2
#define regMMVM_INVALIDATE_CNTL                                                                         0x002b
#define regMMVM_INVALIDATE_CNTL_BASE_IDX                                                                2
#define regMMVM_L2_PROTECTION_FAULT_CNTL_LO32                                                           0x002c
#define regMMVM_L2_PROTECTION_FAULT_CNTL_LO32_BASE_IDX                                                  2
#define regMMVM_L2_PROTECTION_FAULT_CNTL_HI32                                                           0x002d
#define regMMVM_L2_PROTECTION_FAULT_CNTL_HI32_BASE_IDX                                                  2
#define regMMVM_L2_PROTECTION_FAULT_CNTL2                                                               0x002e
#define regMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX                                                      2
#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3                                                            0x002f
#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX                                                   2
#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4                                                            0x0030
#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX                                                   2
#define regMMVM_L2_PROTECTION_FAULT_STATUS_LO32                                                         0x0031
#define regMMVM_L2_PROTECTION_FAULT_STATUS_LO32_BASE_IDX                                                2
#define regMMVM_L2_PROTECTION_FAULT_STATUS_HI32                                                         0x0032
#define regMMVM_L2_PROTECTION_FAULT_STATUS_HI32_BASE_IDX                                                2
#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32                                                           0x0033
#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX                                                  2
#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32                                                           0x0034
#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX                                                  2
#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32                                                   0x0035
#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX                                          2
#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32                                                   0x0036
#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX                                          2
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32                                             0x0038
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX                                    2
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32                                             0x0039
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX                                    2
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32                                            0x003a
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX                                   2
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32                                            0x003b
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX                                   2
#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32                                                0x003c
#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX                                       2
#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32                                                0x003d
#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX                                       2
#define regMMVM_L2_CNTL4                                                                                0x003e
#define regMMVM_L2_CNTL4_BASE_IDX                                                                       2
#define regMMVM_L2_MM_GROUP_RT_CLASSES                                                                  0x003f
#define regMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX                                                         2
#define regMMVM_L2_BANK_SELECT_RESERVED_CID                                                             0x0040
#define regMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX                                                    2
#define regMMVM_L2_BANK_SELECT_RESERVED_CID2                                                            0x0041
#define regMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX                                                   2
#define regMMVM_L2_CACHE_PARITY_CNTL                                                                    0x0042
#define regMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX                                                           2
#define regMMVM_L2_CGTT_CLK_CTRL                                                                        0x0043
#define regMMVM_L2_CGTT_CLK_CTRL_BASE_IDX                                                               2
#define regMMVM_L2_CNTL5                                                                                0x0044
#define regMMVM_L2_CNTL5_BASE_IDX                                                                       2
#define regMMVM_L2_GCR_CNTL                                                                             0x0045
#define regMMVM_L2_GCR_CNTL_BASE_IDX                                                                    2
#define regMMVM_L2_CGTT_BUSY_CTRL                                                                       0x0046
#define regMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX                                                              2
#define regMMVM_L2_PTE_CACHE_DUMP_CNTL                                                                  0x0047
#define regMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX                                                         2
#define regMMVM_L2_PTE_CACHE_DUMP_READ                                                                  0x0048
#define regMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX                                                         2
#define regMMVM_L2_BANK_SELECT_MASKS                                                                    0x0051
#define regMMVM_L2_BANK_SELECT_MASKS_BASE_IDX                                                           2
#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC                                                          0x0052
#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX                                                 2
#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC                                               0x0053
#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX                                      2
#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC                                             0x0054
#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX                                    2
#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT                                                      0x0055
#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX                                             2
#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ                                                      0x0056
#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX                                             2
#define regMMVML2_IH_FAULT_INTERRUPT_CNTL                                                               0x0057
#define regMMVML2_IH_FAULT_INTERRUPT_CNTL_BASE_IDX                                                      2


// addressBlock: mmhub_mmutcl2_mmvml2prdec
// base address: 0x66210
#define regMMMC_VM_L2_PERFCOUNTER_LO                                                                    0x0084
#define regMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX                                                           2
#define regMMMC_VM_L2_PERFCOUNTER_HI                                                                    0x0085
#define regMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX                                                           2
#define regMMUTCL2_PERFCOUNTER_LO                                                                       0x0086
#define regMMUTCL2_PERFCOUNTER_LO_BASE_IDX                                                              2
#define regMMUTCL2_PERFCOUNTER_HI                                                                       0x0087
#define regMMUTCL2_PERFCOUNTER_HI_BASE_IDX                                                              2


// addressBlock: mmhub_mmutcl2_mmatcl2prdec
// base address: 0x66250
#define regMM_ATC_L2_PERFCOUNTER_LO                                                                     0x0094
#define regMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX                                                            2
#define regMM_ATC_L2_PERFCOUNTER_HI                                                                     0x0095
#define regMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX                                                            2


// addressBlock: mmhub_mmutcl2_mmvml2pldec
// base address: 0x66290
#define regMMMC_VM_L2_PERFCOUNTER0_CFG                                                                  0x00a4
#define regMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX                                                         2
#define regMMMC_VM_L2_PERFCOUNTER1_CFG                                                                  0x00a5
#define regMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX                                                         2
#define regMMMC_VM_L2_PERFCOUNTER2_CFG                                                                  0x00a6
#define regMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX                                                         2
#define regMMMC_VM_L2_PERFCOUNTER3_CFG                                                                  0x00a7
#define regMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX                                                         2
#define regMMMC_VM_L2_PERFCOUNTER4_CFG                                                                  0x00a8
#define regMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX                                                         2
#define regMMMC_VM_L2_PERFCOUNTER5_CFG                                                                  0x00a9
#define regMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX                                                         2
#define regMMMC_VM_L2_PERFCOUNTER6_CFG                                                                  0x00aa
#define regMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX                                                         2
#define regMMMC_VM_L2_PERFCOUNTER7_CFG                                                                  0x00ab
#define regMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX                                                         2
#define regMMMC_VM_L2_PERFCOUNTER8_CFG                                                                  0x00ac
#define regMMMC_VM_L2_PERFCOUNTER8_CFG_BASE_IDX                                                         2
#define regMMMC_VM_L2_PERFCOUNTER9_CFG                                                                  0x00ad
#define regMMMC_VM_L2_PERFCOUNTER9_CFG_BASE_IDX                                                         2
#define regMMMC_VM_L2_PERFCOUNTER10_CFG                                                                 0x00ae
#define regMMMC_VM_L2_PERFCOUNTER10_CFG_BASE_IDX                                                        2
#define regMMMC_VM_L2_PERFCOUNTER11_CFG                                                                 0x00af
#define regMMMC_VM_L2_PERFCOUNTER11_CFG_BASE_IDX                                                        2
#define regMMMC_VM_L2_PERFCOUNTER12_CFG                                                                 0x00b0
#define regMMMC_VM_L2_PERFCOUNTER12_CFG_BASE_IDX                                                        2
#define regMMMC_VM_L2_PERFCOUNTER13_CFG                                                                 0x00b1
#define regMMMC_VM_L2_PERFCOUNTER13_CFG_BASE_IDX                                                        2
#define regMMMC_VM_L2_PERFCOUNTER14_CFG                                                                 0x00b2
#define regMMMC_VM_L2_PERFCOUNTER14_CFG_BASE_IDX                                                        2
#define regMMMC_VM_L2_PERFCOUNTER15_CFG                                                                 0x00b3
#define regMMMC_VM_L2_PERFCOUNTER15_CFG_BASE_IDX                                                        2
#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL                                                             0x00b4
#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                    2
#define regMMUTCL2_PERFCOUNTER0_CFG                                                                     0x00b5
#define regMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX                                                            2
#define regMMUTCL2_PERFCOUNTER1_CFG                                                                     0x00b6
#define regMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX                                                            2
#define regMMUTCL2_PERFCOUNTER2_CFG                                                                     0x00b7
#define regMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX                                                            2
#define regMMUTCL2_PERFCOUNTER3_CFG                                                                     0x00b8
#define regMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX                                                            2
#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL                                                                0x00b9
#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                       2


// addressBlock: mmhub_mmutcl2_mmatcl2pldec
// base address: 0x662f0
#define regMM_ATC_L2_PERFCOUNTER0_CFG                                                                   0x00bc
#define regMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX                                                          2
#define regMM_ATC_L2_PERFCOUNTER1_CFG                                                                   0x00bd
#define regMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX                                                          2
#define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL                                                              0x00cc
#define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                     2


// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec
// base address: 0x66400
#define regMMMC_VM_FB_LOCATION_BASE_LO32                                                                0x0100
#define regMMMC_VM_FB_LOCATION_BASE_LO32_BASE_IDX                                                       2
#define regMMMC_VM_FB_LOCATION_BASE_HI32                                                                0x0101
#define regMMMC_VM_FB_LOCATION_BASE_HI32_BASE_IDX                                                       2
#define regMMMC_VM_FB_LOCATION_TOP_LO32                                                                 0x0102
#define regMMMC_VM_FB_LOCATION_TOP_LO32_BASE_IDX                                                        2
#define regMMMC_VM_FB_LOCATION_TOP_HI32                                                                 0x0103
#define regMMMC_VM_FB_LOCATION_TOP_HI32_BASE_IDX                                                        2
#define regMMMC_VM_AGP_TOP_LO32                                                                         0x0104
#define regMMMC_VM_AGP_TOP_LO32_BASE_IDX                                                                2
#define regMMMC_VM_AGP_TOP_HI32                                                                         0x0105
#define regMMMC_VM_AGP_TOP_HI32_BASE_IDX                                                                2
#define regMMMC_VM_AGP_BOT_LO32                                                                         0x0106
#define regMMMC_VM_AGP_BOT_LO32_BASE_IDX                                                                2
#define regMMMC_VM_AGP_BOT_HI32                                                                         0x0107
#define regMMMC_VM_AGP_BOT_HI32_BASE_IDX                                                                2
#define regMMMC_VM_AGP_BASE_LO32                                                                        0x0108
#define regMMMC_VM_AGP_BASE_LO32_BASE_IDX                                                               2
#define regMMMC_VM_AGP_BASE_HI32                                                                        0x0109
#define regMMMC_VM_AGP_BASE_HI32_BASE_IDX                                                               2
#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32                                                        0x010a
#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32_BASE_IDX                                               2
#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32                                                        0x010b
#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32_BASE_IDX                                               2
#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32                                                       0x010c
#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32_BASE_IDX                                              2
#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32                                                       0x010d
#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32_BASE_IDX                                              2
#define regMMMC_VM_MX_L1_TLB_CNTL                                                                       0x010e
#define regMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX                                                              2


// addressBlock: mmhub_mmutcl2_mmvml2vcdec
// base address: 0x66440
#define regMMVM_CONTEXT0_CNTL                                                                           0x0110
#define regMMVM_CONTEXT0_CNTL_BASE_IDX                                                                  2
#define regMMVM_CONTEXT1_CNTL                                                                           0x0111
#define regMMVM_CONTEXT1_CNTL_BASE_IDX                                                                  2
#define regMMVM_CONTEXT2_CNTL                                                                           0x0112
#define regMMVM_CONTEXT2_CNTL_BASE_IDX                                                                  2
#define regMMVM_CONTEXT3_CNTL                                                                           0x0113
#define regMMVM_CONTEXT3_CNTL_BASE_IDX                                                                  2
#define regMMVM_CONTEXT4_CNTL                                                                           0x0114
#define regMMVM_CONTEXT4_CNTL_BASE_IDX                                                                  2
#define regMMVM_CONTEXT5_CNTL                                                                           0x0115
#define regMMVM_CONTEXT5_CNTL_BASE_IDX                                                                  2
#define regMMVM_CONTEXT6_CNTL                                                                           0x0116
#define regMMVM_CONTEXT6_CNTL_BASE_IDX                                                                  2
#define regMMVM_CONTEXT7_CNTL                                                                           0x0117
#define regMMVM_CONTEXT7_CNTL_BASE_IDX                                                                  2
#define regMMVM_CONTEXT8_CNTL                                                                           0x0118
#define regMMVM_CONTEXT8_CNTL_BASE_IDX                                                                  2
#define regMMVM_CONTEXT9_CNTL                                                                           0x0119
#define regMMVM_CONTEXT9_CNTL_BASE_IDX                                                                  2
#define regMMVM_CONTEXT10_CNTL                                                                          0x011a
#define regMMVM_CONTEXT10_CNTL_BASE_IDX                                                                 2
#define regMMVM_CONTEXT11_CNTL                                                                          0x011b
#define regMMVM_CONTEXT11_CNTL_BASE_IDX                                                                 2
#define regMMVM_CONTEXT12_CNTL                                                                          0x011c
#define regMMVM_CONTEXT12_CNTL_BASE_IDX                                                                 2
#define regMMVM_CONTEXT13_CNTL                                                                          0x011d
#define regMMVM_CONTEXT13_CNTL_BASE_IDX                                                                 2
#define regMMVM_CONTEXT14_CNTL                                                                          0x011e
#define regMMVM_CONTEXT14_CNTL_BASE_IDX                                                                 2
#define regMMVM_CONTEXT15_CNTL                                                                          0x011f
#define regMMVM_CONTEXT15_CNTL_BASE_IDX                                                                 2
#define regMMVM_CONTEXTS_DISABLE                                                                        0x0120
#define regMMVM_CONTEXTS_DISABLE_BASE_IDX                                                               2
#define regMMVM_INVALIDATE_ENG0_SEM                                                                     0x0121
#define regMMVM_INVALIDATE_ENG0_SEM_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG1_SEM                                                                     0x0122
#define regMMVM_INVALIDATE_ENG1_SEM_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG2_SEM                                                                     0x0123
#define regMMVM_INVALIDATE_ENG2_SEM_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG3_SEM                                                                     0x0124
#define regMMVM_INVALIDATE_ENG3_SEM_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG4_SEM                                                                     0x0125
#define regMMVM_INVALIDATE_ENG4_SEM_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG5_SEM                                                                     0x0126
#define regMMVM_INVALIDATE_ENG5_SEM_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG6_SEM                                                                     0x0127
#define regMMVM_INVALIDATE_ENG6_SEM_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG7_SEM                                                                     0x0128
#define regMMVM_INVALIDATE_ENG7_SEM_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG8_SEM                                                                     0x0129
#define regMMVM_INVALIDATE_ENG8_SEM_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG9_SEM                                                                     0x012a
#define regMMVM_INVALIDATE_ENG9_SEM_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG10_SEM                                                                    0x012b
#define regMMVM_INVALIDATE_ENG10_SEM_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG11_SEM                                                                    0x012c
#define regMMVM_INVALIDATE_ENG11_SEM_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG12_SEM                                                                    0x012d
#define regMMVM_INVALIDATE_ENG12_SEM_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG13_SEM                                                                    0x012e
#define regMMVM_INVALIDATE_ENG13_SEM_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG14_SEM                                                                    0x012f
#define regMMVM_INVALIDATE_ENG14_SEM_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG15_SEM                                                                    0x0130
#define regMMVM_INVALIDATE_ENG15_SEM_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG16_SEM                                                                    0x0131
#define regMMVM_INVALIDATE_ENG16_SEM_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG17_SEM                                                                    0x0132
#define regMMVM_INVALIDATE_ENG17_SEM_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG0_REQ                                                                     0x0133
#define regMMVM_INVALIDATE_ENG0_REQ_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG1_REQ                                                                     0x0134
#define regMMVM_INVALIDATE_ENG1_REQ_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG2_REQ                                                                     0x0135
#define regMMVM_INVALIDATE_ENG2_REQ_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG3_REQ                                                                     0x0136
#define regMMVM_INVALIDATE_ENG3_REQ_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG4_REQ                                                                     0x0137
#define regMMVM_INVALIDATE_ENG4_REQ_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG5_REQ                                                                     0x0138
#define regMMVM_INVALIDATE_ENG5_REQ_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG6_REQ                                                                     0x0139
#define regMMVM_INVALIDATE_ENG6_REQ_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG7_REQ                                                                     0x013a
#define regMMVM_INVALIDATE_ENG7_REQ_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG8_REQ                                                                     0x013b
#define regMMVM_INVALIDATE_ENG8_REQ_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG9_REQ                                                                     0x013c
#define regMMVM_INVALIDATE_ENG9_REQ_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG10_REQ                                                                    0x013d
#define regMMVM_INVALIDATE_ENG10_REQ_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG11_REQ                                                                    0x013e
#define regMMVM_INVALIDATE_ENG11_REQ_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG12_REQ                                                                    0x013f
#define regMMVM_INVALIDATE_ENG12_REQ_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG13_REQ                                                                    0x0140
#define regMMVM_INVALIDATE_ENG13_REQ_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG14_REQ                                                                    0x0141
#define regMMVM_INVALIDATE_ENG14_REQ_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG15_REQ                                                                    0x0142
#define regMMVM_INVALIDATE_ENG15_REQ_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG16_REQ                                                                    0x0143
#define regMMVM_INVALIDATE_ENG16_REQ_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG17_REQ                                                                    0x0144
#define regMMVM_INVALIDATE_ENG17_REQ_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG0_ACK                                                                     0x0145
#define regMMVM_INVALIDATE_ENG0_ACK_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG1_ACK                                                                     0x0146
#define regMMVM_INVALIDATE_ENG1_ACK_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG2_ACK                                                                     0x0147
#define regMMVM_INVALIDATE_ENG2_ACK_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG3_ACK                                                                     0x0148
#define regMMVM_INVALIDATE_ENG3_ACK_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG4_ACK                                                                     0x0149
#define regMMVM_INVALIDATE_ENG4_ACK_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG5_ACK                                                                     0x014a
#define regMMVM_INVALIDATE_ENG5_ACK_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG6_ACK                                                                     0x014b
#define regMMVM_INVALIDATE_ENG6_ACK_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG7_ACK                                                                     0x014c
#define regMMVM_INVALIDATE_ENG7_ACK_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG8_ACK                                                                     0x014d
#define regMMVM_INVALIDATE_ENG8_ACK_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG9_ACK                                                                     0x014e
#define regMMVM_INVALIDATE_ENG9_ACK_BASE_IDX                                                            2
#define regMMVM_INVALIDATE_ENG10_ACK                                                                    0x014f
#define regMMVM_INVALIDATE_ENG10_ACK_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG11_ACK                                                                    0x0150
#define regMMVM_INVALIDATE_ENG11_ACK_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG12_ACK                                                                    0x0151
#define regMMVM_INVALIDATE_ENG12_ACK_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG13_ACK                                                                    0x0152
#define regMMVM_INVALIDATE_ENG13_ACK_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG14_ACK                                                                    0x0153
#define regMMVM_INVALIDATE_ENG14_ACK_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG15_ACK                                                                    0x0154
#define regMMVM_INVALIDATE_ENG15_ACK_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG16_ACK                                                                    0x0155
#define regMMVM_INVALIDATE_ENG16_ACK_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG17_ACK                                                                    0x0156
#define regMMVM_INVALIDATE_ENG17_ACK_BASE_IDX                                                           2
#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32                                                         0x0157
#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX                                                2
#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32                                                         0x0158
#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX                                                2
#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32                                                         0x0159
#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX                                                2
#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32                                                         0x015a
#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX                                                2
#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32                                                         0x015b
#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX                                                2
#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32                                                         0x015c
#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX                                                2
#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32                                                         0x015d
#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX                                                2
#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32                                                         0x015e
#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX                                                2
#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32                                                         0x015f
#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX                                                2
#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32                                                         0x0160
#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX                                                2
#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32                                                         0x0161
#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX                                                2
#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32                                                         0x0162
#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX                                                2
#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32                                                         0x0163
#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX                                                2
#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32                                                         0x0164
#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX                                                2
#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32                                                         0x0165
#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX                                                2
#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32                                                         0x0166
#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX                                                2
#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32                                                         0x0167
#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX                                                2
#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32                                                         0x0168
#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX                                                2
#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32                                                         0x0169
#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX                                                2
#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32                                                         0x016a
#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX                                                2
#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32                                                        0x016b
#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX                                               2
#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32                                                        0x016c
#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX                                               2
#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32                                                        0x016d
#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX                                               2
#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32                                                        0x016e
#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX                                               2
#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32                                                        0x016f
#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX                                               2
#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32                                                        0x0170
#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX                                               2
#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32                                                        0x0171
#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX                                               2
#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32                                                        0x0172
#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX                                               2
#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32                                                        0x0173
#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX                                               2
#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32                                                        0x0174
#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX                                               2
#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32                                                        0x0175
#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX                                               2
#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32                                                        0x0176
#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX                                               2
#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32                                                        0x0177
#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX                                               2
#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32                                                        0x0178
#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX                                               2
#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32                                                        0x0179
#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX                                               2
#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32                                                        0x017a
#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX                                               2
#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                      0x017b
#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             2
#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                      0x017c
#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             2
#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                      0x017d
#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             2
#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                      0x017e
#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             2
#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                      0x017f
#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             2
#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                      0x0180
#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             2
#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                      0x0181
#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             2
#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                      0x0182
#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             2
#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                      0x0183
#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             2
#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                      0x0184
#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             2
#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                      0x0185
#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             2
#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                      0x0186
#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             2
#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                      0x0187
#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             2
#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                      0x0188
#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             2
#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                      0x0189
#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             2
#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                      0x018a
#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             2
#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                      0x018b
#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             2
#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                      0x018c
#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             2
#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                      0x018d
#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             2
#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                      0x018e
#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             2
#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                     0x018f
#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            2
#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                     0x0190
#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            2
#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                     0x0191
#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            2
#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                     0x0192
#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            2
#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                     0x0193
#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            2
#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                     0x0194
#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            2
#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                     0x0195
#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            2
#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                     0x0196
#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            2
#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                     0x0197
#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            2
#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                     0x0198
#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            2
#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                     0x0199
#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            2
#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                     0x019a
#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            2
#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                     0x019b
#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            2
#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                     0x019c
#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            2
#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                     0x019d
#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            2
#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                     0x019e
#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            2
#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                     0x019f
#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            2
#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                     0x01a0
#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            2
#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                     0x01a1
#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            2
#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                     0x01a2
#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            2
#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                     0x01a3
#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            2
#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                     0x01a4
#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            2
#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                     0x01a5
#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            2
#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                     0x01a6
#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            2
#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                     0x01a7
#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            2
#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                     0x01a8
#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            2
#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                     0x01a9
#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            2
#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                     0x01aa
#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            2
#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                     0x01ab
#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            2
#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                     0x01ac
#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            2
#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                     0x01ad
#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            2
#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                     0x01ae
#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            2
#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                    0x01af
#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           2
#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                    0x01b0
#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           2
#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                    0x01b1
#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           2
#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                    0x01b2
#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           2
#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                    0x01b3
#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           2
#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                    0x01b4
#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           2
#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                    0x01b5
#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           2
#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                    0x01b6
#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           2
#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                    0x01b7
#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           2
#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                    0x01b8
#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           2
#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                    0x01b9
#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           2
#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                    0x01ba
#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           2
#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                       0x01bb
#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              2
#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                       0x01bc
#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              2
#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                       0x01bd
#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              2
#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                       0x01be
#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              2
#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                       0x01bf
#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              2
#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                       0x01c0
#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              2
#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                       0x01c1
#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              2
#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                       0x01c2
#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              2
#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                       0x01c3
#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              2
#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                       0x01c4
#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              2
#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                       0x01c5
#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              2
#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                       0x01c6
#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              2
#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                       0x01c7
#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              2
#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                       0x01c8
#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              2
#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                       0x01c9
#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              2
#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                       0x01ca
#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              2
#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                       0x01cb
#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              2
#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                       0x01cc
#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              2
#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                       0x01cd
#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              2
#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                       0x01ce
#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              2
#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                      0x01cf
#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             2
#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                      0x01d0
#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             2
#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                      0x01d1
#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             2
#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                      0x01d2
#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             2
#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                      0x01d3
#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             2
#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                      0x01d4
#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             2
#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                      0x01d5
#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             2
#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                      0x01d6
#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             2
#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                      0x01d7
#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             2
#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                      0x01d8
#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             2
#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                      0x01d9
#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             2
#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                      0x01da
#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             2
#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                                    0x01db
#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                           2
#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x01dc
#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  2
#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x01dd
#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  2
#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x01de
#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  2
#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x01df
#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  2
#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x01e0
#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  2
#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x01e1
#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  2
#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x01e2
#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  2
#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x01e3
#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  2
#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x01e4
#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  2
#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x01e5
#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  2
#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x01e6
#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 2
#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x01e7
#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 2
#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x01e8
#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 2
#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x01e9
#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 2
#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x01ea
#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 2
#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x01eb
#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 2


// addressBlock: mmhub_mmutcl2_mmvmsharedvfdec
// base address: 0x667c0
#define regMMMC_VM_PCIE_ATOMIC_SUPPORTED                                                                0x01f0
#define regMMMC_VM_PCIE_ATOMIC_SUPPORTED_BASE_IDX                                                       2


// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec
// base address: 0x667e0
#define regMMVM_PCIE_ATS_CNTL                                                                           0x01f8
#define regMMVM_PCIE_ATS_CNTL_BASE_IDX                                                                  2
#define regMMMC_VM_NB_MMIOBASE                                                                          0x01f9
#define regMMMC_VM_NB_MMIOBASE_BASE_IDX                                                                 2
#define regMMMC_VM_NB_MMIOLIMIT                                                                         0x01fa
#define regMMMC_VM_NB_MMIOLIMIT_BASE_IDX                                                                2
#define regMMMC_VM_NB_PCI_CTRL                                                                          0x01fb
#define regMMMC_VM_NB_PCI_CTRL_BASE_IDX                                                                 2
#define regMMMC_VM_NB_PCI_ARB                                                                           0x01fc
#define regMMMC_VM_NB_PCI_ARB_BASE_IDX                                                                  2
#define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1                                                                 0x01fd
#define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX                                                        2
#define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2                                                                0x01fe
#define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX                                                       2
#define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2                                                                0x01ff
#define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX                                                       2
#define regMMMC_VM_STEERING                                                                             0x0200
#define regMMMC_VM_STEERING_BASE_IDX                                                                    2
#define regMMMC_SHARED_VIRT_RESET_REQ                                                                   0x0201
#define regMMMC_SHARED_VIRT_RESET_REQ_BASE_IDX                                                          2
#define regMMMC_VM_XGMI_LFB_CNTL                                                                        0x0202
#define regMMMC_VM_XGMI_LFB_CNTL_BASE_IDX                                                               2
#define regMMMC_VM_XGMI_LFB_SIZE                                                                        0x0203
#define regMMMC_VM_XGMI_LFB_SIZE_BASE_IDX                                                               2
#define regMMMC_VM_HOST_MAPPING                                                                         0x0204
#define regMMMC_VM_HOST_MAPPING_BASE_IDX                                                                2
#define regMMMC_VM_XGMI_GPUIOV_ENABLE                                                                   0x0205
#define regMMMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX                                                          2
#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START                                                         0x0206
#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX                                                2
#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END                                                           0x0207
#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX                                                  2
#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START                                                           0x0208
#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX                                                  2
#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END                                                             0x0209
#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX                                                    2
#define regMMMC_VM_LPDDR_ADDRESS_START                                                                  0x020a
#define regMMMC_VM_LPDDR_ADDRESS_START_BASE_IDX                                                         2
#define regMMMC_VM_LPDDR_ADDRESS_END                                                                    0x020b
#define regMMMC_VM_LPDDR_ADDRESS_END_BASE_IDX                                                           2
#define regMMMC_VM_APT_CNTL                                                                             0x020c
#define regMMMC_VM_APT_CNTL_BASE_IDX                                                                    2
#define regMMUTCL2_HARVEST_BYPASS_GROUPS                                                                0x020d
#define regMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX                                                       2


// addressBlock: mmhub_mmutcl2_mmatcl2dec
// base address: 0x669d0
#define regMM_ATC_L2_CNTL                                                                               0x0274
#define regMM_ATC_L2_CNTL_BASE_IDX                                                                      2
#define regMM_ATC_L2_CNTL2                                                                              0x0275
#define regMM_ATC_L2_CNTL2_BASE_IDX                                                                     2
#define regMM_ATC_L2_CACHE_DATA0                                                                        0x0278
#define regMM_ATC_L2_CACHE_DATA0_BASE_IDX                                                               2
#define regMM_ATC_L2_CACHE_DATA1                                                                        0x0279
#define regMM_ATC_L2_CACHE_DATA1_BASE_IDX                                                               2
#define regMM_ATC_L2_CACHE_DATA2                                                                        0x027a
#define regMM_ATC_L2_CACHE_DATA2_BASE_IDX                                                               2
#define regMM_ATC_L2_CNTL3                                                                              0x027d
#define regMM_ATC_L2_CNTL3_BASE_IDX                                                                     2
#define regMM_ATC_L2_CNTL4                                                                              0x027e
#define regMM_ATC_L2_CNTL4_BASE_IDX                                                                     2
#define regMM_ATC_L2_CNTL5                                                                              0x027f
#define regMM_ATC_L2_CNTL5_BASE_IDX                                                                     2
#define regMM_ATC_L2_MM_GROUP_RT_CLASSES                                                                0x0280
#define regMM_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX                                                       2
#define regMM_ATC_L2_STATUS                                                                             0x0281
#define regMM_ATC_L2_STATUS_BASE_IDX                                                                    2
#define regMM_ATC_L2_MISC_CG                                                                            0x0282
#define regMM_ATC_L2_MISC_CG_BASE_IDX                                                                   2
#define regMM_ATC_L2_CGTT_CLK_CTRL                                                                      0x0283
#define regMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX                                                             2
#define regMM_ATC_L2_SDPPORT_CTRL                                                                       0x0287
#define regMM_ATC_L2_SDPPORT_CTRL_BASE_IDX                                                              2


// addressBlock: mmhub_mmutcl2_mmvml2pspdec
// base address: 0x66b40
#define regMMVM_IOMMU_CONTROL_REGISTER                                                                  0x02d4
#define regMMVM_IOMMU_CONTROL_REGISTER_BASE_IDX                                                         2
#define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER                                         0x02d5
#define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX                                2


// addressBlock: mmhub_mmutcl2_mmvmsharedpspdec
// base address: 0x66b90
#define regMMMC_VM_FB_OFFSET                                                                            0x02ec
#define regMMMC_VM_FB_OFFSET_BASE_IDX                                                                   2


#endif