// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2023, SberDevices. All Rights Reserved.
 *
 * Author: Martin Kurbanov <mmkurbanov@salutedevices.com>
 */

#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/mtd/spinand.h>

#define SPINAND_MFR_FORESEE             0xCD

#define F35SQB002G_STATUS_ECC_MASK              (7 << 4)
#define F35SQB002G_STATUS_ECC_NO_BITFLIPS       (0 << 4)
#define F35SQB002G_STATUS_ECC_1_3_BITFLIPS      (1 << 4)
#define F35SQB002G_STATUS_ECC_UNCOR_ERROR       (7 << 4)

static SPINAND_OP_VARIANTS(read_cache_variants,
                SPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(0, 1, NULL, 0, 0),
                SPINAND_PAGE_READ_FROM_CACHE_1S_1S_2S_OP(0, 1, NULL, 0, 0),
                SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(0, 1, NULL, 0, 0),
                SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(0, 1, NULL, 0, 0));

static SPINAND_OP_VARIANTS(write_cache_variants,
                SPINAND_PROG_LOAD_1S_1S_4S_OP(true, 0, NULL, 0),
                SPINAND_PROG_LOAD_1S_1S_1S_OP(true, 0, NULL, 0));

static SPINAND_OP_VARIANTS(update_cache_variants,
                SPINAND_PROG_LOAD_1S_1S_4S_OP(false, 0, NULL, 0),
                SPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0));

static int f35sqa002g_ooblayout_ecc(struct mtd_info *mtd, int section,
                                    struct mtd_oob_region *region)
{
        return -ERANGE;
}

static int f35sqa002g_ooblayout_free(struct mtd_info *mtd, int section,
                                     struct mtd_oob_region *region)
{
        if (section)
                return -ERANGE;

        /* Reserve 2 bytes for the BBM. */
        region->offset = 2;
        region->length = 62;

        return 0;
}

static const struct mtd_ooblayout_ops f35sqa002g_ooblayout = {
        .ecc = f35sqa002g_ooblayout_ecc,
        .free = f35sqa002g_ooblayout_free,
};

static int f35sqa002g_ecc_get_status(struct spinand_device *spinand, u8 status)
{
        struct nand_device *nand = spinand_to_nand(spinand);

        switch (status & STATUS_ECC_MASK) {
        case STATUS_ECC_NO_BITFLIPS:
                return 0;

        case STATUS_ECC_HAS_BITFLIPS:
                return nanddev_get_ecc_conf(nand)->strength;

        default:
                break;
        }

        /* More than 1-bit error was detected in one or more sectors and
         * cannot be corrected.
         */
        return -EBADMSG;
}

static int f35sqb002g_ecc_get_status(struct spinand_device *spinand, u8 status)
{
        switch (status & F35SQB002G_STATUS_ECC_MASK) {
        case F35SQB002G_STATUS_ECC_NO_BITFLIPS:
                return 0;

        case F35SQB002G_STATUS_ECC_1_3_BITFLIPS:
                return 3;

        case F35SQB002G_STATUS_ECC_UNCOR_ERROR:
                return -EBADMSG;

        default: /* (2 << 4) through (6 << 4) are 4-8 corrected errors */
                return ((status & F35SQB002G_STATUS_ECC_MASK) >> 4) + 2;
        }

        return -EINVAL;
}

static const struct spinand_info foresee_spinand_table[] = {
        SPINAND_INFO("F35SQA002G",
                     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x72, 0x72),
                     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
                     NAND_ECCREQ(1, 512),
                     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
                                              &write_cache_variants,
                                              &update_cache_variants),
                     SPINAND_HAS_QE_BIT,
                     SPINAND_ECCINFO(&f35sqa002g_ooblayout,
                                     f35sqa002g_ecc_get_status)),
        SPINAND_INFO("F35SQA001G",
                     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71, 0x71),
                     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
                     NAND_ECCREQ(1, 512),
                     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
                                              &write_cache_variants,
                                              &update_cache_variants),
                     SPINAND_HAS_QE_BIT,
                     SPINAND_ECCINFO(&f35sqa002g_ooblayout,
                                     f35sqa002g_ecc_get_status)),
        SPINAND_INFO("F35SQB002G",
                     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52, 0x52),
                     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
                     NAND_ECCREQ(8, 512),
                     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
                                              &write_cache_variants,
                                              &update_cache_variants),
                     SPINAND_HAS_QE_BIT,
                     SPINAND_ECCINFO(&f35sqa002g_ooblayout,
                                     f35sqb002g_ecc_get_status)),
};

static const struct spinand_manufacturer_ops foresee_spinand_manuf_ops = {
};

const struct spinand_manufacturer foresee_spinand_manufacturer = {
        .id = SPINAND_MFR_FORESEE,
        .name = "FORESEE",
        .chips = foresee_spinand_table,
        .nchips = ARRAY_SIZE(foresee_spinand_table),
        .ops = &foresee_spinand_manuf_ops,
};