#ifndef __RTS5260_H__
#define __RTS5260_H__

#define RTS5260_DVCC_CTRL               0xFF73
#define RTS5260_DVCC_OCP_EN             (0x01 << 7)
#define RTS5260_DVCC_OCP_THD_MASK       (0x07 << 4)
#define RTS5260_DVCC_POWERON            (0x01 << 3)
#define RTS5260_DVCC_OCP_CL_EN          (0x01 << 2)

#define RTS5260_DVIO_CTRL               0xFF75
#define RTS5260_DVIO_OCP_EN             (0x01 << 7)
#define RTS5260_DVIO_OCP_THD_MASK       (0x07 << 4)
#define RTS5260_DVIO_POWERON            (0x01 << 3)
#define RTS5260_DVIO_OCP_CL_EN          (0x01 << 2)

#define RTS5260_DV331812_CFG            0xFF71
#define RTS5260_DV331812_OCP_EN         (0x01 << 7)
#define RTS5260_DV331812_OCP_THD_MASK   (0x07 << 4)
#define RTS5260_DV331812_POWERON        (0x01 << 3)
#define RTS5260_DV331812_SEL            (0x01 << 2)
#define RTS5260_DV331812_VDD1           (0x01 << 2)
#define RTS5260_DV331812_VDD2           (0x00 << 2)

#define RTS5260_DV331812_OCP_THD_120    (0x00 << 4)
#define RTS5260_DV331812_OCP_THD_140    (0x01 << 4)
#define RTS5260_DV331812_OCP_THD_160    (0x02 << 4)
#define RTS5260_DV331812_OCP_THD_180    (0x03 << 4)
#define RTS5260_DV331812_OCP_THD_210    (0x04 << 4)
#define RTS5260_DV331812_OCP_THD_240    (0x05 << 4)
#define RTS5260_DV331812_OCP_THD_270    (0x06 << 4)
#define RTS5260_DV331812_OCP_THD_300    (0x07 << 4)

#define RTS5260_DVIO_OCP_THD_250        (0x00 << 4)
#define RTS5260_DVIO_OCP_THD_300        (0x01 << 4)
#define RTS5260_DVIO_OCP_THD_350        (0x02 << 4)
#define RTS5260_DVIO_OCP_THD_400        (0x03 << 4)
#define RTS5260_DVIO_OCP_THD_450        (0x04 << 4)
#define RTS5260_DVIO_OCP_THD_500        (0x05 << 4)
#define RTS5260_DVIO_OCP_THD_550        (0x06 << 4)
#define RTS5260_DVIO_OCP_THD_600        (0x07 << 4)

#define RTS5260_DVCC_OCP_THD_550        (0x00 << 4)
#define RTS5260_DVCC_OCP_THD_970        (0x05 << 4)

#endif