/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright(c) 2025 Intel Corporation */
#ifndef ICP_QAT_HW_51_COMP_DEFS_H_
#define ICP_QAT_HW_51_COMP_DEFS_H_

#include <linux/bits.h>

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SOM_CONTROL_BITPOS        28
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SOM_CONTROL_MASK          GENMASK(1, 0)
enum icp_qat_hw_comp_51_som_control {
        ICP_QAT_HW_COMP_51_SOM_CONTROL_NORMAL_MODE = 0x0,
        ICP_QAT_HW_COMP_51_SOM_CONTROL_DICTIONARY_MODE = 0x1,
        ICP_QAT_HW_COMP_51_SOM_CONTROL_INPUT_CRC = 0x2,
        ICP_QAT_HW_COMP_51_SOM_CONTROL_RESERVED_MODE = 0x3,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SOM_CONTROL_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_SOM_CONTROL_NORMAL_MODE
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_RD_CONTROL_BITPOS       27
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK         GENMASK(0, 0)
enum icp_qat_hw_comp_51_skip_hash_rd_control {
        ICP_QAT_HW_COMP_51_SKIP_HASH_RD_CONTROL_NO_SKIP = 0x0,
        ICP_QAT_HW_COMP_51_SKIP_HASH_RD_CONTROL_SKIP_HASH_READS = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_RD_CONTROL_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_SKIP_HASH_RD_CONTROL_NO_SKIP
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYPASS_COMPRESSION_BITPOS 25
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYPASS_COMPRESSION_MASK   GENMASK(0, 0)
enum icp_qat_hw_comp_51_bypass_compression {
        ICP_QAT_HW_COMP_51_BYPASS_COMPRESSION_DISABLED = 0x0,
        ICP_QAT_HW_COMP_51_BYPASS_COMPRESSION_ENABLED = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYPASS_COMPRESSION_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_BYPASS_COMPRESSION_DISABLED
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_DMM_ALGORITHM_BITPOS      22
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_DMM_ALGORITHM_MASK        GENMASK(0, 0)
enum icp_qat_hw_comp_51_dmm_algorithm {
        ICP_QAT_HW_COMP_51_DMM_ALGORITHM_EDMM_ENABLED = 0x0,
        ICP_QAT_HW_COMP_51_DMM_ALGORITHM_ZSTD_DMM_LITE = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_DMM_ALGORITHM_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_DMM_ALGORITHM_EDMM_ENABLED
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_TOKEN_FUSION_INTERNAL_ONLY_BITPOS 21
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_TOKEN_FUSION_INTERNAL_ONLY_MASK   GENMASK(0, 0)
enum icp_qat_hw_comp_51_token_fusion_internal_only {
        ICP_QAT_HW_COMP_51_TOKEN_FUSION_INTERNAL_ONLY_ENABLED = 0x0,
        ICP_QAT_HW_COMP_51_TOKEN_FUSION_INTERNAL_ONLY_DISABLED = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_TOKEN_FUSION_INTERNAL_ONLY_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_TOKEN_FUSION_INTERNAL_ONLY_ENABLED
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BMS_BITPOS        19
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BMS_MASK          GENMASK(1, 0)
enum icp_qat_hw_comp_51_bms {
        ICP_QAT_HW_COMP_51_BMS_BMS_64KB = 0x0,
        ICP_QAT_HW_COMP_51_BMS_BMS_256KB = 0x1,
        ICP_QAT_HW_COMP_51_BMS_BMS_1MB = 0x2,
        ICP_QAT_HW_COMP_51_BMS_BMS_4MB = 0x3,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BMS_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_BMS_BMS_64KB
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS        18
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK          GENMASK(0, 0)
enum icp_qat_hw_comp_51_scb_mode_reset_mask {
        ICP_QAT_HW_COMP_51_SCB_MODE_RESET_MASK_DO_NOT_RESET_HB_HT = 0x0,
        ICP_QAT_HW_COMP_51_SCB_MODE_RESET_MASK_RESET_HB_HT = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SCB_MODE_RESET_MASK_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_SCB_MODE_RESET_MASK_DO_NOT_RESET_HB_HT
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_BITPOS      2
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_MASK        GENMASK(0, 0)
enum icp_qat_hw_comp_51_zstd_frame_gen_dec_en {
        ICP_QAT_HW_COMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_DISABLE = 0x0,
        ICP_QAT_HW_COMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_ENABLE = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_ENABLE
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_CNV_DISABLE_BITPOS        1
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_CNV_DISABLE_MASK          GENMASK(0, 0)
enum icp_qat_hw_comp_51_cnv_disable {
        ICP_QAT_HW_COMP_51_CNV_DISABLE_CNV_ENABLED = 0x0,
        ICP_QAT_HW_COMP_51_CNV_DISABLE_CNV_DISABLED = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_CNV_DISABLE_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_CNV_DISABLE_CNV_ENABLED
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ASB_DISABLE_BITPOS        0
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ASB_DISABLE_MASK          GENMASK(0, 0)
enum icp_qat_hw_comp_51_asb_disable {
        ICP_QAT_HW_COMP_51_ASB_DISABLE_ASB_ENABLED = 0x0,
        ICP_QAT_HW_COMP_51_ASB_DISABLE_ASB_DISABLED = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ASB_DISABLE_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_ASB_DISABLE_ASB_ENABLED
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_BITPOS 21
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_MASK   GENMASK(0, 0)
enum icp_qat_hw_comp_51_spec_decoder_internal_only {
        ICP_QAT_HW_COMP_51_SPEC_DECODER_INTERNAL_ONLY_NORMAL = 0x0,
        ICP_QAT_HW_COMP_51_SPEC_DECODER_INTERNAL_ONLY_DISABLED = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_SPEC_DECODER_INTERNAL_ONLY_NORMAL
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_BITPOS    20
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_MASK      GENMASK(0, 0)
enum icp_qat_hw_comp_51_mini_xcam_internal_only {
        ICP_QAT_HW_COMP_51_MINI_XCAM_INTERNAL_ONLY_NORMAL = 0x0,
        ICP_QAT_HW_COMP_51_MINI_XCAM_INTERNAL_ONLY_DISABLED = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_MINI_XCAM_INTERNAL_ONLY_NORMAL
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_REP_OFF_ENC_INTERNAL_ONLY_BITPOS  19
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_REP_OFF_ENC_INTERNAL_ONLY_MASK    GENMASK(0, 0)
enum icp_qat_hw_comp_51_rep_off_enc_internal_only {
        ICP_QAT_HW_COMP_51_REP_OFF_ENC_INTERNAL_ONLY_ENABLED = 0x0,
        ICP_QAT_HW_COMP_51_REP_OFF_ENC_INTERNAL_ONLY_DISABLED = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_REP_OFF_ENC_INTERNAL_ONLY_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_REP_OFF_ENC_INTERNAL_ONLY_ENABLED
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_PROG_BLOCK_DROP_INTERNAL_ONLY_BITPOS      18
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_PROG_BLOCK_DROP_INTERNAL_ONLY_MASK        GENMASK(0, 0)
enum icp_qat_hw_comp_51_prog_block_drop_internal_only {
        ICP_QAT_HW_COMP_51_PROG_BLOCK_DROP_INTERNAL_ONLY_DISABLE = 0x0,
        ICP_QAT_HW_COMP_51_PROG_BLOCK_DROP_INTERNAL_ONLY_ENABLE = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_PROG_BLOCK_DROP_INTERNAL_ONLY_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_PROG_BLOCK_DROP_INTERNAL_ONLY_DISABLE
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_BITPOS   17
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_MASK     GENMASK(0, 0)
enum icp_qat_hw_comp_51_skip_hash_override_internal_only {
        ICP_QAT_HW_COMP_51_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_DETERMINE_HASH_PARAMS = 0x0,
        ICP_QAT_HW_COMP_51_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_OVERRIDE_HASH_PARAMS = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_DETERMINE_HASH_PARAMS
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_HBS_BITPOS        14
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_HBS_MASK          GENMASK(2, 0)
enum icp_qat_hw_comp_51_hbs {
        ICP_QAT_HW_COMP_51_HBS_32KB = 0x0,
        ICP_QAT_HW_COMP_51_HBS_64KB = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_HBS_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_HBS_32KB
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ABD_BITPOS        13
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ABD_MASK          GENMASK(0, 0)
enum icp_qat_hw_comp_51_abd {
        ICP_QAT_HW_COMP_51_ABD_ABD_ENABLED = 0x0,
        ICP_QAT_HW_COMP_51_ABD_ABD_DISABLED = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ABD_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_ABD_ABD_ENABLED
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LLLBD_CTRL_BITPOS 12
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LLLBD_CTRL_MASK   GENMASK(0, 0)
enum icp_qat_hw_comp_51_lllbd_ctrl {
        ICP_QAT_HW_COMP_51_LLLBD_CTRL_LLLBD_ENABLED = 0x0,
        ICP_QAT_HW_COMP_51_LLLBD_CTRL_LLLBD_DISABLED = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LLLBD_CTRL_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_LLLBD_CTRL_LLLBD_ENABLED
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SEARCH_DEPTH_BITPOS       8
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SEARCH_DEPTH_MASK         GENMASK(3, 0)
enum icp_qat_hw_comp_51_search_depth {
        ICP_QAT_HW_COMP_51_SEARCH_DEPTH_LEVEL_1 = 0x1,
        ICP_QAT_HW_COMP_51_SEARCH_DEPTH_LEVEL_6 = 0x3,
        ICP_QAT_HW_COMP_51_SEARCH_DEPTH_LEVEL_9 = 0x4,
        ICP_QAT_HW_COMP_51_SEARCH_DEPTH_LEVEL_10 = 0x4,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SEARCH_DEPTH_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_SEARCH_DEPTH_LEVEL_1
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_FORMAT_BITPOS     5
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_FORMAT_MASK       GENMASK(2, 0)
enum icp_qat_hw_comp_51_format {
        ICP_QAT_HW_COMP_51_FORMAT_ILZ77 = 0x1,
        ICP_QAT_HW_COMP_51_FORMAT_LZ4 = 0x2,
        ICP_QAT_HW_COMP_51_FORMAT_LZ4s = 0x3,
        ICP_QAT_HW_COMP_51_FORMAT_ZSTD = 0x4,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_FORMAT_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_FORMAT_ILZ77
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS  4
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MIN_MATCH_CONTROL_MASK    GENMASK(0, 0)
enum icp_qat_hw_comp_51_min_match_control {
        ICP_QAT_HW_COMP_51_MIN_MATCH_CONTROL_MATCH_3B = 0x0,
        ICP_QAT_HW_COMP_51_MIN_MATCH_CONTROL_MATCH_4B = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MIN_MATCH_CONTROL_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_MIN_MATCH_CONTROL_MATCH_3B
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS        3
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_COLLISION_MASK          GENMASK(0, 0)
enum icp_qat_hw_comp_51_skip_hash_collision {
        ICP_QAT_HW_COMP_51_SKIP_HASH_COLLISION_ALLOW = 0x0,
        ICP_QAT_HW_COMP_51_SKIP_HASH_COLLISION_DONT_ALLOW = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_COLLISION_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_SKIP_HASH_COLLISION_ALLOW
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS   2
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_UPDATE_MASK     GENMASK(0, 0)
enum icp_qat_hw_comp_51_skip_hash_update {
        ICP_QAT_HW_COMP_51_SKIP_HASH_UPDATE_ALLOW = 0x0,
        ICP_QAT_HW_COMP_51_SKIP_HASH_UPDATE_DONT_ALLOW = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_UPDATE_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_SKIP_HASH_UPDATE_ALLOW
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYTE_SKIP_BITPOS  1
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYTE_SKIP_MASK    GENMASK(0, 0)
enum icp_qat_hw_comp_51_byte_skip {
        ICP_QAT_HW_COMP_51_BYTE_SKIP_3BYTE_TOKEN = 0x0,
        ICP_QAT_HW_COMP_51_BYTE_SKIP_3BYTE_LITERAL = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYTE_SKIP_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_BYTE_SKIP_3BYTE_TOKEN
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_BITPOS 0
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_MASK   GENMASK(0, 0)
enum icp_qat_hw_comp_51_lz4_block_checksum {
        ICP_QAT_HW_COMP_51_LZ4_BLOCK_CHECKSUM_ABSENT = 0x0,
        ICP_QAT_HW_COMP_51_LZ4_BLOCK_CHECKSUM_PRESENT = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_DEFAULT_VAL \
        ICP_QAT_HW_COMP_51_LZ4_BLOCK_CHECKSUM_ABSENT
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_DISCARD_DATA_BITPOS     26
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_DISCARD_DATA_MASK       GENMASK(0, 0)
enum icp_qat_hw_decomp_51_discard_data {
        ICP_QAT_HW_DECOMP_51_DISCARD_DATA_DISABLED = 0x0,
        ICP_QAT_HW_DECOMP_51_DISCARD_DATA_ENABLED = 0x1,
};

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_DISCARD_DATA_DEFAULT_VAL \
        ICP_QAT_HW_DECOMP_51_DISCARD_DATA_DISABLED
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_BMS_BITPOS      19
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_BMS_MASK        GENMASK(1, 0)
enum icp_qat_hw_decomp_51_bms {
        ICP_QAT_HW_DECOMP_51_BMS_BMS_64KB = 0x0,
        ICP_QAT_HW_DECOMP_51_BMS_BMS_256KB = 0x1,
        ICP_QAT_HW_DECOMP_51_BMS_BMS_1MB = 0x2,
        ICP_QAT_HW_DECOMP_51_BMS_BMS_4MB = 0x3,
};

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_BMS_DEFAULT_VAL \
        ICP_QAT_HW_DECOMP_51_BMS_BMS_64KB
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_BITPOS    2
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_MASK      GENMASK(0, 0)
enum icp_qat_hw_decomp_51_zstd_frame_gen_dec_en {
        ICP_QAT_HW_DECOMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_DISABLE = 0x0,
        ICP_QAT_HW_DECOMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_ENABLE = 0x1,
};

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_DEFAULT_VAL \
        ICP_QAT_HW_DECOMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_ENABLE
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_BITPOS       21
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_MASK         GENMASK(0, 0)
enum icp_qat_hw_decomp_51_spec_decoder_internal_only {
        ICP_QAT_HW_DECOMP_51_SPEC_DECODER_INTERNAL_ONLY_NORMAL = 0x0,
        ICP_QAT_HW_DECOMP_51_SPEC_DECODER_INTERNAL_ONLY_DISABLED = 0x1,
};

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_DEFAULT_VAL \
        ICP_QAT_HW_DECOMP_51_SPEC_DECODER_INTERNAL_ONLY_NORMAL
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_BITPOS  20
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_MASK    GENMASK(0, 0)
enum icp_qat_hw_decomp_51_mini_xcam_internal_only {
        ICP_QAT_HW_DECOMP_51_MINI_XCAM_INTERNAL_ONLY_NORMAL = 0x0,
        ICP_QAT_HW_DECOMP_51_MINI_XCAM_INTERNAL_ONLY_DISABLED = 0x1,
};

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_DEFAULT_VAL \
        ICP_QAT_HW_DECOMP_51_MINI_XCAM_INTERNAL_ONLY_NORMAL
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_HBS_BITPOS      14
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_HBS_MASK        GENMASK(2, 0)
enum icp_qat_hw_decomp_51_hbs {
        ICP_QAT_HW_DECOMP_51_HBS_32KB = 0x0,
        ICP_QAT_HW_DECOMP_51_HBS_64KB = 0x1,
};

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_HBS_DEFAULT_VAL \
        ICP_QAT_HW_DECOMP_51_HBS_32KB
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_FORMAT_BITPOS   5
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_FORMAT_MASK     GENMASK(2, 0)
enum icp_qat_hw_decomp_51_format {
        ICP_QAT_HW_DECOMP_51_FORMAT_ILZ77 = 0x1,
        ICP_QAT_HW_DECOMP_51_FORMAT_LZ4 = 0x2,
        ICP_QAT_HW_DECOMP_51_FORMAT_RESERVED = 0x3,
        ICP_QAT_HW_DECOMP_51_FORMAT_ZSTD = 0x4,
};

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_FORMAT_DEFAULT_VAL \
        ICP_QAT_HW_DECOMP_51_FORMAT_ILZ77
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_BITPOS       0
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_MASK         GENMASK(0, 0)
enum icp_qat_hw_decomp_51_lz4_block_checksum {
        ICP_QAT_HW_DECOMP_51_LZ4_BLOCK_CHECKSUM_ABSENT = 0x0,
        ICP_QAT_HW_DECOMP_51_LZ4_BLOCK_CHECKSUM_PRESENT = 0x1,
};

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_DEFAULT_VAL \
        ICP_QAT_HW_DECOMP_51_LZ4_BLOCK_CHECKSUM_ABSENT

#endif /* ICP_QAT_HW_51_COMP_DEFS_H_ */