/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#ifndef QCOM_PHY_QMP_PCS_V8_H_
#define QCOM_PHY_QMP_PCS_V8_H_

/* Only for QMP V8 PHY - USB/PCIe PCS registers */
#define QPHY_V8_PCS_SW_RESET                    0x000
#define QPHY_V8_PCS_PCS_STATUS1                 0x014
#define QPHY_V8_PCS_POWER_DOWN_CONTROL          0x040
#define QPHY_V8_PCS_START_CONTROL               0x044
#define QPHY_V8_PCS_POWER_STATE_CONFIG1         0x090
#define QPHY_V8_PCS_LOCK_DETECT_CONFIG1         0x0c4
#define QPHY_V8_PCS_LOCK_DETECT_CONFIG2         0x0c8
#define QPHY_V8_PCS_LOCK_DETECT_CONFIG3         0x0cc
#define QPHY_V8_PCS_LOCK_DETECT_CONFIG6         0x0d8
#define QPHY_V8_PCS_REFGEN_REQ_CONFIG1          0x0dc
#define QPHY_V8_PCS_RX_SIGDET_LVL               0x188
#define QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_L        0x190
#define QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_H        0x194
#define QPHY_V8_PCS_RATE_SLEW_CNTRL1            0x198
#define QPHY_V8_PCS_CDR_RESET_TIME              0x1b0
#define QPHY_V8_PCS_ALIGN_DETECT_CONFIG1        0x1c0
#define QPHY_V8_PCS_ALIGN_DETECT_CONFIG2        0x1c4
#define QPHY_V8_PCS_PCS_TX_RX_CONFIG            0x1d0
#define QPHY_V8_PCS_EQ_CONFIG1                  0x1dc
#define QPHY_V8_PCS_EQ_CONFIG2                  0x1e0
#define QPHY_V8_PCS_EQ_CONFIG5                  0x1ec

#endif