// SPDX-License-Identifier: GPL-2.0
#ifndef ARCH_PERF_ARM64_EXCEPTION_TYPES_H
#define ARCH_PERF_ARM64_EXCEPTION_TYPES_H

/* Per asm/virt.h */
#define HVC_STUB_ERR              0xbadca11

/* Per asm/kvm_asm.h */
#define ARM_EXCEPTION_IRQ               0
#define ARM_EXCEPTION_EL1_SERROR        1
#define ARM_EXCEPTION_TRAP              2
#define ARM_EXCEPTION_IL                3
/* The hyp-stub will return this for any kvm_call_hyp() call */
#define ARM_EXCEPTION_HYP_GONE          HVC_STUB_ERR

#define kvm_arm_exception_type                                  \
        {ARM_EXCEPTION_IRQ,             "IRQ"           },      \
        {ARM_EXCEPTION_EL1_SERROR,      "SERROR"        },      \
        {ARM_EXCEPTION_TRAP,            "TRAP"          },      \
        {ARM_EXCEPTION_IL,              "ILLEGAL"       },      \
        {ARM_EXCEPTION_HYP_GONE,        "HYP_GONE"      }

/* Per asm/esr.h */
#define ESR_ELx_EC_UNKNOWN      (0x00)
#define ESR_ELx_EC_WFx          (0x01)
/* Unallocated EC: 0x02 */
#define ESR_ELx_EC_CP15_32      (0x03)
#define ESR_ELx_EC_CP15_64      (0x04)
#define ESR_ELx_EC_CP14_MR      (0x05)
#define ESR_ELx_EC_CP14_LS      (0x06)
#define ESR_ELx_EC_FP_ASIMD     (0x07)
#define ESR_ELx_EC_CP10_ID      (0x08)  /* EL2 only */
#define ESR_ELx_EC_PAC          (0x09)  /* EL2 and above */
#define ESR_ELx_EC_OTHER        (0x0A)
/* Unallocated EC: 0x0B */
#define ESR_ELx_EC_CP14_64      (0x0C)
#define ESR_ELx_EC_BTI          (0x0D)
#define ESR_ELx_EC_ILL          (0x0E)
/* Unallocated EC: 0x0F - 0x10 */
#define ESR_ELx_EC_SVC32        (0x11)
#define ESR_ELx_EC_HVC32        (0x12)  /* EL2 only */
#define ESR_ELx_EC_SMC32        (0x13)  /* EL2 and above */
/* Unallocated EC: 0x14 */
#define ESR_ELx_EC_SVC64        (0x15)
#define ESR_ELx_EC_HVC64        (0x16)  /* EL2 and above */
#define ESR_ELx_EC_SMC64        (0x17)  /* EL2 and above */
#define ESR_ELx_EC_SYS64        (0x18)
#define ESR_ELx_EC_SVE          (0x19)
#define ESR_ELx_EC_ERET         (0x1a)  /* EL2 only */
/* Unallocated EC: 0x1B */
#define ESR_ELx_EC_FPAC         (0x1C)  /* EL1 and above */
#define ESR_ELx_EC_SME          (0x1D)
/* Unallocated EC: 0x1E */
#define ESR_ELx_EC_IMP_DEF      (0x1f)  /* EL3 only */
#define ESR_ELx_EC_IABT_LOW     (0x20)
#define ESR_ELx_EC_IABT_CUR     (0x21)
#define ESR_ELx_EC_PC_ALIGN     (0x22)
/* Unallocated EC: 0x23 */
#define ESR_ELx_EC_DABT_LOW     (0x24)
#define ESR_ELx_EC_DABT_CUR     (0x25)
#define ESR_ELx_EC_SP_ALIGN     (0x26)
#define ESR_ELx_EC_MOPS         (0x27)
#define ESR_ELx_EC_FP_EXC32     (0x28)
/* Unallocated EC: 0x29 - 0x2B */
#define ESR_ELx_EC_FP_EXC64     (0x2C)
#define ESR_ELx_EC_GCS          (0x2D)
/* Unallocated EC: 0x2E */
#define ESR_ELx_EC_SERROR       (0x2F)
#define ESR_ELx_EC_BREAKPT_LOW  (0x30)
#define ESR_ELx_EC_BREAKPT_CUR  (0x31)
#define ESR_ELx_EC_SOFTSTP_LOW  (0x32)
#define ESR_ELx_EC_SOFTSTP_CUR  (0x33)
#define ESR_ELx_EC_WATCHPT_LOW  (0x34)
#define ESR_ELx_EC_WATCHPT_CUR  (0x35)
/* Unallocated EC: 0x36 - 0x37 */
#define ESR_ELx_EC_BKPT32       (0x38)
/* Unallocated EC: 0x39 */
#define ESR_ELx_EC_VECTOR32     (0x3A)  /* EL2 only */
/* Unallocated EC: 0x3B */
#define ESR_ELx_EC_BRK64        (0x3C)
/* Unallocated EC: 0x3D - 0x3F */
#define ESR_ELx_EC_MAX          (0x3F)

#define ECN(x) { ESR_ELx_EC_##x, #x }

#define kvm_arm_exception_class \
        ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \
        ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(PAC), ECN(CP14_64), \
        ECN(SVC64), ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(SVE), \
        ECN(IMP_DEF), ECN(IABT_LOW), ECN(IABT_CUR), \
        ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
        ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \
        ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \
        ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \
        ECN(BKPT32), ECN(VECTOR32), ECN(BRK64)

#endif /* ARCH_PERF_ARM64_EXCEPTION_TYPES_H */