/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
 * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5424_CMN_PLL_H
#define _DT_BINDINGS_CLK_QCOM_IPQ5424_CMN_PLL_H

/* CMN PLL core clock. */
#define IPQ5424_CMN_PLL_CLK                     0

/* The output clocks from CMN PLL of IPQ5424. */
#define IPQ5424_XO_24MHZ_CLK                    1
#define IPQ5424_SLEEP_32KHZ_CLK                 2
#define IPQ5424_PCS_31P25MHZ_CLK                3
#define IPQ5424_NSS_300MHZ_CLK                  4
#define IPQ5424_PPE_375MHZ_CLK                  5
#define IPQ5424_ETH0_50MHZ_CLK                  6
#define IPQ5424_ETH1_50MHZ_CLK                  7
#define IPQ5424_ETH2_50MHZ_CLK                  8
#define IPQ5424_ETH_25MHZ_CLK                   9
#endif