/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */

#ifndef _DT_BINDINGS_MEDIATEK_MT6359_AUXADC_H
#define _DT_BINDINGS_MEDIATEK_MT6359_AUXADC_H

/* ADC Channel Index */
#define MT6359_AUXADC_BATADC            0
#define MT6359_AUXADC_BAT_TEMP          1
#define MT6359_AUXADC_CHIP_TEMP         2
#define MT6359_AUXADC_ACCDET            3
#define MT6359_AUXADC_VDCXO             4
#define MT6359_AUXADC_TSX_TEMP          5
#define MT6359_AUXADC_HPOFS_CAL         6
#define MT6359_AUXADC_DCXO_TEMP         7
#define MT6359_AUXADC_VBIF              8
#define MT6359_AUXADC_VCORE_TEMP        9
#define MT6359_AUXADC_VPROC_TEMP        10
#define MT6359_AUXADC_VGPU_TEMP         11
#define MT6359_AUXADC_VBAT              12
#define MT6359_AUXADC_IBAT              13

#endif