/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* * Copyright (c) 2023, 2025 The Linux Foundation. All rights reserved. */ #ifndef _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H #define _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H #define EDMA_HW_RESET 0 #define NSS_CC_CE_BCR 1 #define NSS_CC_CLC_BCR 2 #define NSS_CC_EIP197_BCR 3 #define NSS_CC_HAQ_BCR 4 #define NSS_CC_IMEM_BCR 5 #define NSS_CC_MAC_BCR 6 #define NSS_CC_PPE_BCR 7 #define NSS_CC_UBI_BCR 8 #define NSS_CC_UNIPHY_BCR 9 #define UBI3_CLKRST_CLAMP_ENABLE 10 #define UBI3_CORE_CLAMP_ENABLE 11 #define UBI2_CLKRST_CLAMP_ENABLE 12 #define UBI2_CORE_CLAMP_ENABLE 13 #define UBI1_CLKRST_CLAMP_ENABLE 14 #define UBI1_CORE_CLAMP_ENABLE 15 #define UBI0_CLKRST_CLAMP_ENABLE 16 #define UBI0_CORE_CLAMP_ENABLE 17 #define NSSNOC_NSS_CSR_ARES 18 #define NSS_CSR_ARES 19 #define PPE_BTQ_ARES 20 #define PPE_IPE_ARES 21 #define PPE_ARES 22 #define PPE_CFG_ARES 23 #define PPE_EDMA_ARES 24 #define PPE_EDMA_CFG_ARES 25 #define CRY_PPE_ARES 26 #define NSSNOC_PPE_ARES 27 #define NSSNOC_PPE_CFG_ARES 28 #define PORT1_MAC_ARES 29 #define PORT2_MAC_ARES 30 #define PORT3_MAC_ARES 31 #define PORT4_MAC_ARES 32 #define PORT5_MAC_ARES 33 #define PORT6_MAC_ARES 34 #define XGMAC0_PTP_REF_ARES 35 #define XGMAC1_PTP_REF_ARES 36 #define XGMAC2_PTP_REF_ARES 37 #define XGMAC3_PTP_REF_ARES 38 #define XGMAC4_PTP_REF_ARES 39 #define XGMAC5_PTP_REF_ARES 40 #define HAQ_AHB_ARES 41 #define HAQ_AXI_ARES 42 #define NSSNOC_HAQ_AHB_ARES 43 #define NSSNOC_HAQ_AXI_ARES 44 #define CE_APB_ARES 45 #define CE_AXI_ARES 46 #define NSSNOC_CE_APB_ARES 47 #define NSSNOC_CE_AXI_ARES 48 #define CRYPTO_ARES 49 #define NSSNOC_CRYPTO_ARES 50 #define NSSNOC_NC_AXI0_1_ARES 51 #define UBI0_CORE_ARES 52 #define UBI1_CORE_ARES 53 #define UBI2_CORE_ARES 54 #define UBI3_CORE_ARES 55 #define NC_AXI0_ARES 56 #define UTCM0_ARES 57 #define NC_AXI1_ARES 58 #define UTCM1_ARES 59 #define NC_AXI2_ARES 60 #define UTCM2_ARES 61 #define NC_AXI3_ARES 62 #define UTCM3_ARES 63 #define NSSNOC_NC_AXI0_ARES 64 #define AHB0_ARES 65 #define INTR0_AHB_ARES 66 #define AHB1_ARES 67 #define INTR1_AHB_ARES 68 #define AHB2_ARES 69 #define INTR2_AHB_ARES 70 #define AHB3_ARES 71 #define INTR3_AHB_ARES 72 #define NSSNOC_AHB0_ARES 73 #define NSSNOC_INT0_AHB_ARES 74 #define AXI0_ARES 75 #define AXI1_ARES 76 #define AXI2_ARES 77 #define AXI3_ARES 78 #define NSSNOC_AXI0_ARES 79 #define IMEM_QSB_ARES 80 #define NSSNOC_IMEM_QSB_ARES 81 #define IMEM_AHB_ARES 82 #define NSSNOC_IMEM_AHB_ARES 83 #define UNIPHY_PORT1_RX_ARES 84 #define UNIPHY_PORT1_TX_ARES 85 #define UNIPHY_PORT2_RX_ARES 86 #define UNIPHY_PORT2_TX_ARES 87 #define UNIPHY_PORT3_RX_ARES 88 #define UNIPHY_PORT3_TX_ARES 89 #define UNIPHY_PORT4_RX_ARES 90 #define UNIPHY_PORT4_TX_ARES 91 #define UNIPHY_PORT5_RX_ARES 92 #define UNIPHY_PORT5_TX_ARES 93 #define UNIPHY_PORT6_RX_ARES 94 #define UNIPHY_PORT6_TX_ARES 95 #define PORT1_RX_ARES 96 #define PORT1_TX_ARES 97 #define PORT2_RX_ARES 98 #define PORT2_TX_ARES 99 #define PORT3_RX_ARES 100 #define PORT3_TX_ARES 101 #define PORT4_RX_ARES 102 #define PORT4_TX_ARES 103 #define PORT5_RX_ARES 104 #define PORT5_TX_ARES 105 #define PORT6_RX_ARES 106 #define PORT6_TX_ARES 107 #define PPE_FULL_RESET 108 #define UNIPHY0_SOFT_RESET 109 #define UNIPHY1_SOFT_RESET 110 #define UNIPHY2_SOFT_RESET 111 #define UNIPHY_PORT1_ARES 112 #define UNIPHY_PORT2_ARES 113 #define UNIPHY_PORT3_ARES 114 #define UNIPHY_PORT4_ARES 115 #define UNIPHY_PORT5_ARES 116 #define UNIPHY_PORT6_ARES 117 #define NSSPORT1_RESET 118 #define NSSPORT2_RESET 119 #define NSSPORT3_RESET 120 #define NSSPORT4_RESET 121 #define NSSPORT5_RESET 122 #define NSSPORT6_RESET 123 #endif
