addr_mask
unsigned long addr_mask;
addr_mask = PTE_RPN_MASK & ~(nbytes - 1);
hpa &= addr_mask;
kvmhv_remove_nest_rmap_list(kvm, rmap, hpa, addr_mask);
u64 offset_mask, addr_mask, hop_shift, tmp_phys_addr;
addr_mask = ~(offset_mask);
*phys_addr = (tmp_phys_addr & addr_mask) |
int addr_mask = 0x80 + 4 * ap->port_no;
pci_read_config_byte(pdev, addr_mask, &mode);
pci_write_config_byte(pdev, addr_mask, mode);
int addr_mask = 0x80 + 4 * ap->port_no;
pci_read_config_byte(pdev, addr_mask, &mode);
pci_write_config_byte(pdev, addr_mask, mode);
static int __addr_mask_to_cs_size(u32 addr_mask, u32 addr_mask_sec,
edac_dbg(1, " Primary AddrMask: 0x%x\n", addr_mask);
size = calculate_cs_size(addr_mask, cs_mode);
u32 addr_mask = 0, addr_mask_sec = 0;
addr_mask = pvt->csels[umc].csmasks[cs_mask_nr];
return __addr_mask_to_cs_size(addr_mask, addr_mask_sec, cs_mode, csrow_nr, dimm);
u32 addr_mask = pvt->csels[umc].csmasks[csrow_nr];
return __addr_mask_to_cs_size(addr_mask, addr_mask_sec, cs_mode, csrow_nr, csrow_nr >> 1);
u32 addr_mask;
#define IMU_RLC_RAM_GOLDEN_VALUE(ip, inst, reg, data, addr_mask) \
{ ip##_HWIP, inst, reg##_BASE_IDX, reg, data, addr_mask }
reg |= entry->addr_mask;
reg |= entry->addr_mask;
reg |= entry->addr_mask;
struct addr_mask DC_GPIO_DATA_MASK;
struct addr_mask DC_GPIO_DATA_A;
struct addr_mask DC_GPIO_DATA_EN;
struct addr_mask DC_GPIO_DATA_Y;
struct addr_mask GPIO_MUX_CONTROL;
struct addr_mask GPIO_MUX_STEREO_SEL;
u16 flags, u32 addr_mask, u32 ro_mask, u32 device,
.addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
u32 addr_mask;
u32 addr_mask;
addr_mask = ioread32(&hw->reg->ADDR_MASK);
iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
unsigned int addr_mask; /* MII address mask */
mac->mii.addr_mask = 0x0000F800;
mac->mii.addr_mask = GENMASK(16, 12);
mac->mii.addr_mask = 0x0000F800;
mac->mii.addr_mask = 0x0000F800;
mac->mii.addr_mask = GENMASK(25, 21);
mac->mii.addr_mask = GENMASK(20, 16);
mac->mii.addr_mask = GENMASK(20, 16);
return ((pa << mii_regs->addr_shift) & mii_regs->addr_mask) |
rt2x00dev->hw->wiphy->addr_mask[ETH_ALEN - 1] =
addr_cam->addr_mask = 0;
if (addr_cam->addr_mask != 0) {
addr_msk_start = __ffs(addr_cam->addr_mask);
le32_encode_bits(addr_cam->addr_mask, ADDR_CAM_W2_ADDR_MASK) |
u8 addr_mask : 6;
u8 addr_mask[ETH_ALEN] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x3};
ether_addr_copy(hw->wiphy->addr_mask, addr_mask);
u16 addr_mask;
error_mdata[memid].addr_mask
error_mdata[memid].addr_mask
unsigned long *addr_mask, bool write_fault)
*addr_mask = args.addr_mask;
unsigned long addr_mask;
ret = follow_fault_pfn(vma, mm, vaddr, pfn, &addr_mask,
epfn = (*pfn | (~addr_mask >> PAGE_SHIFT)) + 1;
unsigned int addr_mask, unsigned int len_mask)
if ((unsigned long)(bvec->bv_offset + skip) & addr_mask)
unsigned long addr_mask;
u8 addr_mask[ETH_ALEN];
__u8 addr_mask;
unsigned long addr_mask, bool writable,
args->pfn = pfn_base + ((args->address & ~addr_mask) >> PAGE_SHIFT);
args->addr_mask = addr_mask;
if ((skcb->addr.sa & f->addr_mask) != f->addr)
f->addr &= f->addr_mask;
if (is_zero_ether_addr(local->hw.wiphy->addr_mask))
m = local->hw.wiphy->addr_mask;
if (is_zero_ether_addr(local->hw.wiphy->addr_mask) &&
if (is_zero_ether_addr(local->hw.wiphy->addr_mask))
m = local->hw.wiphy->addr_mask;
union nf_inet_addr addr = {}, addr_mask;
nf_inet_addr_mask(&addr, &addr_mask, &t->mask);
e = recent_entry_lookup(t, &addr_mask, xt_family(par),
e = recent_entry_init(t, &addr_mask, xt_family(par), ttl);
if (!is_zero_ether_addr(rdev->wiphy.addr_mask) &&
rdev->wiphy.addr_mask))
SHOW_FMT(address_mask, "%pM", wiphy.addr_mask);
addr_mask = ~((emu->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK) >> 16);
if (snd_BUG_ON(reg & addr_mask)) // Only raw registers supported here
u32 addr_mask;