arch/alpha/include/asm/machvec.h

76

void (*ack_irq)(unsigned long);

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h

295

struct amdgpu_irq_src ack_irq;

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c

404

adev->virt.ack_irq.num_types = 1;

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c

405

adev->virt.ack_irq.funcs = &xgpu_ai_mailbox_ack_irq_funcs;

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c

418

r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq);

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c

434

r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0);

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c

449

amdgpu_irq_put(adev, &adev->virt.ack_irq, 0);

drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c

495

adev->virt.ack_irq.num_types = 1;

drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c

496

adev->virt.ack_irq.funcs = &xgpu_nv_mailbox_ack_irq_funcs;

drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c

509

r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq);

drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c

525

r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0);

drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c

540

amdgpu_irq_put(adev, &adev->virt.ack_irq, 0);

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

580

adev->virt.ack_irq.num_types = 1;

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

581

adev->virt.ack_irq.funcs = &xgpu_vi_mailbox_ack_irq_funcs;

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

594

r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 138, &adev->virt.ack_irq);

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

610

r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0);

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

623

amdgpu_irq_put(adev, &adev->virt.ack_irq, 0);

drivers/mailbox/hi3660-mailbox.c

107

writel(BIT(mchan->ack_irq), base + MBOX_ICLR_REG);

drivers/mailbox/hi3660-mailbox.c

144

writel(BIT(mchan->ack_irq), base + MBOX_SRC_REG);

drivers/mailbox/hi3660-mailbox.c

148

if (val & BIT(mchan->ack_irq))

drivers/mailbox/hi3660-mailbox.c

202

writel(BIT(mchan->ack_irq), base + MBOX_SEND_REG);

drivers/mailbox/hi3660-mailbox.c

225

mchan->ack_irq = spec->args[2];

drivers/mailbox/hi3660-mailbox.c

58

unsigned int ack_irq;

drivers/mailbox/hi6220-mailbox.c

187

writel(BIT(mchan->ack_irq), ACK_INT_CLR_REG(mbox->ipc));

drivers/mailbox/hi6220-mailbox.c

202

writel(BIT(mchan->ack_irq), ACK_INT_ENA_REG(mbox->ipc));

drivers/mailbox/hi6220-mailbox.c

212

writel(BIT(mchan->ack_irq), ACK_INT_DIS_REG(mbox->ipc));

drivers/mailbox/hi6220-mailbox.c

213

mbox->irq_map_chan[mchan->ack_irq] = NULL;

drivers/mailbox/hi6220-mailbox.c

231

unsigned int ack_irq = spec->args[2];

drivers/mailbox/hi6220-mailbox.c

235

ack_irq >= mbox->chan_num) {

drivers/mailbox/hi6220-mailbox.c

238

i, dst_irq, ack_irq);

drivers/mailbox/hi6220-mailbox.c

244

if (mbox->irq_map_chan[ack_irq] == (void *)chan) {

drivers/mailbox/hi6220-mailbox.c

251

mchan->ack_irq = ack_irq;

drivers/mailbox/hi6220-mailbox.c

253

mbox->irq_map_chan[ack_irq] = (void *)chan;

drivers/mailbox/hi6220-mailbox.c

62

unsigned int dir, dst_irq, ack_irq;

drivers/media/pci/cx18/cx18-mailbox.c

386

u32 ack_irq, req;

drivers/media/pci/cx18/cx18-mailbox.c

390

ack_irq = IRQ_EPU_TO_APU_ACK;

drivers/media/pci/cx18/cx18-mailbox.c

394

ack_irq = IRQ_EPU_TO_CPU_ACK;

drivers/media/pci/cx18/cx18-mailbox.c

413

cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq);

drivers/misc/ocxl/link.c

186

ack_irq(spa, r);

drivers/misc/ocxl/link.c

214

ack_irq(spa, ADDRESS_ERROR);

drivers/misc/ocxl/link.c

233

ack_irq(spa, ADDRESS_ERROR);

drivers/misc/ocxl/link.c

244

ack_irq(spa, ADDRESS_ERROR);

drivers/misc/ocxl/link.c

261

ack_irq(spa, ADDRESS_ERROR);