__bf_shf
.val = 0b00UL << __bf_shf(KVM_PTE_LEAF_ATTR_HI_S2_XN),
.val = 0b01UL << __bf_shf(KVM_PTE_LEAF_ATTR_HI_S2_XN),
.val = 0b10UL << __bf_shf(KVM_PTE_LEAF_ATTR_HI_S2_XN),
.val = 0b11UL << __bf_shf(KVM_PTE_LEAF_ATTR_HI_S2_XN),
__bf_shf(IEC958_SUBFRAME_PARITY));
__bf_shf(IEC958_SUBFRAME_CHANNEL_STATUS));
__bf_shf(IEC958_SUBFRAME_USER_DATA));
__bf_shf(IEC958_SUBFRAME_VALIDITY));
__bf_shf(IEC958_SUBFRAME_SAMPLE_24_MASK));
__bf_shf(IEC958_SUBFRAME_PREAMBLE_MASK));
return etm4_get_access_type(config) << __bf_shf(TRCVICTLR_EXLEVEL_MASK);
config->addr_acc[idx] |= val << __bf_shf(TRCACATRn_CONTEXT_MASK);
if (val & ~(TRCACATRn_EXLEVEL_MASK >> __bf_shf(TRCACATRn_EXLEVEL_MASK)))
config->addr_acc[idx] |= val << __bf_shf(TRCACATRn_EXLEVEL_MASK);
config->cfg |= mode << __bf_shf(TRCCONFIGR_COND_MASK);
val &= TRCVICTLR_EVENT_MASK >> __bf_shf(TRCVICTLR_EVENT_MASK);
config->vinst_ctrl |= val << __bf_shf(TRCVICTLR_EXLEVEL_S_MASK);
config->vinst_ctrl |= val << __bf_shf(TRCVICTLR_EXLEVEL_NS_MASK);
code = pts->entry >> (__bf_shf(AMDV1PT_FMT_OA) - 1 +
val = (buf[i] - '0') << __bf_shf(LP55xx_FADER_MAPPING_MASK);
*shift = __bf_shf(KSZ8_PORT_BASED_PRIO_M);
*shift = __bf_shf(KSZ9477_PORT_BASED_PRIO_M);
__bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK);
__bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK);
return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask));
int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY);
int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE);
int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY);
int bit = __bf_shf(MV88E6185_G1_CTL1_RELOAD_EEPROM);
int bit = __bf_shf(MV88E6XXX_G1_ATU_OP_BUSY);
int bit = __bf_shf(MV88E6XXX_G1_VTU_OP_BUSY);
int bit = __bf_shf(MV88E6XXX_G2_IRL_CMD_BUSY);
int bit = __bf_shf(MV88E6XXX_G2_PVT_ADDR_BUSY);
int bit = __bf_shf(MV88E6XXX_G2_EEPROM_CMD_BUSY);
bit = __bf_shf(MV88E6XXX_G2_EEPROM_CMD_RUNNING);
int bit = __bf_shf(MV88E6XXX_G2_SMI_PHY_CMD_BUSY);
dev <<= __bf_shf(MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK);
int bit = __bf_shf(MV88E6352_G2_AVB_CMD_BUSY);
int bit = __bf_shf(MV88E6393X_PORT_EPC_CMD_BUSY);
(ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) |
*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_DA_MASK);
*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_SA_MASK);
*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VTU_MASK);
*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK);
*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK);
*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK);
*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK);
*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_UDP_MASK);
int bit = __bf_shf(MV88E6XXX_PORT_RESERVED_1A_BUSY);
int bit = __bf_shf(MV88E6XXX_TCAM_OP_BUSY);
addr_lo = addr & (OP_BR_ADDR_LO >> __bf_shf(OP_BR_ADDR_LO));
addr_lo = addr & (OP_BR_BIT_ADDR_LO >> __bf_shf(OP_BR_BIT_ADDR_LO));
return (addr_hi * ((OP_BR_ADDR_LO >> __bf_shf(OP_BR_ADDR_LO)) + 1)) |
addr_lo = offset & (OP_BR_ADDR_LO >> __bf_shf(OP_BR_ADDR_LO));
nfp_eth_set_bit_config(nsp, raw_idx, mask, __bf_shf(mask), \
ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK);
ss_mask.speed_shift = __bf_shf(AT803X_SS_SPEED_MASK);
__bf_shf(IEEE80211_EML_CAP_EML_PADDING_DELAY) | \
__bf_shf(IEEE80211_EML_CAP_EML_TRANSITION_DELAY))
__bf_shf(IEEE80211_EML_CAP_EML_PADDING_DELAY) | \
__bf_shf(IEEE80211_EML_CAP_EML_TRANSITION_DELAY))
_DEF_GPIO(OMNIA_CMD_GET_STATUS_WORD, 0, __bf_shf(OMNIA_STS_ ## _name), \
0, __bf_shf(OMNIA_INT_ ## _name), 0, 0)
__bf_shf(OMNIA_STS_ ## _name), __bf_shf(OMNIA_CTL_ ## _name), \
__bf_shf(OMNIA_EXT_STS_ ## _name), 0, \
__bf_shf(OMNIA_INT_ ## _name), \
__bf_shf(OMNIA_EXT_STS_ ## _name), 0, \
__bf_shf(OMNIA_INT_ ## _name), \
__bf_shf(OMNIA_EXT_STS_ ## _name), 0, \
__bf_shf(OMNIA_INT_ ## _name), \
__bf_shf(OMNIA_EXT_CTL_ ## _name), \
__bf_shf(OMNIA_EXT_CTL_ ## _name), -1, \
_DEF_GPIO(0, 0, 0, 0, __bf_shf(OMNIA_INT_ ## _name), 0, 0)
[__bf_shf(OMNIA_INT_CARD_DET)] = 4,
[__bf_shf(OMNIA_INT_MSATA_IND)] = 5,
[__bf_shf(OMNIA_INT_USB30_OVC)] = 6,
[__bf_shf(OMNIA_INT_USB31_OVC)] = 7,
[__bf_shf(OMNIA_INT_BUTTON_PRESSED)] = 12,
[__bf_shf(OMNIA_INT_TRNG)] = 13,
[__bf_shf(OMNIA_INT_MESSAGE_SIGNED)] = 14,
[__bf_shf(OMNIA_INT_SFP_nDET)] = 16,
[__bf_shf(OMNIA_INT_BRIGHTNESS_CHANGED)] = 11,
[__bf_shf(OMNIA_INT_WLAN0_MSATA_LED)] = 28,
[__bf_shf(OMNIA_INT_WLAN1_LED)] = 29,
[__bf_shf(OMNIA_INT_WLAN2_LED)] = 30,
[__bf_shf(OMNIA_INT_WPAN0_LED)] = 31,
[__bf_shf(OMNIA_INT_WPAN1_LED)] = 32,
[__bf_shf(OMNIA_INT_WPAN2_LED)] = 33,
[__bf_shf(OMNIA_INT_WAN_LED0)] = 34,
[__bf_shf(OMNIA_INT_WAN_LED1)] = 35,
[__bf_shf(OMNIA_INT_LAN0_LED0)] = 36,
[__bf_shf(OMNIA_INT_LAN0_LED1)] = 37,
[__bf_shf(OMNIA_INT_LAN1_LED0)] = 38,
[__bf_shf(OMNIA_INT_LAN1_LED1)] = 39,
[__bf_shf(OMNIA_INT_LAN2_LED0)] = 40,
[__bf_shf(OMNIA_INT_LAN2_LED1)] = 41,
[__bf_shf(OMNIA_INT_LAN3_LED0)] = 42,
[__bf_shf(OMNIA_INT_LAN3_LED1)] = 43,
[__bf_shf(OMNIA_INT_LAN4_LED0)] = 44,
[__bf_shf(OMNIA_INT_LAN4_LED1)] = 45,
[__bf_shf(OMNIA_INT_LAN5_LED0)] = 46,
[__bf_shf(OMNIA_INT_LAN5_LED1)] = 47,
div->shift = __bf_shf(CFG_CLK_DIV);
dws->dfs_offset = __bf_shf(DW_PSSI_CTRLR0_DFS32_MASK);
#define TPS_FIELD_GET(_mask, _reg) ((typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)))
((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
((u16)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
(typeof(_mask))((_mask) >> __bf_shf(_mask)); \
!((((typeof(_mask))_val) << __bf_shf(_mask)) & ~(_mask)); \
BUILD_BUG_ON_ZERO(~((_mask) >> __bf_shf(_mask)) & (_val)) + \
__BF_CHECK_POW2((_mask) + (1ULL << __bf_shf(_mask))) + \
(((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask)) \
*(_reg_p) |= (((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask)); \
~((_mask) >> __bf_shf(_mask)) & \
(1ULL << __bf_shf(_mask))); \
((typeof(mask))(val) << __bf_shf(mask)) & (mask); \
(typeof(mask))(((reg) & (mask)) >> __bf_shf(mask)); \
(((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) | \
__bf_shf(SSM3515_GEC_ANA_GAIN),
__bf_shf(SSM3515_GEC_EDGE), 1, 0),
__bf_shf(SSM3515_DAC_HV), 1, 1),
__bf_shf(SSM3515_DAC_HPF), 1, 0),
__bf_shf(SSM3515_SAI1_DAC_POL), 1, 0),
((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \
(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
(1ULL << __bf_shf(_mask))); \
(typeof(_mask))((_mask) >> __bf_shf(_mask)); \
!((((typeof(_mask))_val) << __bf_shf(_mask)) & ~(_mask)); \