drivers/gpu/drm/i915/display/i9xx_wm.c

186

_MASKED_BIT_DISABLE(FW_BLC_SELF_EN);

drivers/gpu/drm/i915/display/i9xx_wm.c

197

_MASKED_BIT_DISABLE(INSTPM_SELF_EN);

drivers/gpu/drm/i915/display/intel_display_irq.c

1631

_MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));

drivers/gpu/drm/i915/gt/intel_engine_cs.c

1695

ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));

drivers/gpu/drm/i915/gt/intel_engine_pm.c

27

_MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

2942

ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));

drivers/gpu/drm/i915/gt/intel_lrc.c

850

ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);

drivers/gpu/drm/i915/gt/intel_lrc.c

854

ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |

drivers/gpu/drm/i915/gt/intel_rc6.c

770

_MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));

drivers/gpu/drm/i915/gt/intel_reset.c

605

_MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));

drivers/gpu/drm/i915/gt/intel_ring_submission.c

1077

_MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));

drivers/gpu/drm/i915/gt/intel_ring_submission.c

277

RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));

drivers/gpu/drm/i915/gt/intel_ring_submission.c

823

*cs++ = _MASKED_BIT_DISABLE(

drivers/gpu/drm/i915/gt/intel_workarounds.c

313

wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);

drivers/gpu/drm/i915/gt/intel_workarounds.c

319

wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

4419

ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));

drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c

1078

intel_uncore_write_fw(uncore, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags));

drivers/gpu/drm/i915/gvt/handlers.c

2142

else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))

drivers/gpu/drm/i915/gvt/reg.h

96

((_val) & _MASKED_BIT_DISABLE(_b))

drivers/gpu/drm/i915/i915_perf.c

2952

_MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE));

drivers/gpu/drm/i915/i915_perf.c

2954

_MASKED_BIT_DISABLE(GEN12_DISABLE_DOP_GATING));

drivers/gpu/drm/i915/intel_clock_gating.c

670

_MASKED_BIT_DISABLE(ECO_FLIP_DONE));

drivers/gpu/drm/i915/intel_clock_gating.c

689

_MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));

drivers/gpu/drm/i915/intel_uncore.c

136

#define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)

drivers/gpu/drm/i915/pxp/intel_pxp.c

70

_MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES);

drivers/gpu/drm/xe/xe_eu_stall.c

445

write_ptr_reg = _MASKED_BIT_DISABLE(XEHPC_EUSTALL_REPORT_OVERFLOW_DROP);

drivers/gpu/drm/xe/xe_eu_stall.c

833

_MASKED_BIT_DISABLE(DISABLE_DOP_GATING));

drivers/gpu/drm/xe/xe_hw_engine.c

344

_MASKED_BIT_DISABLE(STOP_RING));

drivers/gpu/drm/xe/xe_oa.c

827

_MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE));

drivers/gpu/drm/xe/xe_oa.c

829

_MASKED_BIT_DISABLE(DISABLE_DOP_GATING));

drivers/gpu/drm/xe/xe_pxp.c

316

_MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES);

drivers/gpu/drm/xe/xe_uc_fw.c

894

xe_mmio_write32(mmio, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags));